High-precision under-voltage protection circuit

Abstract

The invention discloses a high-precision under-voltage protection circuit, which comprises a configuration circuit and a comparison circuit, and is characterized in that the configuration circuit is used for capturing the change condition of the difference between the input voltage and the output voltage of a chip, and controlling an under-voltage threshold value by setting a compensation current; the comparison circuit is used for detecting and amplifying the difference between the input voltage and the output voltage of the chip. The under-voltage protection circuit detects a difference value between an input voltage and an output voltage and compares the difference value with a set under-voltage threshold value to realize a control function on the circuit, and when the input voltage and the output voltage fluctuate in a normal range, the under-voltage protection circuit outputs a low level; when the difference value between the input voltage and the output voltage is larger than the under-voltage threshold value, it is considered that load overload or output short-circuit grounding faults occur, the output of the under-voltage protection circuit is high level, the control circuit is switched off, and the problem of circuit damage caused by under-voltage in the using process of the analog integrated circuit is solved.

Description

Technical Field

[0001] The invention relates to an input and output undervoltage protection circuit, in particular to a high-precision undervoltage protection circuit. Background Art

[0002] With the rapid development of semiconductor technology, analog integrated chips are increasingly widely used. Power chips are the core of the electronics industry and the foundation of the information industry. They are widely used in analog switches, power control, protection ICs, drivers, sensors and other systems. The design and research of power chip protection has gradually become a hot research point. When in an undervoltage state, some modules inside the chip will be in an abnormal working state, which will cause the entire system to work disorderly and even cause a certain degree of damage to the chip, with potential risks of accidents. Therefore, when an undervoltage fault occurs, the chip should accurately identify and control the circuit to shut down.

[0003] Undervoltage protection circuits are widely used in analog switches, power control, protection ICs, drivers and sensors, and have broad application prospects in automotive electronics, industrial control and other fields. However, due to the high reliability and high precision requirements of power protection chips, the research and design of power protection chips are challenging. Most existing undervoltage protection circuits use passive resistor array voltage division to set the voltage threshold, and then use a comparator for voltage comparison. This structure has great disadvantages: on the one hand, a large number of resistor devices will occupy a large layout area, which is not conducive to on-chip integration; on the other hand, the flip threshold and hysteresis of the undervoltage protection circuit of the resistor voltage division depend on the proportional relationship of the resistor string voltage division. The layout implementation of a large number of resistors brings serious layout non-ideal effects, making it difficult to ensure high precision. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art and propose a high-precision undervoltage protection circuit, which solves the problem of circuit damage caused by undervoltage during the use of analog integrated chips by configuring the design of circuits and comparison circuits.

[0005] The technical solution of the present invention is:

[0006] A high-precision undervoltage protection circuit includes a configuration circuit and a comparison circuit:

[0007] A configuration circuit is used to capture the change of the difference between the chip input and output voltages; the configuration circuit includes a resistor R1, a resistor R2, an NMOS tube M1, an NMOS tube M2 and a bias current circuit; one end of the resistor R1 is connected to the chip input voltage port, and the other end is connected to one end of the resistor R2 and to the drain of the NMOS tube M1, and the other end of the resistor R2 is connected to the bias current circuit; the source of the NMOS tube M1 is connected to the drain of the NMOS tube M2, the gate of the NMOS tube M1 is connected to the drain to form a diode connection, and the source and drain of M1 are respectively connected to the comparison circuit; the source of the NMOS tube M2 is connected to the chip output port, and the gate is connected to the external control potential; the bases of the NMOS tubes M1 and M2 are both grounded;

[0008] A comparison circuit is used to detect and amplify the change of the difference between the two input terminals; the comparison circuit is provided with two input terminals, a positive input terminal and a negative input terminal, which are respectively connected to the source and drain of the NMOS tube M1;

[0009] When the difference between the chip input voltage and output voltage is higher than the undervoltage threshold, the comparison circuit outputs a high level, determining that the chip is overloaded or the output is short-circuited to ground, and the control chip circuit is shut down to form undervoltage protection.

[0010] Further, the comparison circuit includes a comparator and an inverter; the comparator includes an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, an NMOS tube M10, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, and a PMOS tube M9;

[0011] The source of the PMOS tube M3 is connected to the chip power supply voltage, the gate is connected to the gate of the PMOS tube M9, and the drain is connected to the source of the PMOS tube M4 and the PMOS tube M5;

[0012] The gate of the PMOS tube M4 is connected to the drain of the NMOS tube M1, and the gate of the PMOS tube M5 is connected to the source of the NMOS tube M1; the drain of the PMOS tube M4 is connected to the drain of the NMOS tube M6 and to the gate of M6, the gate of the NMOS tube M6 is connected to the gate of the NMOS tube M7, and the drain of the NMOS tube M7 is connected to the drain of M5 and to the gate of the NMOS tube M10;

[0013] The source of the NMOS tube M6 is connected to the source of the NMOS tube M7 and to the drain of the NMOS tube M8. The source of the NMOS tube M8 is connected to the ground line, and the gate of the NMOS tube M8 is externally connected to a bias voltage.

[0014] The source of NMOS tube M9 is connected to the chip power supply voltage, and the drain of M9 is connected to the drain of NMOS tube M10, and the signal of the undervoltage protection circuit is output after rectification by the inverter;

[0015] The source of the NMOS tube M10 is connected to the ground wire, the bases of the NMOS tubes M6, M7, M8, and M10 are all connected to the ground wire, and the bases of the PMOS tubes M3, M4, M5, and M9 are all connected to the power supply voltage.

[0016] Furthermore, the bias current circuit copies the reference current connected to regenerate the current I required by the configuration circuit. UV_IB , NMOS tube M1 electrical characteristics V DS =V GS , that is, V DS >V TH1 When NMOS tube M1 is unidirectional and works in saturation region, V TH1 is the transistor threshold of the NMOS tube M1.

[0017] Furthermore, when the chip is working normally, the chip output port voltage VOUT is large and there is no undervoltage phenomenon, that is, VIN-VOUT-(I UV_IB ×R1)<0<V TH1 , VIN is the voltage of the chip input port; according to the conduction condition of NMOS tube M1, NMOS tube M1 is reverse biased and cut off; the negative terminal voltage of the comparison circuit is equal to VIN-I UV_IB ×R1, the positive terminal voltage is equal to VOUT, VOUT>V X , the comparison circuit outputs a low level.

[0018] Furthermore, when VIN-VOUT is higher than the undervoltage threshold, VIN-VOUT-(I UV_IB ×R1)>V TH1 When M1 is turned on, the voltage between the negative and positive sides of the comparison circuit is equal to the diode conduction voltage V DS >V TH1 >0, the comparison circuit outputs a high level to achieve undervoltage reversal.

[0019] Furthermore, by setting the compensation current I UV_IB and the resistance value of resistor R1 to set the undervoltage threshold I UV_IB ×R1, to achieve the adjustable design of high-precision undervoltage threshold.

[0020] Furthermore, when the chip output port voltage VOUT changes from large to small, it must meet the following conditions:

[0021] VIN-(I M1 +I UV_IB )×R1-V TH1 =VOUT

[0022] The output level of the comparison circuit is flipped, VIN is the voltage of the chip input port, I UV_IB The bias current circuit copies the reference current to generate the current required by the configuration circuit, V TH1is the transistor threshold of NMOS tube M1, I M1 is the saturation leakage current of NMOS tube M1.

[0023] Furthermore, when the chip output port VOUT changes from small to large, VIN-I UV_IB ×R1-V TH1 =VOUT, the comparison circuit output level flips, VIN is the chip input port voltage, I UV_IB The bias current circuit copies the reference current to generate the current required by the configuration circuit, V TH1 is the transistor threshold of the NMOS tube M1.

[0024] Furthermore, by designing the size of the NMOS tube M1 to control the saturation leakage current of the NMOS tube M1, the undervoltage hysteresis I M1 ×R1, realize millivolt-level undervoltage hysteresis adjustable design, I M1 is the saturation leakage current of NMOS tube M1.

[0025] The advantages of the present invention compared with the prior art are:

[0026] The present invention controls the on and off of the protection chip circuit by comparing the size of VIN-VOUT with the undervoltage threshold, thereby realizing undervoltage protection for the chip. The present invention is not only simple in structure and low in cost, but also can realize high-precision control of the undervoltage threshold and undervoltage hysteresis, and can effectively solve the problem of circuit damage caused by undervoltage during the use of the power protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0028] Figure 1 is a circuit diagram of an undervoltage protection circuit according to an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of the composition of an undervoltage protection circuit according to an embodiment of the present invention;

[0030] Figure 3 1 is a simulation curve diagram showing the variation of the undervoltage indication voltage with VIN-VOUT according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0032] The present invention proposes a high-precision undervoltage protection circuit, which plays a vital role in many analog integrated circuits such as power switches and drivers. When the circuit works normally, the input-output voltage difference should fluctuate within a small range within the normal range. Undervoltage will cause the circuit performance to decline or even fail to work normally. If no protective measures are taken, some functions in the system will be disordered, and there is a potential risk of accidents. Therefore, when an undervoltage fault occurs, the chip should accurately identify and control the circuit to shut down. The undervoltage protection circuit proposed by the present invention considers that a load overload or an output short-to-ground fault occurs when VIN-VOUT is higher than the undervoltage threshold, and the control circuit is shut down to form undervoltage protection.

[0033] The high-precision undervoltage protection circuit includes a configuration circuit and a comparison circuit, such as Figure 2 As shown, the configuration circuit is used to capture the change of the difference between the input and output voltages of the chip, and the comparison circuit is used to detect and amplify the change of the difference between the input and output voltages.

[0034] like Figure 1 As shown, the configuration circuit includes resistors R1, R2, NMOS tubes M1, M2, and a bias current circuit. The first end of the resistor R1 is electrically connected to the input voltage port, and the second end of the resistor R1 is electrically connected to the second end of the resistor R2 and to the drain of the NMOS tube M1. The first end of the resistor R2 is electrically connected to the bias current I UV_IB The source of NMOS tube M1 is electrically connected to the drain of NMOS tube M2, and the source of M2 is electrically connected to the output port. The gate of NMOS tube M1 is connected to the drain to form a diode connection. The gate of M2 is connected to the external control potential to control the on and off of the circuit. The source and drain of M1 are electrically connected to the positive and negative input terminals of the comparator respectively, and the bases of NMOS tubes M1 and M2 are both grounded.

[0035] The current bias module copies the reference current connected to regenerate the current I required by the configuration circuit. UV_IB The first MOS tube M1 is a diode connection device composed of NMOS gate and drain connected, and its electrical characteristic V DS =V GS That is V DS >V TH1 The MOS tube is unidirectionally conducted and operates in the saturation region.

[0036] The comparison circuit includes NMOS tubes M6, M7, M8, M10, and PMOS tubes M3, M4, M5, M9. The source of M3 is connected to the chip power supply voltage, the drain of M3 is connected to the sources of M4 and M5, the gate of M3 is connected to the gate of M9, the gate of M4 is connected to the drain of M1, the gate of M5 is connected to the source of M1, the drain of M4 is connected to the drain of M6 and to the gate of M6, the gate of M6 is connected to the gate of M7, the drain of M7 is connected to the drain of M5 and to the gate of M10, the source of M6 is connected to the source of M7 and to the drain of M8, the source of M8 is connected to the ground line, the gate of M8 is externally connected to the bias voltage, the source of M9 is connected to the chip power supply voltage, the drain of M9 is connected to the drain of M10 as a comparison circuit for outputting the signal of the undervoltage protection circuit, the source of M10 is connected to the ground line, the bases of NMOS tubes M6, M7, M8 and M10 are all connected to the ground line, and the bases of PMOS tubes M3, M4, M5 and M9 are all connected to the power supply voltage.

[0037] The voltage difference between the input voltage and the output voltage of this circuit is detected. When the input voltage and the output voltage fluctuate within the normal range, the undervoltage protection circuit outputs a low level; when VIN-VOUT is greater than the undervoltage threshold, it is considered that a load overload or an output short-circuit grounding fault has occurred, the undervoltage protection module outputs a high level, and the control circuit is shut down.

[0038] The circuit sets the compensation current I UV_IB and the resistance value of resistor R1 to set the comparison circuit flip threshold I UB_IB ×R1, realizing the adjustable design of high-precision undervoltage threshold. The circuit controls the saturation leakage current of M1 by designing the size of M1 and setting the undervoltage hysteresis I M1 ×R1, realizing the millivolt-level undervoltage hysteresis adjustable design.

[0039] When the system is operating normally, VOUT is large and there is no undervoltage. That is, VIN-VOUT-(I UV_IB ×R1)<0<V TH1 According to the conduction condition of M1, M1 is reverse biased and cut off. The positive and negative ends of the comparator are connected to the source and drain of M1 respectively. The negative terminal voltage of the comparator is equal to the X node voltage V X =VIN-I UV_IB ×R1, the positive terminal voltage is equal to VOUT, VOUT>V X The comparator outputs a high level, and after being rectified by the inverter, it outputs a low level. When VIN-VOUT is higher than the undervoltage threshold, it is considered that a load overload or output short-to-ground fault occurs, that is, VIN-VOUT-(I UV_IB ×R1)>V TH1 When M1 is turned on, the voltage between the negative and positive terminals of the comparator is equal to the diode conduction voltage VDS>V TH1 >0, the comparator outputs a low level, and after being rectified by the inverter, it outputs a high level, thus realizing the undervoltage flip of the circuit.TH1 is the transistor threshold of the NMOS tube M1.

[0040] When VOUT changes from large to small, VIN-(I M1 +I UV_IB )×R1-V TH1 = VOUT comparator flips; when VOUT changes from small to large, VIN-I UV_IB ×R1-V TH1 = VOUT comparator flips, realizing the hysteresis function of the undervoltage protection circuit, and accurately controls the hysteresis I by controlling the saturation leakage current of M1 M1 ×The size of R1.

[0041] The overall simulation results of the high-precision undervoltage circuit are as follows: Figure 3 As shown, the horizontal axis is VIN-VOUT, the vertical axis is the voltage, the undervoltage threshold is set to 600mV, the hysteresis is set to 120mV, the simulation condition is VIN=6.5V, and the tt process is at room temperature. The simulation results show that when VOUT changes from large to small, that is, when VIN-VOUT changes from left to right along the horizontal axis to 600mV, the output flips from a low potential to a high potential; when VOUT changes from small to large, that is, when VIN-VOUT changes from right to left along the horizontal axis to 480mV, the output flips from a high potential to a low potential.

[0042] The above-described embodiments are only preferred specific implementations of the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-precision undervoltage protection circuit, characterized in that: Including configuration circuit and comparison circuit: A configuration circuit is used to capture the change of the difference between the chip input and output voltages; the configuration circuit includes a resistor R1, a resistor R2, an NMOS tube M1, an NMOS tube M2 and a bias current circuit; one end of the resistor R1 is connected to the chip input voltage port, and the other end is connected to one end of the resistor R2 and to the drain of the NMOS tube M1, and the other end of the resistor R2 is connected to the bias current circuit; the source of the NMOS tube M1 is connected to the drain of the NMOS tube M2, the gate of the NMOS tube M1 is connected to the drain to form a diode connection, and the source and drain of M1 are respectively connected to the comparison circuit; the source of the NMOS tube M2 is connected to the chip output port, and the gate is connected to the external control potential; the bases of the NMOS tubes M1 and M2 are both grounded; A comparison circuit is used to detect and amplify the change of the difference between the two input terminals; the comparison circuit is provided with two input terminals, a positive input terminal and a negative input terminal, which are respectively connected to the source and drain of the NMOS tube M1; When the difference between the chip input voltage and output voltage is higher than the undervoltage threshold, the comparison circuit outputs a high level, determining that the chip is overloaded or the output is short-circuited to ground, and the control chip circuit is shut down to form undervoltage protection.

2. A high-precision undervoltage protection circuit according to claim 1, characterized in that: The comparison circuit includes a comparator and an inverter; the comparator includes an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, an NMOS tube M10, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, and a PMOS tube M9; The source of the PMOS tube M3 is connected to the chip power supply voltage, the gate is connected to the gate of the PMOS tube M9, and the drain is connected to the source of the PMOS tube M4 and the PMOS tube M5; The gate of the PMOS tube M4 is connected to the drain of the NMOS tube M1, and the gate of the PMOS tube M5 is connected to the source of the NMOS tube M1; the drain of the PMOS tube M4 is connected to the drain of the NMOS tube M6 and to the gate of M6, the gate of the NMOS tube M6 is connected to the gate of the NMOS tube M7, and the drain of the NMOS tube M7 is connected to the drain of M5 and to the gate of the NMOS tube M10; The source of the NMOS tube M6 is connected to the source of the NMOS tube M7 and to the drain of the NMOS tube M8. The source of the NMOS tube M8 is connected to the ground line, and the gate of the NMOS tube M8 is externally connected to a bias voltage. The source of NMOS tube M9 is connected to the chip power supply voltage, and the drain of M9 is connected to the drain of NMOS tube M10, and the signal of the undervoltage protection circuit is output after rectification by the inverter; The source of the NMOS tube M10 is connected to the ground wire, the bases of the NMOS tubes M6, M7, M8, and M10 are all connected to the ground wire, and the bases of the PMOS tubes M3, M4, M5, and M9 are all connected to the power supply voltage.

3. The high-precision undervoltage protection circuit according to claim 1, characterized in that: The bias current circuit copies the reference current connected to regenerate the current I required by the configuration circuit. UV_IB , NMOS tube M1 electrical characteristics V DS =V GS , that is, V DS >V TH1 When NMOS tube M1 is unidirectional and works in saturation region, V TH1 is the transistor threshold of the NMOS tube M1.

4. A high-precision undervoltage protection circuit according to claim 3, characterized in that: When the chip is working normally, the chip output port voltage VOUT is large and there is no undervoltage phenomenon, that is, VIN-VOUT-(I UV_IB ×R1)<0<V TH1 , VIN is the voltage of the chip input port; according to the conduction condition of NMOS tube M1, NMOS tube M1 is reverse biased and cut off; the negative terminal voltage of the comparison circuit is equal to VIN-I UV_IB ×R1, the positive terminal voltage is equal to VOUT, VOUT>V X , the comparison circuit outputs a low level.

5. The high-precision undervoltage protection circuit according to claim 3, characterized in that: When VIN-VOUT is higher than the undervoltage threshold, VIN-VOUT-(I UV_IB ×R1)>V TH1 When M1 is turned on, the voltage between the negative and positive sides of the comparison circuit is equal to the diode conduction voltage V DS >V TH1 >0, the comparison circuit outputs a high level to achieve undervoltage reversal.

6. A high-precision undervoltage protection circuit according to claim 3, characterized in that: By setting the compensation current I UV_IB and the resistance value of resistor R1 to set the undervoltage threshold I UV_IB ×R1, to achieve the adjustable design of high-precision undervoltage threshold.

7. The high-precision undervoltage protection circuit according to claim 1, characterized in that: When the chip output port voltage VOUT changes from large to small, it must meet VIN-(I M1 +I UV_IB )×R1-V TH1 =VOUT, the comparison circuit output level flips, VIN is the chip input port voltage, I UV_IB The bias current circuit copies the reference current to generate the current required by the configuration circuit, V TH1 is the transistor threshold of NMOS tube M1, I M1 is the saturation leakage current of NMOS tube M1.

8. The high-precision undervoltage protection circuit according to claim 1, characterized in that: When the chip output port VOUT changes from small to large, it must meet the VIN-I UV_IB ×R1-V TH1 =VOUT, the comparison circuit output level flips, VIN is the chip input port voltage, I UV_IB The bias current circuit copies the reference current to generate the current required by the configuration circuit, V TH1 is the transistor threshold of the NMOS tube M1.

9. A high-precision undervoltage protection circuit according to claim 7 or 8, characterized in that: By designing the size of NMOS tube M1 to control the saturation leakage current of NMOS tube M1, the undervoltage hysteresis I M1 ×R1, realize millivolt-level undervoltage hysteresis adjustable design, I M1 is the saturation leakage current of NMOS tube M1.

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