Intelligent power module

Abstract

The invention relates to the technical field of intelligent power modules, and provides an intelligent power module. Comprising a first input stage circuit, a second input stage circuit, a double-level bootstrap circuit, a dead zone generation circuit, a pulse generation circuit, a first level shift circuit, a first output circuit, a low-side delay circuit, a second output circuit, an overcurrent protection circuit, a fault logic control circuit, a fault output circuit and an undervoltage protection circuit. The input end of the double-level bootstrap circuit is connected with the input end of the first input stage circuit and the input end of the under-voltage protection circuit, the input end of the under-voltage protection circuit is used for being connected with a power supply, and the output end of the double-level bootstrap circuit is connected with the input end of the dead zone generation circuit. According to the intelligent power module, the applicability, the reliability and the market competitiveness of the intelligent power module can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of intelligent power modules, and in particular to an intelligent power module. Background Art

[0002] An intelligent power module (IPM) is a power drive product that combines power electronics and integrated circuit technology. It integrates power switching devices and high-voltage drive circuits, and includes built-in fault detection circuits for overvoltage, overcurrent, and overheating. The IPM receives control signals from the MCU to drive subsequent circuits and transmits system status signals back to the MCU. Compared to traditional discrete solutions, IPMs are gaining a growing market share due to their high integration and reliability. They are particularly well-suited for motor drive inverters and various inverter power supplies, making them ideal power electronics devices for variable-frequency speed regulation, metallurgical machinery, electric traction, servo drives, and variable-frequency home appliances.

[0003] The high-voltage side power supply of traditional intelligent power modules is floating, and the voltage will increase with the increase of the bus voltage (VBUS). The voltage drop between the high-voltage side floating power supply and the floating ground must remain constant, while the potential of the high-voltage side floating ground will vary between zero and VBUS. Therefore, the high-voltage side power supply of the chip needs to adopt an isolated power supply solution, and the high-voltage side power supply of the chip needs to have a certain ability to resist voltage transients. Currently, the bootstrap power supply method is the most commonly used power supply method for the high-voltage side of the intelligent power module, such as Figure 1 As shown in the figure. When the low-voltage side power transistor Q2 turns on, the potential of VS is pulled to zero. At this time, VCC supplies power to the bootstrap capacitor through the bootstrap diode Dboot. When charging stops, the voltage on Cboot is approximately equal to the voltage of VCC. When the low-voltage side power transistor is turned off and the high-voltage side power transistor is turned on, the potential of the Vs terminal is quickly pulled to VBUS due to the turning on of Q1. Since the voltage across the capacitor cannot change suddenly, the voltage of VCCA is approximately equal to (VBUS + VCC). At this time, the capacitor acts as a power supply for the high-voltage circuit of the battery. In the next cycle, when the lower transistor Q2 turns on, Cboot is recharged to meet the power supply requirements when the high-voltage side power transistor turns on in the next cycle, and this cycle repeats. Therefore, the bootstrap power supply method can ensure continuous power supply for the high-voltage side circuit. During normal operation of a system using an intelligent power module, the freewheeling effect of the inductive load causes the source-drain voltage difference of the high-voltage side switching tube device to be less than the output negative voltage. At this time, the bootstrap capacitor will be continuously charged by the bootstrap diode, and the voltage across it can easily exceed the maximum gate-source voltage of the switching tube device, resulting in excessive gate-source voltage and damage to the switching tube, resulting in poor overall circuit reliability. Summary of the Invention

[0004] The present invention provides an intelligent power module, aiming to solve the problem of poor reliability of existing intelligent power modules.

[0005] An embodiment of the present invention provides an intelligent power module, comprising: a first input stage circuit, a second input stage circuit, a dual-level bootstrap circuit, a dead zone generation circuit, a pulse generation circuit, a first level shift circuit, a first output circuit, a low-side delay circuit, a second output circuit, an overcurrent protection circuit, a fault logic control circuit, a fault output circuit, and an undervoltage protection circuit;

[0006] The input end of the first input stage circuit is used to connect to the high-side drive signal, and the output end of the first input stage circuit is connected to the dead zone generating circuit, the pulse generating circuit, the first level shifting circuit and the first output circuit in sequence; the input end of the dual-level bootstrap circuit is respectively connected to the input end of the first input stage circuit and the input end of the undervoltage protection circuit, the input end of the undervoltage protection circuit is used to connect to a power supply, and the output end of the dual-level bootstrap circuit is connected to the input end of the dead zone generating circuit; the output end of the undervoltage protection circuit is connected to the input end of the fault logic control circuit;

[0007] The input end of the second input stage circuit is used to connect the low-side drive signal, and the output end of the second input stage circuit is sequentially connected to the dead zone generating circuit, the low-side delay circuit and the second output circuit;

[0008] The input end of the overcurrent protection circuit is used to connect the overcurrent detection signal, the output end of the overcurrent protection circuit is connected to the input end of the fault logic control circuit, the output end of the fault logic control circuit is respectively connected to the input end of the first output circuit, the input end of the second output circuit and the input end of the fault output circuit, and the output end of the fault output circuit is used to output a fault signal.

[0009] Preferably, the dual-level bootstrap circuit includes: a dual-level bootstrap power supply circuit, a second level shift circuit, an RS trigger circuit and an output buffer circuit;

[0010] The input end of the dual-level bootstrap power supply circuit is connected to the power supply, the output end of the dual-level bootstrap power supply circuit is connected to the second level shift circuit, the RS trigger circuit and the output buffer circuit in sequence, and the output end of the output buffer circuit is connected to the input end of the dead zone generation circuit.

[0011] Preferably, the dual-level bootstrap power supply circuit includes: a control switch, an undervoltage detection circuit, a first bootstrap diode simulation circuit and a second bootstrap diode simulation circuit;

[0012] The input end of the undervoltage detection circuit and the source of the control switch are respectively used to connect to the power supply; the output end of the undervoltage protection circuit is connected to the second level shift circuit and grounded; the drain of the control switch is connected to the input end of the first bootstrap diode simulation circuit; the gate of the control switch is used to connect to the undervoltage detection circuit; the output end of the first bootstrap diode simulation circuit is connected to the input end of the second level shift circuit; the input end of the second bootstrap diode simulation circuit is used to connect to the power supply; and the output end of the second bootstrap diode simulation circuit is connected to the input end of the second level shift circuit.

[0013] Preferably, the undervoltage detection circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, an inverter, a first diode, a first MOS transistor, a second MOS transistor and a third MOS transistor;

[0014] The first end of the third resistor is respectively connected to the source of the third MOS transistor, the source of the second MOS transistor, and the first end of the second resistor, and is also connected to the power supply; the second end of the third resistor is respectively connected to the first end of the fourth resistor and the gate of the first MOS transistor, and the second end of the fourth resistor is grounded; the source of the first MOS transistor is respectively connected to the drain of the second MOS transistor, the second end of the second resistor, and the first end of the first resistor, the second end of the first resistor is connected to the anode of the first diode, and the cathode of the first diode is connected to the input end of the second level shift circuit; the gate of the second MOS transistor is connected to the source of the second MOS transistor; the drain of the first MOS transistor is respectively connected to the drain of the third MOS transistor and the input end of the inverter, and the drain of the third MOS transistor is connected to the gate of the third MOS transistor; the output end of the inverter is connected to the gate of the control switch.

[0015] Preferably, the first bootstrap diode simulation circuit includes: a first bootstrap diode simulator, a fifth resistor, a fourth MOS transistor and a MOS transistor JFET1;

[0016] The drain of the first bootstrap diode emulator is connected to the drain of the control switch, the source of the first bootstrap diode emulator is respectively connected to the first end of the fifth resistor and the drain of the MOS transistor JFET1, the gate of the first bootstrap diode emulator is respectively connected to the second end of the fifth resistor and the drain of the fourth MOS transistor, the source of the MOS transistor JFET1 is connected to the input end of the second level shift circuit, and the gate of the MOS transistor JFET1 is grounded; the source of the fourth MOS transistor is grounded, and the gate of the fourth MOS transistor is used to connect to the LIN port.

[0017] Preferably, the second bootstrap diode simulation circuit includes: a second bootstrap diode simulator, a sixth resistor, a fifth MOS transistor and a MOS transistor JFET2;

[0018] The drain of the second bootstrap diode emulator is connected to the power supply, the source of the second bootstrap diode emulator is respectively connected to the first end of the sixth resistor and the drain of the MOS transistor JFET2, the gate of the second bootstrap diode emulator is respectively connected to the second end of the sixth resistor and the drain of the fifth MOS transistor, the source of the MOS transistor JFET2 is connected to the input end of the second level shift circuit, and the gate of the MOS transistor JFET2 is grounded; the source of the fifth MOS transistor is grounded, and the gate of the fifth MOS transistor is connected to the gate of the fourth MOS transistor.

[0019] Preferably, the second level shift circuit includes: a triode, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, and a seventeenth MOS transistor;

[0020] The base of the transistor is connected to the source of the MOS transistor JFET1, the collector of the transistor is connected to the power supply voltage, and the emitter of the transistor is respectively connected to the source of the MOS transistor JFET2, the source of the sixth MOS transistor, the source of the seventh MOS transistor, the source of the eighth MOS transistor, the source of the ninth MOS transistor, the source of the tenth MOS transistor, and the source of the eleventh MOS transistor; the gate of the sixth MOS transistor is respectively connected to the gate of the seventh MOS transistor and the gate of the eighth MOS transistor, and the gate of the ninth MOS transistor is respectively connected to the gate of the tenth MOS transistor and the gate of the eleventh MOS transistor; the drain of the sixth MOS transistor is connected to the drain of the sixteenth MOS transistor, the drain of the seventh MOS transistor is connected to the drain of the twelfth MOS transistor, and the drain of the eighth MOS transistor is connected to the drain of the fourteenth MOS transistor;

[0021] The drain of the ninth MOS transistor is connected to the drain of the seventeenth MOS transistor, the drain of the tenth MOS transistor is connected to the drain and gate of the thirteenth MOS transistor respectively, and the drain of the eleventh MOS transistor is connected to the drain and gate of the fifteenth MOS transistor respectively;

[0022] The source of the twelfth MOS transistor is connected to the source of the thirteenth MOS transistor, the source of the fourteenth MOS transistor, and the source of the fifteenth MOS transistor, respectively, and is grounded; the gate of the twelfth MOS transistor is connected to the gate of the thirteenth MOS transistor, and the gate of the fourteenth MOS transistor is connected to the gate of the fifteenth MOS transistor; the source of the twelfth MOS transistor is connected to the cathode of the first diode;

[0023] The source of the sixteenth MOS transistor is connected to the source of the seventeenth MOS transistor, the gate of the sixteenth MOS transistor is used to connect to the SET port, and the gate of the seventeenth MOS transistor is used to connect to the RESET port.

[0024] Preferably, the first end of the RS trigger circuit is connected to the source of the eleventh MOS transistor, and the second end of the RS trigger circuit is connected to the source of the fifteenth MOS transistor and is grounded.

[0025] Preferably, the output buffer circuit includes: a first capacitor and a first transistor, the two ends of the first capacitor are respectively connected to the two ends of the RS trigger circuit, the source of the first transistor is grounded, the gate of the first transistor is connected to the RS trigger circuit, and the drain of the first transistor is used to connect to the bus voltage.

[0026] Preferably, the first input stage circuit includes a MOS transistor M20 and a MOS transistor M21; the gate of the MOS transistor M20 is connected to the gate of the MOS transistor M21 and is used to connect to the high-side drive signal; the source of the MOS transistor M20 is used to connect to the HL1 port, and the drain of the MOS transistor M20 is used to connect to the VB1 port; the source of the MOS transistor M21 is used to connect to the VS1 port, and the drain of the MOS transistor M21 is used to connect to the HL1 port;

[0027] The second input stage circuit includes a MOS transistor M22 and a MOS transistor M23; the gate of the MOS transistor M22 is connected to the gate of the MOS transistor M23 and is used to connect the low-side drive signal; the source of the MOS transistor M22 is used to connect to the LH1 port, and the drain of the MOS transistor M22 is used to connect to the power supply; the source of the MOS transistor M23 is grounded, and the drain of the MOS transistor M23 is used to connect to the LL01 port.

[0028] Compared with the prior art, the beneficial effect of the present invention lies in that the input end of the first input stage circuit is used to connect the high-side drive signal, and the output end of the first input stage circuit is connected to the dead zone generating circuit, the pulse generating circuit, the first level shifting circuit and the first output circuit in sequence; the input end of the dual-level bootstrap circuit is respectively connected to the input end of the first input stage circuit and the input end of the undervoltage protection circuit, the input end of the undervoltage protection circuit is used to connect the power supply, and the output end of the dual-level bootstrap circuit is connected to the input end of the dead zone generating circuit; the output end of the undervoltage protection circuit is connected to the input end of the fault logic control circuit; the input end of the second input stage circuit is used to connect the low-side drive signal, and the output end of the second input stage circuit is connected to the dead zone generating circuit, the low-side delay circuit and the second output circuit in sequence; the input end of the overcurrent protection circuit is used to connect the overcurrent detection signal, the output end of the overcurrent protection circuit is connected to the input end of the fault logic control circuit, the output end of the fault logic control circuit is respectively connected to the input end of the first output circuit, the input end of the second output circuit and the input end of the fault output circuit, and the output end of the fault output circuit is used to output a fault signal. In this way, by integrating a dual-level bootstrap circuit and driving the upper and lower tubes of the output stage to output separately, the intelligent power module uses a dual-level circuit to realize the bootstrap circuit function, and uses the gate clamping technology of the dual-level bootstrap circuit to realize voltage clamping, while greatly improving the negative bias capability of the chip's VS terminal; the upper and lower tubes of the output stage are driven to output separately, realizing flexible control of the turn-on time and turn-off time of the switching device to meet the requirements of switching devices of different current levels, thereby improving the applicability, reliability and market competitiveness of the intelligent power module. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings:

[0030] Figure 1 This is the circuit diagram of the traditional bootstrap power supply method;

[0031] Figure 2 is a circuit diagram of an intelligent power module provided by an embodiment of the present invention;

[0032] Figure 3 is a circuit diagram of a dual-level bootstrap circuit provided by an embodiment of the present invention;

[0033] Figure 4 is a circuit diagram of a dual-level bootstrap power supply circuit provided by an embodiment of the present invention;

[0034] Figure 5 is a circuit diagram of a second level shift circuit provided by an embodiment of the present invention;

[0035] Figure 6is a waveform diagram of the intelligent power module provided by an embodiment of the present invention;

[0036] Figure 7 4 is a circuit diagram of an input stage circuit provided by an embodiment of the present invention.

[0037] In the figure, 1. first input stage circuit, 2. second input stage circuit, 3. dual-level bootstrap circuit, 31. dual-level bootstrap power supply circuit, 311. undervoltage detection circuit, 312. first bootstrap diode simulation circuit, 313. second bootstrap diode simulation circuit, 32. second level shift circuit, 33. RS trigger circuit, 34. output buffer circuit, 4. dead zone generation circuit, 5. pulse generation circuit, 6. first level shift circuit, 7. first output circuit, 8. low-side delay circuit, 9. second output circuit, 10. overcurrent protection circuit, 11. fault logic control circuit, 12. fault output circuit, 13. undervoltage protection circuit. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0039] Combined with attachment Figure 2-Figure 7 As shown, an embodiment of the present invention provides an intelligent power module, including: a first input stage circuit 1, a second input stage circuit 2, a dual-level bootstrap circuit 3, a dead zone generation circuit 4, a pulse generation circuit 5, a first level shift circuit 6, a first output circuit 7, a low-side delay circuit 8, a second output circuit 9, an overcurrent protection circuit 10, a fault logic control circuit 11, a fault output circuit 12 and an undervoltage protection circuit 13.

[0040] The input end of the first input stage circuit 1 is used to connect to the high-side drive signal, and the output end of the first input stage circuit 1 is connected to the dead zone generating circuit 4, the pulse generating circuit 5, the first level shifting circuit 6 and the first output circuit 7 in sequence; the input end of the dual-level bootstrap circuit 3 is respectively connected to the input end of the first input stage circuit 1 and the input end of the undervoltage protection circuit 13, the input end of the undervoltage protection circuit 13 is used to connect to VCC, and the output end of the dual-level bootstrap circuit 3 is connected to the input end of the dead zone generating circuit 4; the output end of the undervoltage protection circuit 13 is connected to the input end of the fault logic control circuit 11;

[0041] The input end of the second input stage circuit 2 is used to connect the low-side drive signal, and the output end of the second input stage circuit 2 is sequentially connected to the dead zone generating circuit 4, the low-side delay circuit 8 and the second output circuit 9;

[0042] The input end of the overcurrent protection circuit 10 is used to connect the overcurrent detection signal, the output end of the overcurrent protection circuit 10 is connected to the input end of the fault logic control circuit 11, the output end of the fault logic control circuit 11 is respectively connected to the input end of the first output circuit 7, the input end of the second output circuit 9 and the input end of the fault output circuit 12, and the output end of the fault output circuit 12 is used to output a fault signal.

[0043] Specifically, the input drive signals of HIN1, HIN2, and HIN3 (3-channel high-side drive circuits) pass through the first input stage circuit 1 and the dead zone generation circuit 4 to output the OUT_H pulse signal. The pulse generation circuit 5 outputs SET and RESET short pulse signals respectively through the rising edge and falling edge of the OUT_H pulse signal. The low-to-high voltage conversion is realized through the first level shift circuit 6, and the first output circuit 7 outputs the high-side drive pulse signals HHO and HLO.

[0044] The LIN1, LIN2, and LIN3 (3-channel low-side drive circuit) input drive signals pass through the second input stage circuit 2 and the dead zone generation circuit 4 to output the OUT_L pulse signal; through the low-side delay circuit 8, the consistency of the high and low-side drive signals is achieved, and the second output circuit 9 outputs the low-side drive pulse signals LHO and LLO.

[0045] In this way, by driving the upper and lower tubes of the output stage separately, the on-time and off-time of the switching device can be flexibly controlled to meet the requirements of switching devices of different current levels.

[0046] The dual-level bootstrap circuit 3 implements the bootstrap circuit function and simultaneously uses the gate clamping technology of the dual-level bootstrap circuit 3 to achieve voltage clamping while significantly improving the chip's VS negative bias capability. The drive signal HO and LO outputs are protected by the undervoltage protection circuit 13, the overcurrent protection circuit 10 (ITRIP protection circuit), and the fault logic circuit, and a fault signal is output through the fault output circuit 12. In this way, by integrating the dual-level bootstrap circuit 3 and the driver output stage with separate upper and lower transistor outputs, the intelligent power module not only implements the bootstrap circuit function using the dual-level circuit, but also uses the gate clamping technology of the dual-level bootstrap circuit 3 to achieve voltage clamping while significantly improving the chip's VS negative bias capability. The separate upper and lower transistor outputs of the driver output stage enable flexible control of the switch device's turn-on and turn-off times to meet the requirements of switches of different current levels, thereby improving the applicability, reliability, and market competitiveness of the intelligent power module.

[0047] In this embodiment, the dual-level bootstrap circuit 3 includes: a dual-level bootstrap power supply circuit 31, a second level shift circuit 32, an RS trigger circuit 33 and an output buffer circuit 34;

[0048] The input end of the dual-level bootstrap power supply circuit 31 is connected to the VCC, the output end of the dual-level bootstrap power supply circuit 31 is connected to the second level shift circuit 32, the RS trigger circuit 33 and the output buffer circuit 34 in sequence, and the output end of the output buffer circuit 34 is connected to the input end of the dead zone generating circuit 4.

[0049] In this embodiment, the dual-level bootstrap power supply circuit 31 includes: a control switch, an undervoltage detection circuit 311, a first bootstrap diode simulation circuit 312 and a second bootstrap diode simulation circuit 313;

[0050] The input end of the undervoltage detection circuit 311 and the source of the control switch are respectively used to connect to the VCC, the output end of the undervoltage protection circuit 13 is connected to the second level shift circuit 32 and grounded, the drain of the control switch is connected to the input end of the first bootstrap diode simulation circuit 312, and the gate of the control switch is used to connect to the undervoltage detection circuit 311; the output end of the first bootstrap diode simulation circuit 312 is connected to the input end of the second level shift circuit 32, the input end of the second bootstrap diode simulation circuit 313 is used to connect to the VCC, and the output end of the second bootstrap diode simulation circuit 313 is connected to the input end of the second level shift circuit 32.

[0051] In this embodiment, the undervoltage detection circuit 311 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, an inverter INV, a first diode D1, a first MOS transistor M1, a second MOS transistor M2, and a third MOS transistor M3;

[0052] A first end of the third resistor R3 is respectively connected to the source of the third MOS transistor M3, the source of the second MOS transistor M2, and the first end of the second resistor R2, and is also connected to VCC; a second end of the third resistor R3 is respectively connected to the first end of the fourth resistor R4 and the gate of the first MOS transistor M1, and a second end of the fourth resistor R4 is grounded; a source of the first MOS transistor M1 is respectively connected to the drain of the second MOS transistor M2, the second end of the second resistor R2, and the first end of the first resistor R1; a second end of the first resistor R1 is connected to the anode of the first diode D1, and a cathode of the first diode D1 is connected to the input end of the second level shift circuit 32; a gate of the second MOS transistor M2 is connected to the source of the second MOS transistor M2; a drain of the first MOS transistor M1 is respectively connected to the drain of the third MOS transistor M3 and the input end of the inverter INV, and a drain of the third MOS transistor M3 is connected to the gate of the third MOS transistor M3; and an output end of the inverter INV is connected to the gate of the control switch.

[0053] Specifically, the cathode of the first diode D1 of the VS negative voltage detection circuit is connected to VS, the anode is connected to the second end of the first resistor R1, and the source of the first MOS transistor M1 is respectively connected to the drain of the second MOS transistor M2, the second end of the second resistor R2, and the first end of the first resistor R1.

[0054] The main function of the VS negative voltage detection circuit in the dead zone phase is to control the charging path from VCC to VCCA to achieve the purpose of clamping the high-voltage side output voltage. However, due to the particularity of the VS terminal voltage, which may be a negative voltage or a high voltage as high as 600V, the traditional negative voltage detection circuit 311 is likely to cause the risk of chip burning. The common negative voltage detection circuit 311 can be performed by comparing the resistor divider value with the reference voltage. In order to solve this problem, the present invention uses the parasitic diode of the high-voltage LDMOS device as a negative voltage detection device, which can not only play the role of negative voltage detection, but also play the role of voltage resistance to protect the drive circuit.

[0055] The first diode D1 is a high-voltage diode, and the value of Vref is the reference voltage. The first resistor R1 filters out transient noise caused by the parasitic capacitance of the first diode D1. The second resistor R2 is a pull-up resistor, used to determine the potential of point E when VS is positive. The second MOS transistor M2 prevents the potential at point E from being too high, which could damage circuit components. The second MOS transistor M2 serves as the primary detection device, with a threshold voltage of 0.8V. The third MOS transistor M3 acts as a load for the second MOS transistor M2, accelerating the rise of point F. If Vref is set to 1V, then when the voltage of VS exceeds -0.5V, MN7 will shut down, transmitting a control signal to the gate of the control switch PSW, turning on the control switch PSW to charge the bootstrap capacitor. During the dead zone, VS will become negative. Due to the forward clamping effect of the diode, the potential of point E will be pulled down. If the voltage of VS is lower than -0.5V, the voltage of point E will be pulled down to below 0.2V by the first diode D1, causing MN7 to turn on. The negative voltage detection module will output a high-level signal to turn off the control switch PSW, thereby achieving the purpose of clamping the output stage voltage.

[0056] In this embodiment, the first bootstrap diode simulation circuit 312 includes: a first bootstrap diode simulator P1, a fifth resistor RD1, a fourth MOS transistor N1 and a MOS transistor JFET1;

[0057] The drain of the first bootstrap diode emulator P1 is connected to the drain of the control switch. The source of the first bootstrap diode emulator P1 is respectively connected to the first end of the fifth resistor RD1 and the drain of the MOS transistor JFET1. The gate of the first bootstrap diode emulator P1 is respectively connected to the second end of the fifth resistor RD1 and the drain of the fourth MOS transistor N1. The source of the MOS transistor JFET1 is connected to the input end of the second level shift circuit 32, and the gate of the MOS transistor JFET1 is grounded. The source of the fourth MOS transistor N1 is grounded, and the gate of the fourth MOS transistor N1 is used to connect to the LIN port. The connection point between the first end of the fifth resistor RD1 and the drain of the MOS transistor JFET1 is denoted as S1.

[0058] In this embodiment, the second bootstrap diode simulation circuit 313 includes: a second bootstrap diode simulator P2, a sixth resistor RD2, a fifth MOS transistor N2 and a MOS transistor JFET2;

[0059] The drain of the second bootstrap diode emulator P2 is connected to VCC, the source of the second bootstrap diode emulator P2 is respectively connected to the first end of the sixth resistor RD2 and the drain of the MOS transistor JFET2, the gate of the second bootstrap diode emulator P2 is respectively connected to the second end of the sixth resistor RD2 and the drain of the fifth MOS transistor N2, the source of the MOS transistor JFET2 is connected to the input end of the second level shift circuit 32, and the gate of the MOS transistor JFET2 is grounded; the source of the fifth MOS transistor N2 is grounded, and the gate of the fifth MOS transistor N2 is connected to the gate of the fourth MOS transistor N1. The connection point between the first end of the sixth resistor RD2 and the drain of the MOS transistor JFET2 is denoted as S2.

[0060] Specifically, such as Figure 3As shown in the figure. When LIN = 1, the first bootstrap diode emulator P1 and the fourth MOS transistor N1 are simultaneously turned on, and VCC charges the bootstrap capacitor CBST through the channel of the first bootstrap diode emulator P1 and the MOS transistor JFET1. When LIN is zero and HIN is high, the high-side GaN device turns on, and the high-side floating ground VS gradually rises to VBUS. At this time, the fourth MOS transistor N1 and the first bootstrap diode emulator P1 are turned off, and the potential at point S1 in the diode model rises as VCCA rises. However, as long as the voltage at point S1 exceeds the pinch-off voltage of MOS transistor JFET1, MOS transistor JFET1 closes the drain-to-source channel. At this point, even if VS continues to increase, the potential of S1 will not continue to increase, achieving the voltage withstand function. Using a JFET bootstrap diode emulator can achieve better reverse recovery characteristics. Because JFETs have no body diode and therefore no reverse recovery current, transistor P1, as a low-voltage device, has a high doping concentration, so the reverse recovery current is extremely small.

[0061] In this embodiment, the second level shift circuit 32 includes: a transistor Q1, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor LDMOS1, and a seventeenth MOS transistor LDMOS2;

[0062] The base of the transistor Q1 is connected to the source of the MOS transistor JFET1, the collector of the transistor Q1 is connected to the power supply voltage, and the emitter of the transistor Q1 is respectively connected to the source of the MOS transistor JFET2, the source of the sixth MOS transistor M6, the source of the seventh MOS transistor M7, the source of the eighth MOS transistor M8, the source of the ninth MOS transistor M9, the source of the tenth MOS transistor M10, and the source of the eleventh MOS transistor M11; the gate of the sixth MOS transistor M6 is respectively connected to the gate of the seventh MOS transistor M7 and the gate of the eighth MOS transistor M8, and the gate of the ninth MOS transistor M9 is respectively connected to the gate of the tenth MOS transistor M10 and the gate of the eleventh MOS transistor M11; the drain of the sixth MOS transistor M6 is connected to the drain of the sixteenth MOS transistor LDMOS1, the drain of the seventh MOS transistor M7 is connected to the drain of the twelfth MOS transistor M12, and the drain of the eighth MOS transistor M8 is connected to the drain of the fourteenth MOS transistor M14;

[0063] The drain of the ninth MOS transistor M9 is connected to the drain of the seventeenth MOS transistor LDMOS2, the drain of the tenth MOS transistor M10 is connected to the drain and gate of the thirteenth MOS transistor M13, and the drain of the eleventh MOS transistor M11 is connected to the drain and gate of the fifteenth MOS transistor M15.

[0064] The source of the twelfth MOS transistor M12 is respectively connected to the source of the thirteenth MOS transistor M13, the source of the fourteenth MOS transistor M14, and the source of the fifteenth MOS transistor M15 and is grounded; the gate of the twelfth MOS transistor M12 is connected to the gate of the thirteenth MOS transistor M13, and the gate of the fourteenth MOS transistor M14 is connected to the gate of the fifteenth MOS transistor M15; the source of the twelfth MOS transistor M12 is connected to the cathode of the first diode D1;

[0065] The source of the sixteenth MOS transistor LDMOS1 is connected to the source of the seventeenth MOS transistor LDMOS2 , the gate of the sixteenth MOS transistor LDMOS1 is connected to the SET port, and the gate of the seventeenth MOS transistor LDMOS2 is connected to the RESET port.

[0066] In this embodiment, a first end of the RS trigger circuit 33 is connected to the source of the eleventh MOS transistor M11 , and a second end of the RS trigger circuit 33 is connected to the source of the fifteenth MOS transistor M15 and is grounded.

[0067] In this embodiment, the output buffer circuit 34 includes: a first capacitor C BST and the first transistor GaNFET1, the first capacitor C BST The two ends of the first transistor GaNFET1 are respectively connected to the two ends of the RS trigger circuit 33, the source of the first transistor GaNFET1 is grounded, the gate of the first transistor GaNFET1 is connected to the RS trigger circuit 33, and the drain of the first transistor GaNFET1 is used to connect the bus voltage V BUS .

[0068] In this embodiment, the first input stage circuit 1 includes a MOS transistor M20 and a MOS transistor M21; the gate of the MOS transistor M20 is connected to the gate of the MOS transistor M21 and is used to connect to the high-side drive signal; the source of the MOS transistor M20 is used to connect to the HL1 port, and the drain of the MOS transistor M20 is used to connect to the VB1 port; the source of the MOS transistor M21 is used to connect to the VS1 port, and the drain of the MOS transistor M21 is used to connect to the HL1 port;

[0069] The second input stage circuit 2 includes a MOS transistor M22 and a MOS transistor M23; the gate of the MOS transistor M22 is connected to the gate of the MOS transistor M23 and is used to connect to the low-side drive signal; the source of the MOS transistor M22 is used to connect to the LH1 port, and the drain of the MOS transistor M22 is used to connect to the VCC; the source of the MOS transistor M23 is grounded, and the drain of the MOS transistor M23 is used to connect to the LL01 port.

[0070] Specifically, the signal loss caused by VS negative bias essentially stems from the fact that after passing through the high-voltage level shifting circuit, the signal cannot be received by the buffer, thus preventing it from being transmitted to the subsequent circuitry. The reason the buffer cannot receive the output signal of the high-voltage level shifting circuit is that as the high-voltage side floating ground VS drops, its threshold voltage also drops. When the threshold voltage drops below the level of the previous stage signal, the signal cannot continue to be transmitted. Therefore, to increase the chip's VS negative bias capability, it is necessary to ensure that the threshold voltage of the high-voltage side receiving stage circuit (the first stage circuit in the VCCA to VS voltage domain) does not change with changes in VS. The turn-on condition for a PMOS transistor is that the source-gate voltage difference is greater than the absolute value of the PMOS transistor's turn-on voltage, Vth. That is, as long as the gate voltage is Vth lower than the power supply voltage, the transistor will respond, regardless of grounding. Therefore, this characteristic of PMOS can be used to solve the problem of LDMOS subsequent stage circuits being affected by VS negative bias.

[0071] The gate driver circuit of the dual-level bootstrap circuit 3 utilizes a PMOS transistor level-shifting structure, isolating the receiver stage's response voltage from its dependence on VS. Secondly, the high-voltage power supply is split into two: VCCA, which ultimately outputs to the gate of the high-voltage-side power device, and HB, which powers the first stage of the high-voltage receiver circuit. Transistor Q1 isolates the two. When VS goes negative, the control circuit detects the negative VS voltage and outputs a control signal to shut off the charging path's control switch, K(PSW). The VCCA value varies with the high-voltage-side floating ground, VS, to ensure a constant VCCA-VS voltage and prevent gate-source breakdown of the GaN device. During the negative VS voltage phase, the HB voltage is powered by a second bootstrap diode emulation circuit. Therefore, its potential remains unchanged with changes in the high-voltage-side floating ground, VS, ensuring that the input signal can still be transmitted to the subsequent circuitry during this negative VS voltage phase. The detailed operation of the dual-level bootstrap power supply module is described below. When the high-voltage-side GaN is off and the low-voltage-side GaN is on, the VS voltage is zero. At this time, switch PSW is turned on, VCC charges VCCA through the first bootstrap diode emulation circuit, and charges HB through the second bootstrap diode emulation circuit. At this point, the voltages of VCCA and HB are essentially the same, and the circuit operates in the same manner as a conventional bootstrap power supply circuit. When the high-voltage side GaN is on and the low-voltage side GaN is off, the VS voltage is equal to VBUS. At this point, switch PSW is turned on, the first bootstrap diode emulation circuit 312 and the second bootstrap diode emulation circuit 313 both withstand reverse voltage, and VCCA supplies power to HB through transistor Q1, so the HB voltage is approximately equal to VCCA. In this case, the circuit operates in the same manner as a conventional bootstrap power supply circuit.

[0072] When the working state of the circuit is in the dead zone between the high-voltage side power tube being turned off and the low-voltage side power tube being turned on, the voltage of VS becomes a negative voltage, and the control circuit detects the negative voltage and controls the switch PSW to be disconnected. At this time, VCCA changes with the change of VS, but HB is still powered by VCC through the second bootstrap diode analog circuit 313, so the potential of HB does not change. The high-voltage level shift circuit operates in the voltage domain of VCCA-COM, the high-voltage receiving stage operates at the HB-VS voltage, and the high-voltage side output stage circuit and RS trigger operate at the VCCA-VS voltage. Since the high-voltage receiving stage is a current comparator structure, its response voltage is the threshold voltage Vth,p of the seventh MOS tube M7 and the eighth MOS tube M8. Since the HB potential does not change at this time, the VS potential drop will not affect the response voltage of the high-voltage receiving stage, and the input signal can be transmitted to the subsequent path. In the process of the VS voltage changing from positive to negative, the voltage waveform of the key nodes in the circuit is as follows: Figure 6As shown in the figure, the high-voltage receiving stage operates at a voltage between HB and VS, resulting in the high and low levels of its output signal being HB and VS, respectively. The RS flip-flop, however, operates at a voltage between VCCA and VS. Due to the disconnection of switch PSW and the isolation of transistor Q1, the voltage of VCCA varies with the voltage of VS and is less than HB. Therefore, the presence of the high-voltage receiving stage expands the output voltage range. Regardless of how low VS is, as long as the device withstand voltage meets the requirements, the output voltage of the high-voltage receiving stage circuit will always include the response threshold of the RS flip-flop.

[0073] The gate clamping technology with high VS negative bias capability of the present invention can not only realize the gate protection of GaN, but also take into account the static power consumption and VS negative bias capability of the high-voltage side.

[0074] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, article, or device comprising the element.

[0075] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. An intelligent power module, characterized in that: include: A first input stage circuit, a second input stage circuit, a dual-level bootstrap circuit, a dead zone generating circuit, a pulse generating circuit, a first level shifting circuit, a first output circuit, a low-side delay circuit, a second output circuit, an overcurrent protection circuit, a fault logic control circuit, a fault output circuit, and an undervoltage protection circuit; The input end of the first input stage circuit is used to connect the high-side drive signal, and the output end of the first input stage circuit is sequentially connected to the dead zone generating circuit, the pulse generating circuit, the first level shifting circuit and the first output circuit; The input end of the dual-level bootstrap circuit is respectively connected to the input end of the first input stage circuit and the input end of the undervoltage protection circuit, the input end of the undervoltage protection circuit is used to connect to the power supply, the output end of the dual-level bootstrap circuit is connected to the input end of the dead zone generating circuit; the output end of the undervoltage protection circuit is connected to the input end of the fault logic control circuit; The input end of the second input stage circuit is used to connect the low-side driving signal, and the output end of the second input stage circuit is sequentially connected to the dead zone generating circuit, the low-side delay circuit and the second output circuit; The input end of the overcurrent protection circuit is used to connect to the overcurrent detection signal, the output end of the overcurrent protection circuit is connected to the input end of the fault logic control circuit, the output end of the fault logic control circuit is respectively connected to the input end of the first output circuit, the input end of the second output circuit and the input end of the fault output circuit, and the output end of the fault output circuit is used to output a fault signal.

2. The intelligent power module according to claim 1, characterized in that: The dual-level bootstrap circuit comprises: a dual-level bootstrap power supply circuit, a second level shift circuit, an RS trigger circuit and an output buffer circuit; The input end of the dual-level bootstrap power supply circuit is connected to the power supply, the output end of the dual-level bootstrap power supply circuit is connected to the second level shift circuit, the RS trigger circuit and the output buffer circuit in sequence, and the output end of the output buffer circuit is connected to the input end of the dead zone generating circuit.

3. The intelligent power module according to claim 2, characterized in that: The dual-level bootstrap power supply circuit comprises: a control switch, an undervoltage detection circuit, a first bootstrap diode simulation circuit and a second bootstrap diode simulation circuit; The input end of the undervoltage detection circuit and the source of the control switch are respectively used to connect to the power supply, the output end of the undervoltage protection circuit is connected to the second level shift circuit and grounded, the drain of the control switch is connected to the input end of the first bootstrap diode simulation circuit, and the gate of the control switch is used to connect to the undervoltage detection circuit; the output end of the first bootstrap diode simulation circuit is connected to the input end of the second level shift circuit, the input end of the second bootstrap diode simulation circuit is used to connect to the power supply, and the output end of the second bootstrap diode simulation circuit is connected to the input end of the second level shift circuit.

4. The intelligent power module according to claim 3, characterized in that: The undervoltage detection circuit comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, an inverter, a first diode, a first MOS transistor, a second MOS transistor and a third MOS transistor; The first end of the third resistor is respectively connected to the source of the third MOS tube, the source of the second MOS tube and the first end of the second resistor and is connected to the power supply; the second end of the third resistor is respectively connected to the first end of the fourth resistor and the gate of the first MOS tube, and the second end of the fourth resistor is grounded; the source of the first MOS tube is respectively connected to the drain of the second MOS tube, the second end of the second resistor and the first end of the first resistor, the second end of the first resistor is connected to the positive electrode of the first diode, and the negative electrode of the first diode is connected to the input end of the second level shift circuit; the gate of the second MOS tube is connected to the source of the second MOS tube; the drain of the first MOS tube is respectively connected to the drain of the third MOS tube and the input end of the inverter, and the drain of the third MOS tube is connected to the gate of the third MOS tube; the output end of the inverter is connected to the gate of the control switch.

5. The intelligent power module according to claim 4, characterized in that: The first bootstrap diode simulation circuit includes: a first bootstrap diode simulator, a fifth resistor, a fourth MOS transistor and a MOS transistor JFET1; The drain of the first bootstrap diode simulator is connected to the drain of the control switch, the source of the first bootstrap diode simulator is respectively connected to the first end of the fifth resistor and the drain of the MOS tube JFET1, the gate of the first bootstrap diode simulator is respectively connected to the second end of the fifth resistor and the drain of the fourth MOS tube, the source of the MOS tube JFET1 is connected to the input end of the second level shift circuit, and the gate of the MOS tube JFET1 is grounded; the source of the fourth MOS tube is grounded, and the gate of the fourth MOS tube is used to connect to the LIN port.

6. The intelligent power module according to claim 5, characterized in that: The second bootstrap diode simulation circuit includes: a second bootstrap diode simulator, a sixth resistor, a fifth MOS transistor and a MOS transistor JFET2; The drain of the second bootstrap diode simulator is connected to the power supply, the source of the second bootstrap diode simulator is respectively connected to the first end of the sixth resistor and the drain of the MOS tube JFET2, the gate of the second bootstrap diode simulator is respectively connected to the second end of the sixth resistor and the drain of the fifth MOS tube, the source of the MOS tube JFET2 is connected to the input end of the second level shift circuit, and the gate of the MOS tube JFET2 is grounded; the source of the fifth MOS tube is grounded, and the gate of the fifth MOS tube is connected to the gate of the fourth MOS tube.

7. The intelligent power module according to claim 6, characterized in that: The second level shift circuit includes: a triode, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube and a seventeenth MOS tube; The base of the transistor is connected to the source of the MOS tube JFET1, the collector of the transistor is connected to the power supply voltage, and the emitter of the transistor is respectively connected to the source of the MOS tube JFET2, the source of the sixth MOS tube, the source of the seventh MOS tube, the source of the eighth MOS tube, the source of the ninth MOS tube, the source of the tenth MOS tube and the source of the eleventh MOS tube; the gate of the sixth MOS tube is respectively connected to the gate of the seventh MOS tube and the gate of the eighth MOS tube, and the gate of the ninth MOS tube is respectively connected to the gate of the tenth MOS tube and the gate of the eleventh MOS tube; the drain of the sixth MOS tube is connected to the drain of the sixteenth MOS tube, the drain of the seventh MOS tube is connected to the drain of the twelfth MOS tube, and the drain of the eighth MOS tube is connected to the drain of the fourteenth MOS tube; The drain of the ninth MOS tube is connected to the drain of the seventeenth MOS tube, the drain of the tenth MOS tube is respectively connected to the drain and gate of the thirteenth MOS tube, and the drain of the eleventh MOS tube is respectively connected to the drain and gate of the fifteenth MOS tube; The source of the twelfth MOS tube is respectively connected to the source of the thirteenth MOS tube, the source of the fourteenth MOS tube and the source of the fifteenth MOS tube and is grounded; the gate of the twelfth MOS tube is connected to the gate of the thirteenth MOS tube, the gate of the fourteenth MOS tube is connected to the gate of the fifteenth MOS tube; the source of the twelfth MOS tube is connected to the cathode of the first diode; The source of the sixteenth MOS tube is connected to the source of the seventeenth MOS tube, the gate of the sixteenth MOS tube is used to connect to the SET port, and the gate of the seventeenth MOS tube is used to connect to the RESET port.

8. The intelligent power module according to claim 7, characterized in that: The first end of the RS trigger circuit is connected to the source of the eleventh MOS tube, and the second end of the RS trigger circuit is connected to the source of the fifteenth MOS tube and is grounded.

9. The intelligent power module according to claim 8, characterized in that: The output buffer circuit includes: a first capacitor and a first transistor, wherein two ends of the first capacitor are respectively connected to two ends of the RS trigger circuit, the source of the first transistor is grounded, the gate of the first transistor is connected to the RS trigger circuit, and the drain of the first transistor is used to connect to the bus voltage.

10. The intelligent power module according to claim 1, characterized in that: The first input stage circuit includes a MOS tube M20 and a MOS tube M21; the gate of the MOS tube M20 is connected to the gate of the MOS tube M21 and is used to connect the high-side drive signal; the source of the MOS tube M20 is used to connect the HL1 port, and the drain of the MOS tube M20 is used to connect the VB1 port; the source of the MOS tube M21 is used to connect the VS1 port, and the drain of the MOS tube M21 is used to connect the HL1 port; The second input stage circuit includes a MOS tube M22 and a MOS tube M23; the gate of the MOS tube M22 is connected to the gate of the MOS tube M23 and is used to connect the low-side drive signal; the source of the MOS tube M22 is used to connect the LH1 port, and the drain of the MOS tube M22 is used to connect the power supply; the source of the MOS tube M23 is grounded, and the drain of the MOS tube M23 is used to connect the LL01 port.

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