Charge pump circuit

Abstract

The invention discloses a charge pump circuit, and the circuit comprises a first boost module which is used for responding to a first clock signal, and carrying out the pumping operation of a power voltage, so as to generate a first charge pump signal; the second boosting module is used for performing pumping operation on the power supply voltage in response to a second clock signal so as to generate a second charge pump signal; the notch filter is used for filtering the second charge pump signal in response to the sampling clock signal so as to obtain a control voltage signal; the first end of the output transistor is used for receiving the first charge pump signal, the control end of the output transistor is used for receiving the control voltage signal, and the output voltage signal of the output end of the charge pump circuit is adjusted according to the control voltage signal. The charge pump circuit provided by the invention can realize very low output ripple amplitude at very small area and power consumption cost, has very strong loading capacity, can provide the advantages of high efficiency, low noise, miniaturization and the like when being used as a power supply, and is suitable for various electronic equipment and application scenes.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a charge pump circuit. Background Art

[0002] In modern electronic devices, Charge Pump circuits are widely used in the field of power management due to their high efficiency, small size, and low power consumption. Charge pumps store and convert energy through capacitors, and can achieve voltage conversion without the use of inductors, which has obvious advantages in integrated circuit design. However, when charge pumps are used as power sources for other circuits, they face technical challenges such as large output ripple amplitude and weak load capacity.

[0003] In order to reduce the output ripple amplitude, the traditional charge pump structure usually needs to connect a large-capacity capacitor to the output end or adopt RC filtering, cascade RC filtering and other methods. Although these methods can reduce the ripple amplitude to a certain extent, they also bring some problems. First, large-capacity capacitors will increase the circuit area, which is not conducive to the miniaturization and integration of electronic equipment. Secondly, due to the limitation of the output voltage, the series resistance value cannot be too large, otherwise it will cause a large voltage drop at the output, affecting the efficiency of the circuit. In addition, in order to improve the load capacity of the charge pump circuit and reduce the output ripple amplitude, it is necessary to increase the value of the pump-up capacitor as much as possible, which further increases the area and cost of the circuit.

[0004] Figure 1 FIG. 2 shows a schematic diagram of a charge pump circuit according to the prior art. Figure 1 The structure shown forms a multi-stage low-pass filtering effect by arranging multiple capacitors Cs1 to Csn in parallel and multiple resistors Rs1 to Rsn in series at the output end of the charge pump circuit 100. This design can reduce the output ripple amplitude to a certain extent, but because the sum of the resistors Rs1 to Rsn cannot be too large, it is necessary to increase the capacitance of the capacitors Cs1 to Csn as much as possible in the circuit to further reduce the output ripple amplitude, which in turn leads to an increase in the area of ​​the capacitors and increases the cost of the circuit. At the same time, in order to improve the load capacity of the charge pump circuit and reduce the output ripple amplitude, the area of ​​the pumping capacitors C1 and C2 also needs to be as large as possible, which will also lead to an increase in the circuit area.

[0005] Therefore, how to design a charge pump circuit that can reduce the output ripple amplitude, improve the load capacity, and reduce the complexity and cost of circuit design is an urgent problem to be solved in the current electronic technology field. Summary of the invention

[0006] In view of the above problems, an object of the present invention is to provide a charge pump circuit that can reduce the output ripple amplitude and improve the load capacity while reducing the complexity and cost of circuit design.

[0007] According to one aspect of the present invention, a charge pump circuit is provided, comprising: a first boost module, for performing a pumping operation on a power supply voltage in response to a first clock signal to generate a first charge pump signal; a second boost module, for performing a pumping operation on the power supply voltage in response to a second clock signal to generate a second charge pump signal; a notch filter, for filtering the second charge pump signal in response to a sampling clock signal to obtain a control voltage signal; and an output transistor, wherein a first end of the output transistor is used to receive the first charge pump signal, a control end is used to receive the control voltage signal, and an output voltage signal at an output end of the charge pump circuit is adjusted according to the control voltage signal.

[0008] Optionally, the frequency of the sampling clock signal is the same as the frequency of the second clock signal and has a phase difference of 90°.

[0009] Optionally, a frequency of the first clock signal is twice a frequency of the second clock signal and the sampling clock signal.

[0010] Optionally, the first boost module and the second boost module each include at least one transistor forming a differential cross-coupled architecture, at least one boost node and at least one pump-up capacitor, a first end of the at least one pump-up capacitor being connected to a clock signal, and a second end of the at least one pump-up capacitor being connected to the boost node.

[0011] Optionally, it further includes: a sampling control circuit connected to at least one boost node of the first boost module and generating the sampling clock signal according to the voltage at the boost node.

[0012] Optionally, the first boost module includes: a first pumping capacitor, a first end of the first pumping capacitor is connected to the inverted signal of the first clock signal, and a second end of the first pumping capacitor is connected to the first boosting node; a second pumping capacitor, a first end of the second pumping capacitor is connected to the first clock signal, and a second end of the second pumping capacitor is connected to the second boosting node; a first transistor, connected between the first boosting node and a power supply voltage, and a control end of the first transistor is connected to the second boosting node; a second transistor, connected between the second boosting node and the power supply voltage, and a control end of the second transistor is connected to the first boosting node; a third transistor, connected between the output end of the first charge pump signal and the first boosting node, and a control end of the third transistor is connected to the second boosting node; and a fourth transistor, connected between the output end of the first charge pump signal and the second boosting node, and a control end of the fourth transistor is connected to the first boosting node, wherein the sampling control circuit is connected to the second boosting node, and generates the sampling clock signal according to the voltage at the second boosting node.

[0013] Optionally, the sampling control circuit includes: a first inverter, an input end of the first inverter is connected to the second boost node; a first D flip-flop, a clock end of the first D flip-flop is connected to the output end of the first inverter, a first output end of the first D flip-flop is used to output the sampling clock signal, a second output end of the first D flip-flop is used to output an inverted signal of the sampling clock signal, and a data end of the first D flip-flop is short-circuited with the second output end.

[0014] Optionally, it further includes: a second inverter, wherein the input end of the second inverter is connected to the first boost node, and the output end of the second inverter is floating or connected to a second D flip-flop.

[0015] Optionally, it also includes: a clock generating circuit, including an oscillator circuit and a frequency divider, the oscillator circuit is used to generate the first clock signal, and the frequency divider is used to perform a two-division operation on the first clock signal to generate the second clock signal.

[0016] Optionally, the notch filter includes: a first switch, a first end of the first switch is connected to the second charge pump signal; a second switch, a first end of the second switch is connected to the second end of the first switch, and the second end of the second switch is connected to the output end of the control voltage signal; a third switch, a first end of the third switch is connected to the second charge pump signal; a fourth switch, a first end of the fourth switch is connected to the second end of the third switch, and the second end of the fourth switch is connected to the output end of the control voltage signal; a first capacitor, a first end of the first capacitor is connected to the power supply voltage, and a second end of the first capacitor is connected to a common node of the first switch and the second switch; and a second capacitor, a first end of the second capacitor is connected to the power supply voltage, and a second end of the second capacitor is connected to a common node of the third switch and the fourth switch, wherein the first switch and the fourth switch are controlled by the sampling clock signal, and the second switch and the third switch are controlled by an inverted signal of the sampling clock signal.

[0017] Optionally, the notch filter charges and discharges the first capacitor and the second capacitor according to the sampling clock signal, wherein, when the sampling clock signal is at a high level, the first capacitor samples the second charge pump signal, and the second capacitor provides an output voltage to the output end of the notch filter; when the sampling clock signal is at a low level, the second capacitor samples the second charge pump signal, and the first capacitor provides an output voltage to the output end of the notch filter.

[0018] Optionally, it also includes: a filtering module, including a first resistor and a third capacitor, the first resistor and the third capacitor are connected between the second end of the output transistor and the power supply voltage, the intermediate node of the first resistor and the third capacitor is connected to the output end of the charge pump circuit, and the filtering module is used to reduce the noise of the output voltage signal.

[0019] In summary, the charge pump circuit of the present invention includes a first boost module, a second boost module, a notch filter and an output transistor. The first charge pump signal generated by the first boost module provides a load current to the output transistor. The second charge pump signal generated by the second boost module is filtered by the notch filter to obtain a control voltage signal applied to the gate of the output transistor. The notch filter can weaken the signal within a specific frequency range while allowing other frequency signals to pass as is, thereby reducing the ripple amplitude of the control voltage signal. Since the ripple of the output voltage signal of the charge pump circuit is consistent with the ripple of the control voltage of the output transistor when the output transistor operates in the saturation region, the ripple amplitude of the output voltage of the charge pump circuit of the present invention can also be significantly reduced. Therefore, the charge pump circuit of the present invention can achieve a very low output ripple amplitude at a very small area and power consumption cost, and has a strong load capacity. When used as a power supply, it can provide many benefits such as high efficiency, low noise, miniaturization, cost-effectiveness and flexibility, and is suitable for a variety of electronic devices and application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A structural schematic diagram of a charge pump circuit according to the prior art is shown.

[0022] Figure 2 A schematic structural diagram of a charge pump circuit according to an embodiment of the present invention is shown.

[0023] Figure 3 A circuit diagram of a notch filter according to an embodiment of the present invention is shown.

[0024] Figure 4 A circuit diagram of a sampling control circuit according to an embodiment of the present invention is shown.

[0025] Figure 5 A circuit diagram of a clock generating circuit according to an embodiment of the present invention is shown.

[0026] Figure 6 FIG. 4 shows an operation timing diagram of a charge pump circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0028] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "coupled" to another element or an element or circuit is said to be "coupled between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0029] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0030] Figure 2 FIG. 2 shows a schematic diagram of the structure of a charge pump circuit according to an embodiment of the present invention. Figure 2 As shown, the charge pump circuit 200 includes a first boost module 210 , a second boost module 220 , a notch filter 230 , a sampling control circuit 240 , a clock generation circuit 250 , an output transistor Mn0 , and a filtering module 260 .

[0031] The first boost module 210 is used to perform a pumping operation on the power supply voltage VCC in response to the first clock signal CLK1 to generate a first charge pump signal CP_D. For example, the first boost module 210 includes transistors T1 to T4 and pumping capacitors C1 and C2. One end of the pumping capacitor C2 is connected to the first clock signal CLK1, and the other end is connected to the boosting node B inside the first boost module 210. One end of the pumping capacitor C1 is connected to the inverted signal CLK1B of the first clock signal, and the other end is connected to the boosting node A inside the first boost module 210. Transistors T1 to T4 adopt a differential cross-coupling architecture, transistors T1 and T2 are N-type field effect transistors, transistors T3 and T4 are P-type field effect transistors, the sources of transistors T1 and T2 are connected to the power supply voltage VCC, the drains of transistors T1 and T3 and the gates of transistors T2 and T4 are connected to the boost node A, the drains of transistors T2 and T4 and the gates of transistors T1 and T3 are connected to the boost node B, and the sources of transistors T3 and T4 are connected to the output end of the first charge pump signal CP_D. The first boost module 210 utilizes the characteristic that the voltages at both ends of the pumping capacitors C1 and C2 cannot change suddenly, and continuously superimposes the voltage difference between the high and low levels of the first clock signals CLK1 and CLK1B on the power supply voltage VCC, thereby obtaining a first charge pump signal CP_D higher than the power supply voltage VCC at the output end.

[0032] The second boost module 220 is used to perform a pumping operation on the power supply voltage VCC in response to the second clock signal CLK2 to generate a second charge pump signal CP_G. For example, the second boost module 220 includes transistors T5 to T8 and pumping capacitors C3 and C4. One end of the pumping capacitor C4 is connected to the second clock signal CLK2, and the other end is connected to the boosting node D inside the second boost module 220. One end of the pumping capacitor C3 is connected to the inverted signal CLK2B of the second clock signal, and the other end is connected to the boosting node C inside the second boost module 220. Transistors T5 to T8 adopt a differential cross-coupling architecture, transistors T5 and T6 are N-type field effect transistors, transistors T7 and T8 are P-type field effect transistors, the sources of transistors T5 and T6 are connected to the power supply voltage VCC, the drains of transistors T5 and T7 and the gates of transistors T6 and T8 are connected to the boost node C, the drains of transistors T6 and T8 and the gates of transistors T5 and T7 are connected to the boost node D, and the sources of transistors T7 and T8 are connected to the output end of the second charge pump signal CP_G. The second boost module 220 utilizes the characteristic that the voltages at both ends of the pumping capacitors C3 and C4 cannot change suddenly, and continuously superimposes the voltage difference between the high and low levels of the second clock signals CLK2 and CLK2B on the power supply voltage VCC, thereby obtaining a second charge pump signal CP_G higher than the power supply voltage VCC at the output end.

[0033] The notch filter 230 is used for filtering the second charge pump signal CP_G in response to the sampling clock signal CS_CLK to obtain a control voltage signal VCTRL.

[0034] The output transistor Mn0 is implemented, for example, by an N-type field effect transistor, whose first end (for example, the drain) is used to receive the first charge pump signal CP_D, and the control end (for example, the gate) is used to receive the control voltage signal VCTRL, and adjust the output voltage signal Vout of the output end of the charge pump circuit according to the control voltage signal.

[0035] The filter module 260 is connected between the second end (e.g., source) of the output transistor Mn0 and the output end of the charge pump circuit 200, and is used to reduce the noise of the output voltage signal Vout. For example, the filter module 260 includes a resistor Rs and a capacitor Cs, the resistor Rs and the capacitor Cs are connected in series between the output transistor Mn0 and the power supply voltage VCC, and the intermediate node of the resistor Rs and the capacitor Cs is connected to the output end of the charge pump circuit 200 to provide the output voltage signal Vout.

[0036] In this embodiment, the first charge pump signal CP_D generated by the first boost module 210 is used to provide a load current to the output transistor Mn0, and the second charge pump signal CP_G generated by the second boost module 220 is used to generate a control voltage signal VCTRL with a very small ripple amplitude through the notch filter 230 to provide a gate control voltage to the output transistor Mn0. In this way, the second charge pump signal CP_G provided to the gate of the output transistor Mn0 is equivalent to having no load, and all load pressure is on the first charge pump signal CP_D, thereby greatly reducing the capacitance value of the pumping capacitors C3 and C4. It is only necessary to increase the capacitance value of the pumping capacitors C1 and C2 according to the load of the charge pump circuit, so the overall area consumption of the second boost module 220 is very small. Furthermore, when the output transistor Mn0 operates in the saturation region, the output voltage signal Vout of the charge pump circuit 200 is VCTRL-Vgs_Mn0. Therefore, the ripple amplitude on the output voltage signal Vout can be reduced by only reducing the amplitude of the ripple on the control voltage signal VCTRL. The ripple amplitude on the output voltage signal Vout is independent of the ripple amplitude of the first charge pump signal CP_D. It is only necessary to ensure that the amplitude of the first charge pump signal CP_D can satisfy the requirement for the output transistor Mn0 to operate in the saturation region. This can be easily achieved by controlling the capacitance values ​​of the pumping capacitors C1 and C2. Because the amplitudes of the first charge pump signal CP_D and the second charge pump signal CP_G are almost the same without considering the load, the present invention does not need to specifically optimize the ripple amplitude of the first charge pump signal CP_D. Compared with the existing structure, under the same load conditions, the capacitance values ​​of the pumping capacitors C1 and C2 are no longer limited by the ripple amplitude and can be relatively much smaller, thereby saving circuit area.

[0037] Furthermore, this embodiment also uses a notch filter 230 to filter the second charge pump signal CP_G to obtain a control voltage signal VCTRL applied to the gate of the output transistor Mn0. The notch filter can attenuate signals within a specific frequency range while allowing other frequency signals to pass intact, thereby reducing the ripple amplitude in the control voltage signal VCTRL.

[0038] Figure 3 FIG. 2 shows a circuit diagram of a notch filter according to an embodiment of the present invention. Figure 3As shown, the notch filter 230 of this embodiment includes switches S1 to S4 and capacitors C5 and C6. The first end of switch S1 is connected to the second charge pump signal CP_G, the second end is connected to the first end of switch S2, and the second end of switch S2 is connected to the output end of the control voltage signal VCTRL. The first end of switch S3 is connected to the second charge pump signal CP_G, the second end is connected to the first end of switch S4, and the second end of switch S4 is connected to the output end of the control voltage signal VCTRL. The first end of capacitor C5 is connected to the power supply voltage VCC, and the second end of capacitor C5 is connected to the common node of switch S1 and switch S2. The first end of capacitor C6 is connected to the power supply voltage VCC, and the second end of capacitor C6 is connected to the common node of switch S3 and switch S4. The on and off of switch S1 and switch S4 are controlled by the sampling clock signal CS_CLK, and the on and off of switch S2 and switch S3 are controlled by the inverted signal CS_CLKB of the sampling clock signal.

[0039] In the present embodiment, since one end of the capacitor C5 and the capacitor C6 are connected to the power supply voltage VCC, during the sampling process of the notch filter 230, the voltage difference between the two ends of the capacitor C5 and the capacitor C6 is relatively small, so that the capacitor C5 and the capacitor C6 can be implemented using a metal-insulator-metal (MIM) capacitor. Since there is no load current, the areas of the capacitors C5 and C6 and the four switches S1~S4 can be very small, so the overall area consumption of the notch filter 230 is very small.

[0040] Further, the notch filter 230 is used to charge and discharge the capacitor C5 and the capacitor C6 according to the sampling clock signal CS_CLK. When the sampling clock signal CS_CLK is at a high level, the switch S1 and the switch S4 are turned on, and the switch S2 and the switch S3 are turned off, the capacitor C5 samples the second charge pump signal CP_G, and provides an output voltage to the output end of the notch filter 230 through the capacitor C6; when the sampling clock signal CS_CLK is at a low level, the switch S1 and the switch S4 are turned off, and the switch S2 and the switch S3 are turned on, the capacitor C6 samples the second charge pump signal CP_G, and provides an output voltage to the output end of the notch filter 230 through the capacitor C5. It can be seen that the center frequency of the notch filter 230 of the present embodiment is twice the frequency of the sampling clock signal CS_CLK. Since the center frequency of the notch filter 230 needs to be equal to the ripple frequency of the second charge pump signal CP_G generated by the second boost module 220, and the ripple frequency of the second charge pump signal CP_G is twice the frequency of the second clock signal CLK2, in order to ensure the normal operation of the notch filter 230, the frequency of the sampling clock signal CS_CLK needs to be consistent with the frequency of the second clock signal CLK2.

[0041] However, if the second clock signal CLK2 is in phase with the sampling clock signal CS_CLK, the problem that the notch filter 230 samples the transient glitches caused by the switch switching in the second boost module 220 may occur during the circuit operation. In order to avoid the above problem, in this embodiment, it is also necessary to ensure that the frequency of the sampling clock signal CS_CLK is the same as the frequency of the second clock signal CLK2 and there is a phase difference of 90°, so that the notch filter 230 can be fixedly sampled to the middle point of the output cycle of the second charge pump signal CP_G, so that the control voltage signal VCTRL obtained by filtering can be more stable, thereby avoiding the transient glitches caused by the switch switching.

[0042] Further, the sampling clock signal CS_CLK can be obtained by dividing the clock on the boost node in the first boost module 210. Figure 2 The charge pump circuit 200 of this embodiment further includes a sampling control circuit 240 and a clock generation circuit 250. The clock generation circuit 250 is used to generate the first clock signal CLK1 and its inverted signal CLK1B, and perform a two-frequency division operation on the first clock signal CLK1 to generate the second clock signal CLK2 and its inverted signal CLK2B, and apply them to the first boost module 210 and the second boost module 220 respectively. Therefore, the frequency of the first clock signal CLK1 of this embodiment is twice the frequency of the second clock signal CLK2.

[0043] Furthermore, the sampling control circuit 240 is connected to the boost node B in the first boost module 210 , and is used to generate a sampling clock signal CS_CLK applied to the notch filter 230 according to the voltage Vc at the boost node B, so as to control the center frequency of the notch filter 230 .

[0044] Further, Figure 4 FIG. 2 shows a circuit diagram of a sampling control circuit according to an embodiment of the present invention. Figure 4 As shown, the sampling control circuit 240 includes an inverter INV1 and a D flip-flop DFF1, wherein the input of the inverter INV1 is connected to the boost node B in the first boost module 210 to receive the voltage Vc, and the output of the inverter INV1 is used to provide the voltage Vc_b. The clock terminal of the D flip-flop DFF1 is connected to the voltage Vc_b, the first output terminal of the D flip-flop DFF1 is used to output the sampling clock signal CS_CLK, the second output terminal of the D flip-flop DFF1 is used to output the inverted signal CS_CLKB of the sampling clock signal, and the data terminal of the D flip-flop DFF1 is short-circuited with the second output terminal. In this embodiment, the voltage Vc_b is divided into two by the D flip-flop DFF1 to generate the sampling clock signal CS_CLK and its inverted signal CS_CLKB.

[0045] Further, since the voltage frequency and phase at the boost node B in the first boost module 210 are the same as the frequency and phase of the first clock signal CLK1, only the voltage domain is different, the frequency of the sampling clock signal CS_CLK obtained after the inverter INV1 and the D flip-flop DFF1 perform a two-frequency division operation is 1 / 2 of the frequency of the first clock signal CLK1, so the frequency of CS_CLK is the same as the frequency of the second clock signal CLK2, and its phase is 90° different from the second clock signal CLK2. Therefore, through the above operation, the sampling clock signal CS_CLK with the same frequency as the second clock signal CLK2 and a phase difference of 90° can be obtained.

[0046] Furthermore, the charge pump circuit 200 of the present embodiment can generate a sampling clock for controlling the center frequency of the notch filter according to the voltage signal inside the charge pump circuit by using an inverter and a D flip-flop, and can easily achieve a 90° phase difference between the sampling clock signal CS_CLK and the second clock signal CLK2, thereby eliminating the need to arrange an additional complex clock generator in the circuit to generate the sampling clock signal, which is beneficial to reducing the area and cost of the circuit.

[0047] Furthermore, the charge pump circuit 200 of this embodiment also includes an inverter INV2 connected to the boost node A of the first boost module 210, the input of the inverter INV2 is connected to the boost node A, and the output of the inverter INV2 can be floating or connected to another D trigger, so that the loads of the two boost nodes of the first boost module 210 can be the same, which helps to improve the symmetry of the two boost nodes of the first boost module 210, and thereby improve the stability of the entire circuit.

[0048] Figure 5 FIG. 2 shows a circuit diagram of a clock generation circuit according to an embodiment of the present invention. Figure 5 As shown, the clock generation circuit 250 includes an oscillator circuit 251, a frequency divider 252, and inverters INV3 and INV4. The oscillator circuit 251 is, for example, a ring oscillator, for generating the first clock signal CLK1. The inverter INV3 is used to generate an inverted signal CLK1B of the first clock signal CLK1. The frequency divider 252 is used to divide the first clock signal CLK1 by two to generate the second clock signal CLK2. The inverter INV4 is used to generate an inverted signal CLK2B of the second clock signal CLK2.

[0049] Figure 6 FIG. 2 shows a timing diagram of the operation of the charge pump circuit according to an embodiment of the present invention. Figure 6In the embodiment, the frequency of the first clock signal CLK1 is twice the frequency of the second clock signal CLK2 and the frequency of the sampling clock signal CS_CLK, and the phase of the sampling clock signal CS_CLK is 90° different from the phase of the second clock signal CLK2. Therefore, the notch filter 230 can be fixedly sampled at the middle point of the output cycle of the second charge pump signal CP_G, thereby obtaining a more stable control voltage signal VCTRL with a smaller ripple amplitude. Since the ripple of the output voltage signal Vout of the charge pump circuit 200 is consistent with the ripple of the control voltage signal VCTRL, this embodiment can significantly reduce the ripple amplitude of the output voltage signal Vout.

[0050] In summary, the charge pump circuit of the present invention includes a first boost module, a second boost module, a notch filter and an output transistor. The first charge pump signal generated by the first boost module provides a load current to the output transistor. The second charge pump signal generated by the second boost module is filtered by the notch filter to obtain a control voltage signal applied to the gate of the output transistor. The notch filter can weaken the signal within a specific frequency range while allowing other frequency signals to pass as is, thereby reducing the ripple amplitude of the control voltage signal. Since the ripple of the output voltage signal of the charge pump circuit is consistent with the ripple of the control voltage of the output transistor when the output transistor operates in the saturation region, the ripple amplitude of the output voltage of the charge pump circuit of the present invention can also be significantly reduced. Therefore, the charge pump circuit of the present invention can achieve a very low output ripple amplitude at a very small area and power consumption cost, and has a strong load capacity. When used as a power supply, it can provide many benefits such as high efficiency, low noise, miniaturization, cost-effectiveness and flexibility, and is suitable for a variety of electronic devices and application scenarios.

[0051] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0052] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A charge pump circuit, comprising: A first boost module, configured to perform a pump-up operation on a power supply voltage in response to a first clock signal to generate a first charge pump signal; A second boost module, configured to perform a pump-up operation on the power supply voltage in response to a second clock signal to generate a second charge pump signal; a notch filter, configured to filter the second charge pump signal in response to a sampling clock signal to obtain a control voltage signal; as well as An output transistor, wherein the first end of the output transistor is used to receive the first charge pump signal, the control end is used to receive the control voltage signal, and the output voltage signal of the output end of the charge pump circuit is adjusted according to the control voltage signal.

2. The charge pump circuit according to claim 1, wherein: The sampling clock signal has the same frequency as the second clock signal and has a phase difference of 90°.

3. The charge pump circuit according to claim 1, wherein: The frequency of the first clock signal is twice the frequency of the second clock signal and the sampling clock signal.

4. The charge pump circuit according to claim 1, wherein: The first boost module and the second boost module each include at least one transistor forming a differential cross-coupled architecture, at least one boost node, and at least one pump-up capacitor, wherein a first end of the at least one pump-up capacitor is connected to a clock signal, and a second end of the at least one pump-up capacitor is connected to the boost node.

5. The charge pump circuit according to claim 4, wherein: Also includes: The sampling control circuit is connected to at least one boosting node of the first boosting module and generates the sampling clock signal according to the voltage at the boosting node.

6. The charge pump circuit according to claim 5, wherein: The first boost module comprises: a first pumping capacitor, wherein a first end of the first pumping capacitor is connected to an inverted signal of the first clock signal, and a second end of the first pumping capacitor is connected to a first boosting node; a second pumping capacitor, wherein a first end of the second pumping capacitor is connected to the first clock signal, and a second end of the second pumping capacitor is connected to a second boosting node; A first transistor connected between the first boost node and a power supply voltage, wherein a control terminal of the first transistor is connected to the second boost node; A second transistor connected between the second boost node and the power supply voltage, wherein a control terminal of the second transistor is connected to the first boost node; A third transistor connected between the output terminal of the first charge pump signal and the first boost node, wherein the control terminal of the third transistor is connected to the second boost node; and a fourth transistor connected between the output terminal of the first charge pump signal and the second boost node, wherein the control terminal of the fourth transistor is connected to the first boost node, The sampling control circuit is connected to the second boost node and generates the sampling clock signal according to the voltage at the second boost node.

7. The charge pump circuit according to claim 6, wherein: The sampling control circuit comprises: a first inverter, wherein an input terminal of the first inverter is connected to the second boost node; A first D flip-flop, wherein a clock terminal of the first D flip-flop is connected to an output terminal of the first inverter, a first output terminal of the first D flip-flop is used to output the sampling clock signal, a second output terminal of the first D flip-flop is used to output an inverted signal of the sampling clock signal, and a data terminal of the first D flip-flop is short-circuited with the second output terminal.

8. The charge pump circuit according to claim 7, wherein: Also includes: A second inverter, wherein an input terminal of the second inverter is connected to the first boost node, and an output terminal of the second inverter is floating or connected to a second D flip-flop.

9. The charge pump circuit according to claim 3, further comprising: The clock generating circuit comprises an oscillator circuit and a frequency divider, wherein the oscillator circuit is used to generate the first clock signal, and the frequency divider is used to perform a two-frequency division operation on the first clock signal to generate the second clock signal.

10. The charge pump circuit according to claim 1, wherein: The notch filter comprises: a first switch, wherein a first end of the first switch is connected to the second charge pump signal; a second switch, wherein a first end of the second switch is connected to a second end of the first switch, and a second end of the second switch is connected to an output end of the control voltage signal; a third switch, a first end of the third switch being connected to the second charge pump signal; a fourth switch, wherein a first end of the fourth switch is connected to a second end of the third switch, and a second end of the fourth switch is connected to an output end of the control voltage signal; a first capacitor, wherein a first end of the first capacitor is connected to a power supply voltage, and a second end of the first capacitor is connected to a common node of the first switch and the second switch; and a second capacitor, a first end of the second capacitor being connected to the power supply voltage, and a second end of the second capacitor being connected to a common node of the third switch and the fourth switch, The first switch and the fourth switch are controlled by the sampling clock signal, and the second switch and the third switch are controlled by an inverted signal of the sampling clock signal.

11. The charge pump circuit according to claim 10, wherein: The notch filter charges and discharges the first capacitor and the second capacitor according to the sampling clock signal, Wherein, when the sampling clock signal is at a high level, the first capacitor samples the second charge pump signal, and the second capacitor provides an output voltage to the output end of the notch filter; When the sampling clock signal is at a low level, the second capacitor samples the second charge pump signal, and the first capacitor provides an output voltage to the output end of the notch filter.

12. The charge pump circuit according to claim 1 , further comprising: A filtering module comprises a first resistor and a third capacitor, wherein the first resistor and the third capacitor are connected between the second end of the output transistor and the power supply voltage, and an intermediate node between the first resistor and the third capacitor is connected to the output end of the charge pump circuit, and the filtering module is used to reduce the noise of the output voltage signal.

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