Current balancing two-phase COT BUCK circuit and current balancing method

Abstract

This invention discloses a current-balanced two-phase COT BUCK circuit and a current balancing method. The circuit includes two BUCK circuits (4) and a current balancing circuit (6). The output terminals of the two BUCK circuits (4) are connected together and output the required output voltage. The two BUCK circuits (4) are turned on alternately, and each time they are turned on for a period of time before being turned off. The two input terminals of the current balancing circuit (6) are connected to the voltage measurement points of the two BUCK circuits (4) respectively. The output terminal of the current balancing circuit (6) is indirectly connected to the switching transistor of the second BUCK circuit (4). The current balancing circuit (6) is used to simultaneously sample the signals of the voltage measurement points of the two BUCK circuits (4) and compare them. According to the comparison result, the on-time of the second BUCK circuit (4) is adjusted so that the duty cycle of the second BUCK circuit (4) tracks the duty cycle of the first BUCK circuit (4), thereby achieving the purpose of balancing the inductor current of the two BUCK circuits.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuits and power supplies, and in particular to a current-balancing two-phase COT BUCK circuit and a current balancing method. Background Technology

[0002] With technological advancements, multiphase parallel technology is widely used in power management to improve output current and efficiency. Theoretically, each phase circuit should have identical parameters, resulting in equal inductor currents. However, in practice, due to process errors, parasitic parameters, and other factors, the output current can deviate significantly. When two currents are unequal or even differ excessively, one current can deviate too much from its normal value, leading to reduced efficiency, overheating, reliability issues, and even chip damage.

[0003] The information disclosed in this background section is included only to enhance the understanding of the context of this disclosure, and therefore may contain information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a current-balanced two-phase COT BUCK circuit and a current balancing method, in view of the above-mentioned defects of the prior art.

[0005] The technical solution adopted by this invention to solve its technical problem is:

[0006] On the one hand, a current-balanced two-phase COT BUCK circuit is constructed, including two BUCK circuits and a current-balanced circuit;

[0007] The output terminals of the two BUCK circuits are connected together to output the required output voltage, and the two BUCK circuits are turned on alternately. Each time they are turned on, they are turned off after a certain period of time.

[0008] The two input terminals of the current equalization circuit are connected to the voltage measurement points of the two BUCK circuits respectively, and the output terminal of the current equalization circuit is indirectly connected to the switching transistor of the second BUCK circuit. The current equalization circuit is used to simultaneously sample the signals of the voltage measurement points of the two BUCK circuits and compare them. Based on the comparison result, the conduction time of the second BUCK circuit is adjusted so that the duty cycle of the second BUCK circuit tracks the duty cycle of the first BUCK circuit.

[0009] Furthermore, in the current-balancing dual-phase COT BUCK circuit described in this invention, the conduction time is determined by the charging time required for the current source to charge the capacitor to the charging reference voltage, and the current balancing circuit includes:

[0010] The differential voltage amplifier circuit has two input terminals connected to the voltage measurement points of two BUCK circuits respectively. It is used to subtract the signal of the voltage measurement point of the first BUCK circuit from the signal of the voltage measurement point of the second BUCK circuit and perform differential amplification to output the error voltage.

[0011] A voltage-to-current circuit is used to convert the error voltage into an error current and to superimpose the error current onto the current source to adjust the charging time.

[0012] Furthermore, the current balancing dual-phase COT BUCK circuit of the present invention also includes two COT circuits corresponding to the two BUCK circuits. The BUCK circuit is triggered to start conducting by a conduction signal, and the BUCK circuit is triggered to stop conducting by a shutdown signal output by the corresponding COT circuit.

[0013] The COT circuit is used to control the current source to start charging the capacitor when the conduction signal is triggered, compare the voltage of the capacitor with the charging reference voltage, and generate the shutdown signal based on the comparison result.

[0014] Furthermore, in the current-balanced two-phase COT BUCK circuit described in this invention, the current source is related to the input voltage of the BUCK circuit, and the charging reference voltage is related to the output voltage.

[0015] Furthermore, in the current-balanced two-phase COT BUCK circuit of the present invention, the COT circuit includes a first current mirror, a charging capacitor, a discharging switch, and a first comparator. The current source is connected in series in the control branch of the first current mirror, the charging capacitor is connected in series in the mirror branch of the first current mirror, the positive terminal of the charging capacitor is connected to the positive input terminal of the first comparator, and the positive terminal of the charging capacitor is also grounded through the discharging switch. The control terminal of the discharging switch receives the turn-on signal to rapidly discharge the charging capacitor under the trigger of the turn-on signal. The negative input terminal of the first comparator is connected to the charging reference voltage, and the output terminal of the first comparator outputs the turn-off signal.

[0016] In the COT circuit corresponding to the second BUCK circuit, the positive terminal of the current source is also connected to the voltage-to-current circuit to superimpose the error current.

[0017] Furthermore, the current-balanced dual-phase COT BUCK circuit of the present invention also includes two filter circuits corresponding to the two BUCK circuits. The two input terminals of the differential voltage amplifier circuit are respectively connected to the voltage measurement points of the corresponding BUCK circuits via the corresponding filter circuits. The filter circuits are used to filter the signals at the voltage measurement points to obtain duty cycle signals, which are then input to the corresponding BUCK circuits.

[0018] Furthermore, in the current-balanced two-phase COT BUCK circuit described in this invention, the voltage-to-current circuit includes an error amplifier, a bias current source, a current conversion resistor, and a second current mirror.

[0019] The error amplifier's positive input terminal is connected to the error voltage, the second terminal of the current conversion resistor is grounded, the output terminal of the error amplifier is connected to the gate of the control transistor and the mirror transistor of the second current mirror, the drain of the control transistor of the second current mirror, the first terminal of the current conversion resistor, and the negative input terminal of the error amplifier are connected together and then connected to the output terminal of the error amplifier via a compensation network, the second terminal of the current conversion resistor is grounded, the source of the control transistor of the second current mirror and the source of the mirror transistor are connected to the power supply, the drain of the mirror transistor of the second current mirror is grounded via a bias current source, and the drain of the mirror transistor of the second current mirror outputs the error current.

[0020] Furthermore, the current-balanced dual-phase COT BUCK circuit of the present invention also includes a dual-phase conduction control circuit, whose input terminal is connected to the common junction of the output terminals of the two BUCK circuits, and whose two output terminals respectively output two conduction signals corresponding to the two BUCK circuits; the dual-phase conduction control circuit is used to compare the output voltage with the reference voltage, and control the two conduction signals to be triggered alternately according to the comparison result.

[0021] Furthermore, the current-balanced two-phase COT BUCK circuit described in this invention also includes two driving circuits corresponding to the two BUCK circuits.

[0022] The two output terminals of the dual-phase conduction control circuit are connected one-to-one to the first input terminals of the two drive circuits. The second input terminal of the drive circuit is connected to the output terminal of the corresponding COT circuit. The output terminal of the drive circuit is connected to the control terminal of the switching transistor of the corresponding BUCK circuit. The drive circuit is used to output a drive signal for controlling the switching transistor of the BUCK circuit according to the conduction signal and the shutdown signal.

[0023] Secondly, a current balancing method based on the aforementioned current balancing two-phase COT BUCK circuit is constructed, the method comprising:

[0024] Simultaneously sample and compare the voltage measurement points of the two BUCK circuits. Adjust the conduction time of the second BUCK circuit according to the comparison result so that the duty cycle of the second BUCK circuit tracks the duty cycle of the first BUCK circuit.

[0025] The current-balancing dual-phase COT BUCK circuit and current-balancing method of the present invention have the following beneficial effects: The present invention utilizes a current-balancing circuit connected to the voltage measurement points of two BUCK circuits respectively, and the output terminal of the current-balancing circuit is indirectly connected to the switching transistor of the second BUCK circuit. The current-balancing circuit simultaneously samples the signals of the voltage measurement points of the two BUCK circuits and compares them. Based on the comparison result, the conduction time of the second BUCK circuit is adjusted so that the duty cycle of the second BUCK circuit tracks the duty cycle of the first BUCK circuit, thereby achieving the purpose of balancing the inductor current of the two BUCK circuits. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort:

[0027] Figure 1 This is a schematic diagram of the current-balanced two-phase COT BUCK circuit of the present invention;

[0028] Figure 2 This is a waveform diagram of the control signal according to an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the COT circuit corresponding to the main BUCK;

[0030] Figure 4 This is a schematic diagram of the COT circuit corresponding to BUCK;

[0031] Figure 5 This is a circuit diagram of a specific implementation of a current balancing circuit;

[0032] Figure 6 yes Figure 5 The equivalent circuit diagram;

[0033] Figure 7 This is a comparison chart of current deviations in a two-phase buck converter. Detailed Implementation

[0034] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Typical embodiments of the invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present invention more thorough and complete. It should be understood that the embodiments of the present invention and the specific features thereof are detailed descriptions of the technical solutions of this application, and not limitations thereof. Where there is no conflict, the embodiments of the present invention and the technical features thereof can be combined with each other.

[0035] refer to Figure 1 The current balancing dual-phase COT BUCK circuit of the present invention includes a dual-phase conduction control circuit 1, two BUCK circuits 4, two drive circuits 3 corresponding to the two BUCK circuits 4, two COT circuits 2 corresponding to the two BUCK circuits 4, two filter circuits 5 corresponding to the two BUCK circuits 4, and a current balancing circuit 6.

[0036] A BUCK circuit, also known as a step-down converter, is a DC-DC converter based on the principle of inductor energy storage. For example... Figure 1 In this circuit, BUCK circuit 4 is used to convert the input voltage Vin to DC-DC converter and output the desired voltage Vout. The output terminals of the two BUCK circuits 4 are connected together. The first BUCK circuit 4 is designated as the master BUCK (BUCK_MST), and the second BUCK circuit 4 is designated as the slave BUCK (BUCK_SLV). The two BUCK circuits 4 have the same structure and dimensions, and their peripheral components (including inductors and capacitors) are also identical. For example, in a specific embodiment, BUCK circuit 4 includes upper and lower bridge arms, an inductor, and an output capacitor. Each bridge arm can consist of one or more switching transistors. For instance, in this embodiment, M1 and M2 constitute the upper and lower bridge arms of one BUCK circuit 4, and M3 and M4 constitute the upper and lower bridge arms of the other BUCK circuit 4. The upper and lower bridge arms are connected in series between the input voltage Vin and ground. The connection point of the upper and lower bridge arms in BUCK circuit 4 is the voltage measurement point mentioned in this paper. The voltage measurement point is connected to the positive terminal of the output capacitor via an inductor, and the negative terminal of the output capacitor is grounded. The positive terminal of the output capacitor is the output terminal of BUCK circuit 4. The positive terminals of the output capacitors of the two BUCK circuits 4 are connected together, resulting in an output Vout. The purpose of this invention is to achieve inductor current balancing between the two BUCK circuits 4.

[0037] The two BUCK circuits 4 are alternately turned on, and each time they are turned on for a certain period of time before being turned off. (Reference) Figure 2The drive signals for the switching transistors of the two BUCK circuits 4 are PMW_MST (controlling M1 and M2) and PMW_SLV (controlling M3 and M4), respectively. A high level drive signal turns on the corresponding switch, and a low level drive signal turns off the corresponding switch.

[0038] Specifically, each of the BUCK circuits 4 is initiated by a turn-on signal (specifically, triggered by the rising edge of the turn-on signal), and the BUCK circuit 4 is de-initiated by a turn-off signal output from the corresponding COT circuit 2 (specifically, triggered by the rising edge of the turn-off signal). (See reference) Figure 2 The turn-on signals that trigger the two BUCK circuits 4 to start conducting are on_start_MST and on_start_SLV, respectively, and the turn-off signals that trigger the two BUCK circuits 4 to stop conducting are on_end_MST and on_end_SLV, respectively. Specifically, on_start_MST and on_end_MST generate PMW_MST. Because the PWM signal generation in this embodiment is based on the rising edge being valid, the rising edge of on_start_MST determines the rising edge of PMW_MST, and the rising edge of on_end_MST determines the falling edge of PMW_MST; similarly, on_start_SLV and on_end_SLV generate PMW_SLV, the rising edge of on_start_SLV determines the rising edge of PMW_SLV, and the rising edge of on_end_SLV determines the falling edge of PMW_SLV.

[0039] The current sharing scheme of the present invention adjusts the inductor current of the slave BUCK by adjusting only the conduction time of the switching transistors M3 and M4 of the slave BUCK, so that it tracks the inductor current of the master BUCK. Specifically, it adjusts the falling edge of PMW_SLV, that is, adjusts the trigger time of on_end_SLV. Specifically, to adjust the triggering time of on_end_SLV, this invention designs the conduction time of BUCK circuit 4 to be determined by the charging time required for the current source to charge the capacitor to the charging reference voltage. For example, COT circuit 2 controls the current source to start charging the capacitor when the conduction signal is triggered, compares the capacitor voltage with the charging reference voltage, and generates the shutdown signal based on the comparison result. On the other hand, signals from the voltage measurement points of two BUCK circuits 4 are collected, and through comparison, amplification, and voltage-to-current processing, an error current is obtained. This error current is superimposed on the current source used for charging from the COT circuit 2 corresponding to BUCK. Thus, by superimposing the error current on the current source, the charging time of the COT circuit 2 corresponding to BUCK can be adjusted, which also adjusts the conduction time of BUCK.

[0040] The following section provides a detailed explanation of the specific circuit structure.

[0041] refer to Figure 1 The dual-phase conduction control circuit 1 has its input terminal connected to the common junction of the output terminals of two BUCK circuits 4. Its two output terminals output two conduction signals, on_start_MST and on_start_SLV, corresponding to the two BUCK circuits 4, respectively. The dual-phase conduction control circuit 1 is used to compare the output voltage Vout with the reference voltage VREF. Based on the comparison result, it controls the two conduction signals on_start_MST and on_start_SLV to be triggered alternately, i.e., alternately switched to a high level. Alternating triggering specifically means that when the output voltage Vout is lower than the reference voltage VREF, one conduction signal, such as on_start_MST, is triggered; then, the next time the output voltage Vout is lower than the reference voltage VREF, the other conduction signal, such as on_start_SLV, is triggered, and so on.

[0042] Specifically, the two-phase conduction control circuit 1 includes a comparator and a two-phase control logic circuit. The positive input terminal of the comparator is connected to the output voltage Vout, and the negative input terminal is connected to the reference voltage VREF. Therefore, when Vout is less than VREF, the comparator outputs a low level. The output terminal of the comparator is connected to the two-phase control logic. When the comparator outputs a low level, the two-phase control logic generates a rectangular wave (low-level triggering to generate a rectangular wave is a common technique, which will not be elaborated here). The two-phase control logic has two output terminals, and it sends the generated rectangular wave to the two output terminals alternately. For example, when Vout was less than VREF last time, the first output terminal output a rectangular wave; the next time Vout is less than VREF, the second output terminal outputs a rectangular wave. It can be understood that outputting a signal alternately between the two output terminals can be achieved using a dual-channel switch. For example, the generated rectangular wave can be sent to the input terminal of the dual-channel switch, and the generated rectangular wave can be used to trigger the switching of the output path of the dual-channel switch. This technology is existing and relatively mature, and will not be elaborated here.

[0043] The two conduction signals, on_start_MST and on_start_SLV, generated by the dual-phase conduction control circuit 1, are supplied to the drive circuit 3 and the COT circuit 2, respectively. Specifically, the two output terminals of the dual-phase conduction control circuit 1 are connected one-to-one to the first input terminals of the two drive circuits 3, and the two output terminals of the dual-phase conduction control circuit 1 are also connected one-to-one to the input terminals of the two COT circuits 2. The second input terminal of the drive circuit 3 is connected to the output terminal of the corresponding COT circuit 2, and the output terminal of the drive circuit 3 is connected to the control terminal of the switching transistor of the corresponding BUCK circuit 4.

[0044] The first drive circuit 3 outputs a drive signal PMW_MST to control the main BUCK switches M1 and M2 based on the on-state signal on_start_MST and the off-state signal on_end_MST. The second drive circuit 3 outputs a drive signal PMW_SLV to control the slave BUCK switches M3 and M4 based on the on-state signal on_start_SLV and the off-state signal on_end_SLV. As previously described, specifically, the drive PWM signals for the switches are generated using rising edge triggering: the rising edge of on_start_MST triggers the rising edge of PMW_MST, the rising edge of on_end_MST triggers the falling edge of PMW_MST, the rising edge of on_start_SLV triggers the rising edge of PMW_SLV, and the rising edge of on_end_SLV triggers the falling edge of PMW_SLV.

[0045] refer to Figure 3-4 The two COT circuits 2 have identical structures, except that the COT circuit 2 corresponding to the BUCK circuit is also connected to a current equalization circuit 6. The two input terminals of the current equalization circuit 6 are connected to the voltage measurement points of the two BUCK circuits 4, respectively. The output terminal of the current equalization circuit 6 is indirectly connected to the switching transistor of the second BUCK circuit 4 through the COT circuit 2. The current equalization circuit 6 is used to simultaneously sample and compare the signals from the voltage measurement points of the two BUCK circuits 4. Based on the comparison result, it adjusts the conduction time of the second BUCK circuit 4 so that the duty cycle of the second BUCK circuit 4 tracks the duty cycle of the first BUCK circuit 4.

[0046] Please refer to the following first. Figure 3 Taking the COT circuit 2 corresponding to the main BUCK as an example, the basic structure and working principle of the COT circuit 2 will be introduced.

[0047] Specifically, COT circuit 2 includes a first current mirror, a charging capacitor C, a discharging switch M0, and a first comparator U1. The first current mirror is a single-transistor current mirror, including a control branch and a mirror branch. The current source I1 is connected in series in the control branch of the first current mirror, and the charging capacitor C is connected in series in the mirror branch of the first current mirror. Specifically, the control branch mainly contains a control transistor, and the mirror branch contains a mirror transistor. The source of the control transistor of the first current mirror is connected to the power supply, and the drain of the control transistor of the first current mirror is connected in series with the current source I1 between it and ground. The current source I1 is related to the input voltage Vin of BUCK circuit 4, and I1 = A * Vin, where A is the conductance constant, which is determined according to the circuit parameters. The source of the mirror transistor of the first current mirror is connected to the power supply. The drain of the mirror transistor of the first current mirror is connected in series with the charging capacitor C between it and ground. The positive terminal of the charging capacitor C is connected to the positive input terminal of the first comparator U1. The positive terminal of the charging capacitor C is also grounded through the discharge switch M0. The control terminal of the discharge switch M0 serves as the input terminal of the COT circuit 2, receiving the on-state signal on_start_MST to rapidly discharge the charging capacitor C when triggered by a high level of the on-state signal on_start_MST. The negative input terminal of the first comparator U1 is connected to the charging reference voltage, which is related to the output voltage. In this embodiment, the charging reference voltage is directly taken as Vout. The output terminal of the first comparator outputs the off-state signal on_end_MST.

[0048] Figure 3 In the process, when the on_start_MST signal is high, the charging capacitor C discharges rapidly. on_start_MST is a short-duration rectangular wave. After the charging capacitor C finishes discharging, it quickly returns to a low level, at which point charging of the charging capacitor C can begin. The first current mirror measures the current IP1 on the control transistor side (…). Figure 3 Mirroring IP1 (where I1 = I1) gives IP2, which is used to charge the capacitor C. When the capacitor charging voltage V1 reaches Vout, the output of comparator U1 will switch to a high level, i.e., the on_end_MST signal will have a rising edge. Figure 2 The rising edge of the on_end_MST signal can be used to trigger the falling edge of PMW_MST, which will cause M1 and M2 of the main BUCK to be turned off.

[0049] according to Figure 3 From the circuit diagram, we can see that the conduction time of the switching transistor in the main BUCK circuit 4 is... for:

[0050]

[0051] Duty cycle of BUCK operating in CCM mode for:

[0052]

[0053] Combining equations (2) and (3) above, we can obtain the operating frequency of the switching transistor in the main BUCK circuit 4. for:

[0054]

[0055] Where A is the internally set conductance constant of the circuit, it can be seen that the PWM switching frequency of the main BUCK circuit 4 is... The CCM switching frequency is approximately independent of the input voltage Vin and the output voltage Vout. When the internal parameters A and C are both determined, the switching frequency of the CCM basically does not change with external conditions.

[0056] refer to Figure 4 The structure of COT circuit 2 corresponding to BUCK is the same as Figure 3 The difference is that the positive terminal of the current source I1 in the COT circuit 2 is also connected to the current balancing circuit 6 to superimpose the error current. That is, the charging current of capacitor C in the COT circuit 2 corresponding to BUCK is changed, which can affect the charging time of capacitor C, thus affecting the triggering time of the on_end_SLV signal, and consequently affecting the conduction time of the switch transistor from BUCK.

[0057] The structure and working principle of the current equalization circuit 6 are described below, as well as how it affects the on_end_SLV signal generated by the COT circuit 2 corresponding to BUCK.

[0058] refer to Figure 5-6 The current equalization circuit 6 includes a differential voltage amplifier circuit 61 and a voltage-to-current converter circuit 62.

[0059] The two input terminals of the differential voltage amplifier circuit 61 are respectively connected to the voltage measurement points of the two BUCK circuits 4. It is used to subtract the signal of the voltage measurement point of the first BUCK circuit 4 from the signal of the second BUCK circuit 4 and perform differential amplification to output the error voltage VO.

[0060] The input terminal of the voltage-to-current circuit 62 is connected to the error voltage VO, and the output terminal of the voltage-to-current circuit 62 is connected to the current source, for converting the error voltage VO into an error current I. BAL The error current I BAL The error current I is superimposed on the current source to adjust the charging duration. BALBy superimposing this onto the current source I1, the charging duration can be adjusted, which means adjusting the timing of the rising edge of the on_end_SLV signal, thereby adjusting the turning-off timing of the switching transistors M3 and M4 from BUCK, that is, adjusting the conduction time of M3 and M4.

[0061] Specifically, the differential voltage amplifier circuit 61 includes an error amplifier EA1 and a capacitor Ccomp. The two input terminals of the error amplifier EA1 are connected to the voltage measurement points of the corresponding BUCK circuit 4 via the corresponding filter circuit 5. The signals of the master and slave BUCK voltage measurement points are denoted as SW_MST and SW_SLV, respectively. The filter circuit 5 is used to filter the signals SW_MST and SW_SLV from the voltage measurement points to obtain the duty cycle signals D_MST and D_SLV. The filter circuit 5 is as follows... Figure 1 As shown, RC filtering can be used. The positive input terminal of error amplifier EA1 is connected to D_MST, and the negative input terminal is connected to D_SLV. The output terminal of error amplifier EA1 is grounded through capacitor Ccomp. The voltage at the end of capacitor Ccomp connected to the output terminal of error amplifier EA1 is the error voltage VO.

[0062] Specifically, the voltage-to-current conversion circuit 62 includes an error amplifier EA2 and a bias current source I. PD The error amplifier EA2 is connected to an error voltage VO at its positive input terminal. The second terminal of the current conversion resistor R6 is grounded. The output terminal of the error amplifier EA2 is connected to the gates of the control transistor and the mirror transistor of the second current mirror. The drain of the control transistor of the second current mirror, the first terminal of the current conversion resistor R6, and the negative input terminal of the error amplifier EA2 are connected together and then connected to the output terminal of the error amplifier EA2 via a compensation network (composed of Rc and Cc in series). The second terminal of the current conversion resistor R6 is grounded. The source of the control transistor and the source of the mirror transistor of the second current mirror are connected to the power supply. The drain of the mirror transistor of the second current mirror is connected to the bias current source I. PD The error current is output from the drain of the mirror transistor of the second current mirror when the ground is connected.

[0063] The following is combined Figure 6 ,introduce Figure 5 How it works.

[0064] refer to Figure 5VBP1 and VBP2 are bias voltages generated by other circuits; MN1 and MN2 constitute the input pair of the differential voltage amplifier circuit 61, and MP2 and MP5, MP1 and MP3, MN4 and MN6 constitute current mirrors respectively. MN9 and MN10 constitute the input pair of the voltage-to-current circuit 62, and MP10 and MP12, MN13 and MN15, MP14 and MP16 constitute current mirrors respectively. The circuit structure in Figure 5 can be simplified to Figure 6, and the working principle is as follows: SW_MST and SW_SLV are respectively filtered by RC filters, which are equivalent to the duty cycles D_MST and D_SLV of the master buck and slave buck, and connected to the positive and negative terminals of EA1. After amplification, the output error voltage VO and Ccomp are used for loop stability compensation.

[0065]

[0066] in, This is the gain for EA1. PD This is the bias current. MP16 and MP14 form a current mirror, then:

[0067]

[0068] Taking the direction of current flow into the circuit as positive, we have:

[0069]

[0070] certainly, Figure 5 This is merely an illustration and is not intended to limit the scope of the invention.

[0071] The working process of the embodiments of the present invention is summarized below:

[0072] (1): The waveform diagram of the circuit control signal is as follows Figure 2 As shown, the output voltage Vout is compared with the reference voltage VREF and the error is amplified. The on_start_MST and on_start_SLV signals are generated by the dual-phase conduction control circuit 1, which control the rising edge of the switching control signals PMW_MST and PMW_SLV of the two BUCK circuits respectively.

[0073] (2): Figure 3 The COT circuit 2 generates the on_end_MST signal, which controls the falling edge of the main BUCK switch control signal.

[0074] (3): By sampling the voltages of the two nodes SW_MST and SW_SLV, and filtering them through the filter circuit 5, the duty cycle signals D_MST and D_SLV of the master BUCK and slave BUCK are obtained respectively, and used as the two inputs of the current equalization circuit 6. Figure 5D_MST and D_SLV are processed by EA1 to obtain VO. VO is then processed by voltage-to-current converter 62 to obtain I. BAL .

[0075] (4): such as Figure 2-5 In this context, IL_MST is the inductor current generated by the main BUCK, and IL_SLV is the inductor current generated by the slave BUCK. When the main BUCK inductor current IL_MST is greater than the slave BUCK inductor current IL_SLV, and SW_MST is greater than the SW_SLV voltage, VO increases. Increase, therefore Ipu rises, I BAL As Ip1 decreases, Ip1 = I1 + Ibal, so Ip1 decreases, the charging current of capacitor C decreases, and the rising edge of the on_end_SLV signal of comparator U1 is delayed. Since the on_end_SLV signal controls the falling edge of the BUCK switch signal to adjust the duty cycle, the delayed rising edge of the on_end_SLV signal will increase the conduction time of BUCK, thus increasing the current of BUCK.

[0076] When the inductor current of the main BUCK is less than the inductor current of the slave BUCK, SW_MST is less than the SW_SLV voltage, and VO decreases. Decrease, therefore Ipu decreases, I BAL As Ip1 rises, Ip1 = I1 + Ibal, so as Ip1 rises, the charging current of capacitor C increases. This causes the rising edge of the on_end_SLV signal of comparator U1 to occur earlier. Since the on_end_SLV signal controls the falling edge of the BUCK switch signal, the earlier rising edge of the on_end_SLV signal leads to a shorter conduction time for the BUCK, thus reducing the current in the BUCK. When the loop finally stabilizes, D_MST = D_SLV, at which point the average currents of the master BUCK and slave BUCK are equal.

[0077] After adopting this invention, the current consistency of the two-phase BUCK is significantly improved, such as... Figure 7The input voltage Vin of the two-phase COT BUCK circuit is 5V, the output voltage Vout is 1.1V, and the output current Iout is 8A. The horizontal axis represents the two-phase current deviation, specifically the difference between the two-phase currents divided by the total current (i.e., output current Iout = 8A). Assuming the currents of the master and slave BUCKs are I_MST and I_SLV respectively, the two-phase current deviation = (I_MST - I_SLV) / (Iout / 2). For example, if the two currents are exactly equal, the deviation is 0; or if I_MST = 4.1A and I_SLV = 3.9A, the deviation is (4.1 - 3.9) / 4 = 5%. The vertical axis represents the chip distribution ratio, which means: what percentage of the chips are within the corresponding two-phase current deviation ratio, such as... Figure 7 The results show that 99% of the balanced chips in this invention have a deviation within 5%, while 99% of the unbalanced chips in the prior art have a deviation within 15%. Through... Figure 7 As can be seen, in the prior art, the current deviation of the two-phase buck is 15% when there is no equalization; while in the embodiment of the present invention, after adding the equalization current, the current deviation is reduced to 5%.

[0078] Based on the same inventive concept, this invention also discloses a current balancing method based on the aforementioned current balancing dual-phase COT BUCK circuit. The method includes: simultaneously sampling and comparing the signals at voltage measurement points of two BUCK circuits 4; adjusting the conduction time of the second BUCK circuit 4 according to the comparison result, so that the duty cycle of the second BUCK circuit 4 tracks the duty cycle of the first BUCK circuit 4. Further details can be found in the circuit implementation section and will not be repeated here.

[0079] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0080] The terms "first," "second," and other ordinal numbers used in this specification are used to describe various constituent elements, but these constituent elements are not limited by these terms. The purpose of using these terms is solely to distinguish one constituent element from others. For example, without departing from the scope of the invention, a first constituent element may be named a second constituent element, and similarly, a second constituent element may be named a first constituent element.

[0081] The terms "equal," "identical," "simultaneous," or other similar expressions are not limited to absolute equality or identity in mathematical terms. When applying the rights described in this patent, they can refer to similarity in an engineering sense or within an acceptable error range. Unless otherwise specified, the term "connected" or "linked" in this invention includes not only directly connecting two entities but also indirectly connecting them through other entities that have beneficial improvement effects.

[0082] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claims. The word “comprising” does not exclude the presence of elements or steps not listed in the claims. The word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. The term “or / and” as used herein includes any and all combinations of one or more of the associated listed items.

[0083] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known structures and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0084] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more aspects of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof in the above description of exemplary embodiments of the invention. However, this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Each claim itself is a separate embodiment of the invention.

[0085] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A current-balanced two-phase COT BUCK circuit, characterized in that, Includes two BUCK circuits (4) and a current balancing circuit (6); The output terminals of the two BUCK circuits (4) are connected together and output the required output voltage. The two BUCK circuits (4) are turned on alternately, and each time they are turned on for a period of time before being turned off. The two input terminals of the current equalization circuit (6) are connected to the voltage measurement points of the two BUCK circuits (4) respectively. The output terminal of the current equalization circuit (6) is indirectly connected to the switching transistor of the second BUCK circuit (4). The current equalization circuit (6) is used to simultaneously sample the signals of the voltage measurement points of the two BUCK circuits (4) and compare them. Based on the comparison result, the conduction time of the second BUCK circuit (4) is adjusted so that the duty cycle of the second BUCK circuit (4) tracks the duty cycle of the first BUCK circuit (4). The conduction time is determined by the charging time required for the current source to charge the capacitor to the charging reference voltage. The current balancing circuit (6) includes: The differential voltage amplifier circuit (61) has two input terminals connected to the voltage measurement points of two BUCK circuits (4) respectively. It is used to subtract the signal of the voltage measurement point of the first BUCK circuit (4) from the signal of the voltage measurement point of the second BUCK circuit (4) and perform differential amplification to output the error voltage. The voltage-to-current circuit (62) has the error voltage connected to its input terminal and the current source connected to its output terminal. It is used to convert the error voltage into an error current and to superimpose the error current onto the current source to adjust the charging time. The current equalization dual-phase COT BUCK circuit also includes two filter circuits (5) corresponding to the two BUCK circuits (4). The two input terminals of the differential voltage amplifier circuit (61) are respectively connected to the voltage measurement points of the corresponding BUCK circuit (4) via the corresponding filter circuits (5). The filter circuits (5) are used to filter the signal of the voltage measurement point to obtain the duty cycle signal and then input it to the corresponding BUCK circuit (4).

2. The current-balanced two-phase COT BUCK circuit according to claim 1, characterized in that, It also includes two COT circuits (2) corresponding to the two BUCK circuits (4). The BUCK circuit (4) is turned on by a turn-on signal and the BUCK circuit (4) is turned off by a turn-off signal output by the corresponding COT circuit (2). The COT circuit (2) is used to control the current source to start charging the capacitor when the conduction signal is triggered, compare the voltage of the capacitor with the charging reference voltage, and generate the shutdown signal according to the comparison result.

3. The current-balanced two-phase COT BUCK circuit according to claim 2, characterized in that, The current source is related to the input voltage of the BUCK circuit (4), and the charging reference voltage is related to the output voltage.

4. The current-balanced two-phase COT BUCK circuit according to claim 2, characterized in that, The COT circuit (2) includes a first current mirror, a charging capacitor, a discharge switch, and a first comparator. The current source is connected in series in the control branch of the first current mirror, and the charging capacitor is connected in series in the mirror branch of the first current mirror. The positive terminal of the charging capacitor is connected to the positive input terminal of the first comparator. The positive terminal of the charging capacitor is also grounded through the discharge switch. The control terminal of the discharge switch receives the turn-on signal to rapidly discharge the charging capacitor under the trigger of the turn-on signal. The negative input terminal of the first comparator is connected to the charging reference voltage, and the output terminal of the first comparator outputs the turn-off signal. The positive terminal of the current source in the COT circuit (2) corresponding to the second BUCK circuit (4) is also connected to the voltage-to-current circuit (62) to superimpose the error current.

5. The current-balanced two-phase COT BUCK circuit according to claim 1, characterized in that, The voltage-to-current conversion circuit (62) includes an error amplifier (EA2) and a bias current source (I). PD ), current conversion resistor (R6), second current mirror; The positive input terminal of the error amplifier (EA2) is connected to the error voltage. The second terminal of the current conversion resistor (R6) is grounded. The output terminal of the error amplifier (EA2) is connected to the gate of the control transistor and the mirror transistor of the second current mirror. The drain of the control transistor of the second current mirror, the first terminal of the current conversion resistor (R6), and the negative input terminal of the error amplifier (EA2) are connected together and then connected to the output terminal of the error amplifier (EA2) via a compensation network. The second terminal of the current conversion resistor (R6) is grounded. The source of the control transistor and the source of the mirror transistor of the second current mirror are connected to the power supply. The drain of the mirror transistor of the second current mirror is connected to the bias current source (I). PD The error current is output from the drain of the mirror transistor of the second current mirror when the ground is connected.

6. The current-balanced two-phase COT BUCK circuit according to claim 2, characterized in that, It also includes a dual-phase conduction control circuit (1), whose input terminal is connected to the common junction of the output terminals of two BUCK circuits (4), and whose two output terminals respectively output two conduction signals corresponding to the two BUCK circuits (4); the dual-phase conduction control circuit (1) is used to compare the output voltage with the reference voltage, and control the two conduction signals to be triggered in turn according to the comparison result.

7. The current-balanced two-phase COT BUCK circuit according to claim 6, characterized in that, It also includes two drive circuits (3) corresponding to the two BUCK circuits (4); The two output terminals of the dual-phase conduction control circuit (1) are connected one-to-one to the first input terminals of the two drive circuits (3), the second input terminal of the drive circuit (3) is connected to the output terminal of the corresponding COT circuit (2), and the output terminal of the drive circuit (3) is connected to the control terminal of the switching transistor of the corresponding BUCK circuit (4); the drive circuit (3) is used to output a drive signal for controlling the switching transistor of the BUCK circuit (4) according to the conduction signal and the shutdown signal.

8. A current balancing method based on the current balancing two-phase COT BUCK circuit according to any one of claims 1-7, characterized in that, The method includes: Simultaneously sample the voltage measurement points of the two BUCK circuits (4) and compare them. Adjust the conduction time of the second BUCK circuit (4) according to the comparison result so that the duty cycle of the second BUCK circuit (4) tracks the duty cycle of the first BUCK circuit (4).

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