Impedance calibration circuit and impedance calibration method for multi-channel 1T1R resistor networks

Abstract

The present invention relates to the field of integrated circuit technology and provides an impedance calibration circuit for a multi-channel 1T1R resistor network and an impedance calibration method thereof. The impedance calibration circuit for a multi-channel 1T1R resistor network includes a positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module, and a DCI adjustment module. The circuit is characterized in that each of the positive impedance calibration module, the negative impedance calibration module, and the user impedance calibration module comprises a multi-channel RRAM network structure; the RRAM network structure comprises multiple branch RRAM structures; and the branch RRAM structure comprises multiple improved RRAM cells, wherein the improved RRAM cell comprises a transistor and an RRAM cell connected in series. The present invention can reduce the complexity of the resistance distribution in the impedance calibration circuit and improve the circuit's adaptability to various impedance calibration algorithms.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an impedance calibration circuit for a multi-channel 1T1R resistor network and an impedance calibration method thereof. Background Art

[0002] Integrated circuits (ICs) are experiencing increasing output transmission rates and data throughput. IO interface circuits serve as a bridge for data exchange between FPGA chips and peripheral circuits. Their circuit performance and signal quality are crucial for these chips. During high-speed signal transmission, impedance matching is employed at the output or receiving end to minimize reflections in different transmission media, ensuring distortion-free signal transmission to the load.

[0003] Currently, digitally controlled impedance matching (DCI) is commonly used in related technical fields to adjust IO impedance by selectively turning on or off transistors within the IO to match the impedance of an external reference resistor. The resistor network in DCI is typically implemented with a resistor width-to-length ratio or a number of resistors connected in parallel with a ratio of 1, 2, 4, ..., 2n-1, or 2n. This resistor network occupies a large area within an integrated circuit and has a highly complex resistor distribution, making it difficult to modify the circuit structure to accommodate various matching algorithms. Summary of the Invention

[0004] The present invention provides an impedance calibration circuit for a multi-channel 1T1R resistor network, the main purpose of which is to reduce the complexity of resistance distribution in the impedance calibration circuit and improve the adaptability of the circuit to various impedance calibration algorithms.

[0005] To achieve the above objectives, the present invention provides an impedance calibration circuit for a multi-channel 1T1R resistor network, comprising a positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module, and a DCI adjustment module, characterized in that the positive impedance calibration module, the negative impedance calibration module, and the user impedance calibration module all comprise a multi-channel RRAM network structure;

[0006] The RRAM network structure comprises a plurality of branch RRAM structures;

[0007] The branch RRAM structure is composed of a plurality of improved RRAM cells, wherein the improved RRAM cell is composed of a transistor and an RRAM cell connected in series.

[0008] In addition, the DCI adjustment module includes a preset rule and a preset calibration algorithm.

[0009] In addition, the RRAM network structure includes:

[0010] Using the preset rule, adjusting the resistance value of each branch RRAM structure in the RRAM network structure;

[0011] According to the preset calibration algorithm, an update rule of each of the RRAM network structures is configured, wherein the update rule represents a switching rule of each transistor of each branch RRAM structure in each RRAM network structure.

[0012] In addition, the positive electrode impedance calibration module includes:

[0013] The positive impedance calibration module consists of a default voltage source, a ground line, a reference potential interface, a transistor, a multi-channel RRAM network structure, a PAD connector, a post-stage comparator, and a precise matching resistor connection;

[0014] The RRAM network structure of each path is pulled up and connected to the default voltage source, and the other end of the RRAM network structure is connected to the PAD connector;

[0015] One end of the precise matching resistor is connected to the ground wire, and the other end of the precise matching resistor is connected to the PAD connector;

[0016] The first input interface of the post-stage comparator is connected to the PAD connector, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the post-stage comparator is connected to the DCI adjustment module;

[0017] The transistors are distributed at both ends of the RRAM network structure and are used to control the on / off state of the RRAM network structure in the positive electrode impedance calibration module;

[0018] The positive electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a positive electrode impedance adjustment signal, wherein the positive electrode impedance adjustment signal is the switching state of each transistor in the multi-channel RRAM network structure.

[0019] In addition, the negative electrode impedance calibration module includes:

[0020] The negative electrode impedance calibration module is composed of the default voltage source, the ground line, the reference potential interface, the PAD connector, a second transistor, a multi-channel second RRAM network structure, a second post-stage comparator and a second precise matching resistor;

[0021] The second RRAM network structure of each path is pulled down and connected to the ground line, and the other end of the RRAM network structure is connected to the PAD connector;

[0022] One end of the second precise matching resistor is connected to the default voltage source, and the other end of the second precise matching resistor is connected to the PAD connector;

[0023] The first input interface of the second post-stage comparator is connected to the PAD connector, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the second post-stage comparator is connected to the DCI adjustment module;

[0024] The second transistors are distributed to both ends of the second RRAM network structure and are used to control the on / off state of the second RRAM network structure in the negative electrode impedance calibration module;

[0025] The negative electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a negative electrode impedance adjustment signal, wherein the negative electrode impedance adjustment signal is the switching state of each second transistor in the multi-channel second RRAM network structure.

[0026] In addition, the DCI adjustment module includes:

[0027] The DCI adjustment module is configured to determine whether the positive impedance calibration module needs to perform an adjustment operation on the resistance connection state according to the output result of the post-stage comparator;

[0028] The DCI adjustment module is further configured to determine, based on an output result of the second post-stage comparator, whether the negative electrode impedance calibration module needs to perform an adjustment operation on the resistance connection state.

[0029] In addition, the user impedance calibration module includes:

[0030] Each route in the user impedance calibration module is obtained by sequentially connecting the default voltage source, the transistor, the RRAM network structure, the transistor, the second transistor, the second RRAM network structure, the second transistor, and the ground line;

[0031] The user impedance calibration module is configured to obtain a positive impedance adjustment signal from the positive impedance calibration module and a negative impedance adjustment signal from the negative impedance calibration module when the DCI adjustment module determines that neither the positive impedance calibration module nor the negative impedance calibration module needs to perform an adjustment operation on the resistance connection state;

[0032] According to the positive impedance adjustment signal and the negative impedance adjustment signal, an assignment operation based on a resistor connection state is performed on a circuit network obtained by connecting the RRAM network structure and the second RRAM network structure in parallel to obtain a matching external resistance value.

[0033] In addition, the preset rule is binary arrangement, and the preset calibration algorithm is dichotomy.

[0034] To achieve the above object, the present invention further provides an impedance calibration method for a multi-channel 1T1R resistor network, characterized in that the method comprises:

[0035] According to a pre-established DCI calibration rule, adjusting the connection state of resistors in the pre-established RRAM network structure to obtain a positive impedance adjustment signal, and adjusting the connection state of resistors in the pre-established second RRAM network structure to obtain a negative impedance adjustment signal, wherein the DCI calibration rule includes a preset calibration algorithm and a preset rule;

[0036] According to the positive impedance adjustment signal and the negative impedance adjustment signal, an assignment operation based on a resistor connection state is performed on a circuit network obtained by connecting the RRAM network structure and the second RRAM network structure in parallel to obtain a matching external resistance value.

[0037] In addition, the method of adjusting the connection state of the resistors in the pre-constructed RRAM network structure according to the pre-constructed DCI calibration rule to obtain a positive impedance adjustment signal, and adjusting the connection state of the resistors in the pre-constructed second RRAM network structure to obtain a negative impedance adjustment signal, includes:

[0038] Using a preset rule in a pre-built DCI calibration rule, the resistance value of each branch RRAM structure in the RRAM network structure in the positive electrode impedance calibration module is adjusted to obtain an initialized positive electrode impedance adjustment signal;

[0039] According to a preset calibration algorithm in a pre-built DCI calibration rule, an update rule of the RRAM network structure is configured to obtain a positive electrode update rule;

[0040] Iteratively updating the initialized positive electrode impedance adjustment signal according to the positive electrode update rule to obtain a positive electrode impedance adjustment signal;

[0041] Using a preset rule in the DCI calibration rule, adjusting the resistance value of each branch RRAM structure in the RRAM network structure in the negative electrode impedance calibration module to obtain an initialization negative electrode impedance adjustment signal;

[0042] According to the preset calibration algorithm in the DCI calibration rule, an update rule of the RRAM network structure in the negative electrode impedance calibration module is configured to obtain a negative electrode update rule, wherein the positive electrode update rule and the negative electrode update rule both represent the switching rule of each transistor of each branch RRAM structure;

[0043] According to the negative electrode update rule, the initialized negative electrode impedance adjustment signal is iteratively updated to obtain a negative electrode impedance adjustment signal.

[0044] To address the problems described in the background art, the present invention proposes replacing the parallel resistor structure in a conventional impedance calibration circuit with an RRAM network structure. The RRAM network structure comprises multiple branch RRAM structures. By configuring the transistor switching states within the branches, different branch RRAM structures can have different resistance values. Furthermore, the transistor switching states between the branches can be configured using different update algorithms, such as a binary algorithm, to better coordinate the accessibility of the RRAM structures in each branch. This allows the impedance calibration circuit to flexibly update resistance using different algorithms. Furthermore, replacing the conventional parallel resistor structure with an RRAM network structure can also optimize the area occupied by the resistance adjustment portion of the integrated circuit. Therefore, the present invention can reduce the complexity of the resistance distribution in the impedance calibration circuit and improve the circuit's adaptability to various impedance calibration algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of the structure of an RRAM network in an impedance calibration circuit of a multi-channel 1T1R resistor network provided by an embodiment of the present invention;

[0046] Figure 2A A schematic diagram of the structure of impedance calibration of a multi-channel 1T1R resistor network with a P-side reference IO in an impedance calibration circuit of a multi-channel 1T1R resistor network provided by an embodiment of the present invention;

[0047] Figure 2B A schematic diagram of the structure of impedance calibration of a multi-channel 1T1R resistor network with reference to IO on the N side in an impedance calibration circuit of a multi-channel 1T1R resistor network provided by an embodiment of the present invention;

[0048] Figure 2C A schematic diagram of the structure of impedance calibration of a multi-channel 1T1R resistor network with a user-side reference IO in an impedance calibration circuit of a multi-channel 1T1R resistor network provided by an embodiment of the present invention;

[0049] Figure 3A This is a waveform diagram of a bisection matching algorithm for a multi-channel 1T1R impedance matching network with an N-side reference IO in an impedance calibration circuit for a multi-channel 1T1R resistor network provided by an embodiment of the present invention;

[0050] Figure 3B This is a waveform diagram of a bisection matching algorithm for a multi-channel 1T1R impedance matching network with a P-side reference IO in an impedance calibration circuit for a multi-channel 1T1R resistor network provided by an embodiment of the present invention;

[0051] Figure 4 A schematic flow chart of an impedance calibration method for a multi-channel 1T1R resistor network provided by an embodiment of the present invention.

[0052] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of this application more apparent, the following exemplary embodiments of this application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this application, rather than all the embodiments of this application, and it should be understood that this application is not limited to the exemplary embodiments described herein.

[0054] In this article, 1T1R refers to a series structure of one transistor and one RRAM cell.

[0055] An embodiment of the present application relates to an impedance calibration circuit for a multi-channel 1T1R resistor network, mainly comprising a positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module, and a DCI adjustment module, wherein the positive impedance calibration module, the negative impedance calibration module, and the user impedance calibration module each comprise a multi-channel RRAM network structure;

[0056] The RRAM network structure comprises a plurality of branch RRAM structures;

[0057] The branch RRAM structure is composed of a plurality of improved RRAM cells, wherein the improved RRAM cell is composed of a transistor and an RRAM cell connected in series.

[0058] RRAM is a new type of non-volatile memory. A more mature structure is the metal / semiconductor / metal MIM structure, which features a simple structure, low write voltage, and fast read and write speeds. Its greatest advantage is its ability to store multiple resistance states and maintain these states for extended periods.

[0059] Therefore, the RRAM network structure can be used as a dynamically adjustable resistor.

[0060] The DCI adjustment module refers to a functional block in the FPGA that adjusts the impedance to match the external reference resistor.

[0061] The FPGA is a programmable integrated circuit whose internal logic structure and connection relationship can be configured through programming according to user needs to realize various digital functions.

[0062] Since the matching resistor network in the existing technology is generally constructed using multiple parallel resistors or resistors with different width-to-length ratios, for example, the resistors are distributed according to the width-to-length ratios of 2nR, 2n-1R, ..., 4R, 2R, R or the parallel resistors are distributed as 1, 2, 4, ..., 2n-1, 2n. This type of resistor network is not only used in large numbers in integrated circuits and occupies a large area, but also this binary resistor network will limit the algorithm and is not flexible enough.

[0063] Therefore, the present invention replaces the matching resistor network with an RRAM network structure.

[0064] In detail, in an embodiment of the present invention, the RRAM network structure includes:

[0065] Using the preset rule, adjusting the resistance value of each branch RRAM structure in the RRAM network structure;

[0066] According to the preset calibration algorithm, an update rule of the RRAM network structure is configured, wherein the update rule represents a switching rule of each transistor of each branch RRAM structure.

[0067] In detail, in the embodiment of the present invention, the DCI adjustment module includes a preset rule and a preset calibration algorithm.

[0068] Specifically, in embodiments of the present invention, the resistance of the matching resistor network is generally distributed according to a resistor width-to-length ratio of 2nR, 2n-1R, ..., 4R, 2R, R, or a parallel resistance of 1, 2, 4, ..., 2^n-1, 2^n. However, the present invention allows adjustment based on a preset rule, for example, to 1, 4, 16, 64, ..., 4^n-1, 4^n. Modification can be achieved by configuring the preset rule, thereby increasing the flexibility of the resistance distribution.

[0069] Furthermore, by controlling the switching of the multi-channel RRAM network structure by transistors, it is possible to not only update the resistance using the binary method during the calibration process, but also use other algorithms to update the resistance.

[0070] Specifically, such as Figure 1As shown, the left side is a pull-up network (RRAM_PU) of an RRAM network structure, and the right side is a pull-down network (RRAM_PD) of an RRAM network structure. This multi-branch 1T1R array combined in series and parallel can not only achieve precise resistance control, but also avoid read disturbance and ensure process consistency. The multi-branch 1T1RRAM resistor network structure can include (n+1)*(m+1) RRAMs, and the values ​​of n and m can be selected according to actual needs. The RRAM adjustment process is to circulate to BL in turn. <0> and BLN <0> Between, BL <1> and BLN <1> Between, BL <2> and BLN <2> Between, BL <n>and BLN <n>The RRAM write signals between them (the updated columns can be controlled by WL) until the multiple branch RRAM structures meet the matching requirements.

[0071] refer to Figure 2A 、 Figure 2B and Figure 2C It can be seen that the impedance calibration circuit of the present invention has a multi-channel structure.

[0072] Among them, VRP represents the P-side reference IO, VCCO represents the default voltage source, PMOS represents the transistor, RRAM-PU represents the pull-up RRAM network structure, Rref represents the precise matching resistor, PAD represents the PAD voltage on the PAD connector, and DCI_COMP represents the post-stage comparator.

[0073] Among them, RRAM-PD represents the second pull-down RRAM network structure, VRN represents the N-side reference IO, and NMOS represents the second transistor on the N side. The difference from VRP is that the second RRAM resistor network structure is connected to the ground line.

[0074] In detail, in an embodiment of the present invention, the positive electrode impedance calibration module includes:

[0075] The positive impedance calibration module consists of a default voltage source, a ground line, a reference potential interface, a transistor, a multi-channel RRAM network structure, a PAD connector, a post-stage comparator, and a precise matching resistor connection;

[0076] The RRAM network structure of each path is pulled up and connected to the default voltage source, and the other end of the RRAM network structure is connected to the PAD connector;

[0077] One end of the precise matching resistor is connected to the ground wire, and the other end of the precise matching resistor is connected to the PAD connector;

[0078] The first input interface of the post-stage comparator is connected to the PAD connector, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the post-stage comparator is connected to the DCI adjustment module;

[0079] The transistors are distributed at both ends of the RRAM network structure and are used to control the on / off state of the RRAM network structure in the positive electrode impedance calibration module;

[0080] The positive electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a positive electrode impedance adjustment signal, wherein the positive electrode impedance adjustment signal is the switching state of each transistor in the multi-channel RRAM network structure.

[0081] The precise matching resistor is used to provide a component with a fixed or adjustable precise resistance value.

[0082] The transistor is a component used to control the on and off of current in electronic circuits. By changing the input signal, the transistor can switch between the "on" (equivalent to a closed switch) and "off" (equivalent to an open switch) states.

[0083] The post-stage comparator refers to a component that receives a signal processed by a pre-stage circuit (such as a PAD voltage), compares the signal with a reference value or other input signal (such as a reference voltage VREF), and then outputs a high level or a low level (digital logic, 0 or 1) as a result.

[0084] Among them, the PAD connector refers to the input / output pin interface module on the FPGA chip, which is a direct interface between external signals and the internal logic of the FPGA. It can be understood that the PAD connector corresponds to the actual I / O pin (or solder ball).

[0085] In detail, in an embodiment of the present invention, the negative electrode impedance calibration module includes:

[0086] The negative electrode impedance calibration module is composed of the default voltage source, the ground line, the reference potential interface, the PAD connector, a second transistor, a multi-channel second RRAM network structure, a second post-stage comparator and a second precise matching resistor;

[0087] The second RRAM network structure of each path is pulled down and connected to the ground line, and the other end of the RRAM network structure is connected to the PAD connector;

[0088] One end of the second precise matching resistor is connected to the default voltage source, and the other end of the second precise matching resistor is connected to the PAD connector;

[0089] The first input interface of the second post-stage comparator is connected to the PAD connector, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the second post-stage comparator is connected to the DCI adjustment module;

[0090] The second transistors are distributed to both ends of the second RRAM network structure and are used to control the on / off state of the second RRAM network structure in the negative electrode impedance calibration module;

[0091] The negative electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a negative electrode impedance adjustment signal, wherein the negative electrode impedance adjustment signal is the switching state of each second transistor in the multi-channel second RRAM network structure.

[0092] In detail, in an embodiment of the present invention, the DCI adjustment module includes:

[0093] The DCI adjustment module is configured to determine whether the positive impedance calibration module needs to perform an adjustment operation on the resistance connection state according to the output result of the post-stage comparator;

[0094] The DCI adjustment module is further configured to determine, based on an output result of the second post-stage comparator, whether the negative electrode impedance calibration module needs to perform an adjustment operation on the resistance connection state.

[0095] In detail, in an embodiment of the present invention, the user impedance calibration module includes:

[0096] Each route in the user impedance calibration module is obtained by sequentially connecting the default voltage source, the transistor, the RRAM network structure, the transistor, the second transistor, the second RRAM network structure, the second transistor, and the ground line;

[0097] The user impedance calibration module is configured to obtain a positive impedance adjustment signal from the positive impedance calibration module and a negative impedance adjustment signal from the negative impedance calibration module when the DCI adjustment module determines that neither the positive impedance calibration module nor the negative impedance calibration module needs to perform an adjustment operation on the resistance connection state;

[0098] According to the positive impedance adjustment signal and the negative impedance adjustment signal, an assignment operation based on a resistor connection state is performed on a circuit network obtained by connecting the RRAM network structure and the second RRAM network structure in parallel to obtain a matching external resistance value.

[0099] Specifically, in the embodiment of the present invention, the functions of the positive impedance calibration module, the negative impedance calibration module, the user impedance calibration module and the DCI adjustment module in the impedance calibration circuit are the same as those in the traditional impedance calibration circuit and are not described in detail here.

[0100] However, in the embodiments of the present invention, the technical means of implementation are different. By designing a multi-channel RRAM network structure to replace the traditional parallel resistor network, a smaller footprint in the integrated circuit and a more flexible configuration method of the resistance distribution law and the resistance calibration algorithm are achieved.

[0101] In detail, in the embodiment of the present invention, the preset rule is a binary arrangement, and the preset calibration algorithm is a dichotomy method.

[0102] refer to Figure 3A and 3B In the embodiments of the present invention, experiments were conducted on the impedance calibration circuit of the multi-channel 1T1R resistor network using the preset rules of traditional binary arrangement and the dichotomy calibration algorithm. The results showed that by combining high and low level digital signals with RRAM, the traditional impedance calibration circuit can be directly replaced with a smaller circuit footprint.

[0103] Specifically, in the embodiment of the present invention, the resistance adjustment of the multi-channel 1T1R resistor network is expressed as:

[0104] Step 1: Take n=6 as an example, you can Figure 2B During the calibration process, an external 64ohm reference resistor (this value is for example only and has no limiting effect) is used, VREF=1 / 2*VCCO; NMOS is turned off. <6> , to RRAM_PD <6> Tube input regulation signal; turn on NMOS <6> , compare the PAD voltage with VREF in the comparator DCI_COMP; <6> Adjust the resistance to 64ohm and record the input RRAM_PD at this time <6> Then Figure 2C Turn off NMOS <6> ,Will Figure 2B Input RRAM_PD recorded in <6> The regulation signal of the tube is input to Figure 2C RRAM_PD in <6> tube, realizing RRAM PD <6> Resistance adjustment;

[0105] Step 2: Follow step 1 above and update RRAM_PD<5:0> one by one. Adjust the resistance value of RRAM_PD<5:0> to 32ohm, 16ohm, 8ohm, 4ohm, 2ohm, and 1ohm respectively. Record the resistance value. Figure 2B The corresponding input RRAM_PD<5:0> tube adjustment signal, in Figure 2C The corresponding NMOS<5:0> tube is turned off, and the corresponding adjustment signal is input into the RRAM_PD<5:0> of USERIO to adjust the resistance value of each RRAM_PD<5:0>.

[0106] Step 3: Figure 2A Follow steps 1-2 above to gradually turn off the PMOS<6:0> transistors and adjust the resistance values ​​of RRAM_PU<6:0> to 64ohm, 32ohm, 16ohm, 8ohm, 4ohm, 2ohm, and 1ohm respectively. Record the resistance values. Figure 2B The corresponding input RRAM_PU<6:0> tube adjustment signal, in Figure 2C In the example, RRAM_PU<6:0> is updated in sequence, and the corresponding adjustment signal is input into RRAM_PU<6:0> of USERIO to adjust the resistance value of each RRAM_PU<6:0>.

[0107] After the resistance adjustment of each RRAM channel is completed, the resistance value is determined, and the NMOS<6:0> and PMOS<6:0> switches can be used for impedance matching.

[0108] Specifically, in the embodiment of the present invention, the impedance matching process of the multi-channel RRAM network structure is expressed as:

[0109] This embodiment proposes a fast impedance calibration algorithm: a binary method, which uses the binary RRAM network structure to perform impedance matching.

[0110] Figure 3A The following waveforms show the binary matching algorithm for the multi-channel 1T1R impedance matching network of the N-side reference IO. Matching starts with all NMOS<6:0> transistors turned off. The PAD voltage is detected by the comparator. VREF is set to 240mV (this value is only an experimental example and has no limiting effect):

[0111] The first clock PAD voltage is equal to VCCO, and the DCI comparison result is 1, so it is fed back to the resistor network NMOS. <6> =1;

[0112] The next clock PAD voltage is equal to 630mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS. <5> =1;

[0113] The next clock PAD voltage is equal to 310mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS. <4> =1;

[0114] The next clock PAD voltage is equal to 150mV, and the DCI comparison result is still 0, so it is fed back to the resistor network NMOS. <3> =0;

[0115] The next clock PAD voltage is equal to 230mV, and the DCI comparison result is still 0, so it is fed back to the resistor network NMOS. <2> =0;

[0116] The next clock PAD voltage is equal to 270mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS. <1> =1;

[0117] The next clock PAD voltage is equal to 250mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS. <0> =1;

[0118] The next clock PAD voltage is equal to 240mV, and the matching is completed at this time.

[0119] The impedance can be accurately calibrated using the binary method in just 7 clocks. In this embodiment, the 7 DCI comparison results are 1110011 respectively, and the results are fed back to the N-side NMOS<6:0> of USERIO.

[0120] Figure 3B The following waveforms show the binary matching algorithm for the multi-channel 1T1R impedance matching network with reference IO on the P side. Matching starts with all PMOS<6:0> turned off, the PAD voltage is detected by the comparator, and VREF is set to 1090mV (this value is only an experimental example and has no limiting effect):

[0121] The first clock PAD voltage is equal to GND, and the DCI comparison result is 0, so it is fed back to the resistor network PMOS. <6> =0;

[0122] The next clock PAD voltage is equal to 640mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS. <5> =0;

[0123] The next clock PAD voltage is equal to 960mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS. <4> =0;

[0124] The next clock PAD voltage is equal to 1120mV, and the DCI comparison result is still 1, so it is fed back to the resistor network PMOS. <3> =1;

[0125] The next clock PAD voltage is equal to 1040mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS. <2> =0;

[0126] The next clock PAD voltage is equal to 1080mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS. <1> =0;

[0127] The next clock PAD voltage is equal to 1100mV, and the DCI comparison result is still 1, so it is fed back to the resistor network PMOS <0> =1;

[0128] The next clock PAD voltage is equal to 1090mV, and the matching is completed at this time.

[0129] The impedance can be accurately calibrated using the binary method in just 7 clocks. In this embodiment, the 7 DCI comparison results are 0001001 respectively, and the results are fed back to the P-side PMOS<6:0> of USERIO.

[0130] In completion Figure 3A and Figure 3B After the steps, the resistance values ​​of all RRAMs in USERIO have been adjusted, and the on and off states of the switches corresponding to each RRAM are also configured through the N-side NMOS<6:0> transistor and the P-side PMOS<6:0> transistor. At this time, the circuit completes impedance calibration.

[0131] To address the problems described in the background art, the present invention proposes replacing the parallel resistor structure in a conventional impedance calibration circuit with an RRAM network structure. The RRAM network structure comprises multiple branch RRAM structures. By configuring the transistor switching states within the branches, different branch RRAM structures can have different resistance values. Furthermore, the transistor switching states between the branches can be configured using different update algorithms, such as a binary algorithm, to better coordinate the accessibility of the RRAM structures in each branch. This allows the impedance calibration circuit to flexibly update resistance using different algorithms. Furthermore, replacing the conventional parallel resistor structure with an RRAM network structure can also optimize the area occupied by the resistance adjustment portion of the integrated circuit. Therefore, the present invention can reduce the complexity of the resistance distribution in the impedance calibration circuit and improve the circuit's adaptability to various impedance calibration algorithms.

[0132] Further, see Figure 4 As shown, the embodiment of the present invention also provides a method for utilizing Figure 1 The control method performed by the impedance calibration circuit of the multi-channel 1T1R resistor network includes:

[0133] S1. According to a pre-established DCI calibration rule, adjusting the connection state of resistors in a pre-established RRAM network structure to obtain a positive impedance adjustment signal, and adjusting the connection state of resistors in a pre-established second RRAM network structure to obtain a negative impedance adjustment signal, wherein the DCI calibration rule includes a preset calibration algorithm and a preset rule;

[0134] S2. According to the positive impedance adjustment signal and the negative impedance adjustment signal, an assignment operation based on a resistor connection state is performed on a circuit network obtained by connecting the RRAM network structure and the second RRAM network structure in parallel to obtain a matching external resistance value.

[0135] The DCI adjustment module refers to a functional block in the FPGA that adjusts the impedance to match the external reference resistor.

[0136] The FPGA is a programmable integrated circuit whose internal logic structure and connection relationship can be configured through programming according to user needs to realize various digital functions.

[0137] RRAM is a new type of non-volatile memory. A more mature structure is the metal / semiconductor / metal MIM structure, which features a simple structure, low write voltage, and fast read and write speeds. Its greatest advantage is its ability to store multiple resistance states and maintain these states for extended periods.

[0138] Therefore, the RRAM network structure can be used as a dynamically adjustable resistor.

[0139] The DCI calibration rules include a preset calibration algorithm and a preset rule.

[0140] Specifically, in embodiments of the present invention, the resistance of the matching resistor network is generally distributed according to a resistor width-to-length ratio of 2nR, 2n-1R, ..., 4R, 2R, R, or a parallel resistance of 1, 2, 4, ..., 2^n-1, 2^n. However, the present invention allows adjustment based on a preset rule, for example, to 1, 4, 16, 64, ..., 4^n-1, 4^n. Modification can be achieved by configuring the preset rule, thereby increasing the flexibility of the resistance distribution.

[0141] Furthermore, by controlling the switching of the multi-channel RRAM network structure by transistors, it is possible to not only update the resistance using the binary method during the calibration process, but also use other algorithms to update the resistance.

[0142] In detail, in an embodiment of the present invention, adjusting the connection state of the resistors in the pre-constructed RRAM network structure according to the pre-constructed DCI calibration rule to obtain a positive impedance adjustment signal, and adjusting the connection state of the resistors in the pre-constructed second RRAM network structure to obtain a negative impedance adjustment signal, include:

[0143] Using a preset rule in a pre-built DCI calibration rule, the resistance value of each branch RRAM structure in the RRAM network structure in the positive electrode impedance calibration module is adjusted to obtain an initialized positive electrode impedance adjustment signal;

[0144] According to a preset calibration algorithm in a pre-built DCI calibration rule, an update rule of the RRAM network structure is configured to obtain a positive electrode update rule;

[0145] Iteratively updating the initialized positive electrode impedance adjustment signal according to the positive electrode update rule to obtain a positive electrode impedance adjustment signal;

[0146] Using a preset rule in the DCI calibration rule, adjusting the resistance value of each branch RRAM structure in the RRAM network structure in the negative electrode impedance calibration module to obtain an initialization negative electrode impedance adjustment signal;

[0147] According to the preset calibration algorithm in the DCI calibration rule, an update rule of the RRAM network structure in the negative electrode impedance calibration module is configured to obtain a negative electrode update rule, wherein the positive electrode update rule and the negative electrode update rule both represent the switching rule of each transistor of each branch RRAM structure;

[0148] According to the negative electrode update rule, the initialized negative electrode impedance adjustment signal is iteratively updated to obtain a negative electrode impedance adjustment signal.

[0149] Specifically, in the embodiment of the present invention, the step of adjusting the resistor connection state in the pre-constructed RRAM network structure according to the pre-constructed DCI calibration rule to obtain the positive impedance adjustment signal includes two parts: resistance adjustment and impedance matching.

[0150] Specifically, in the embodiment of the present invention, the resistance adjustment of the multi-channel 1T1R resistor network is expressed as:

[0151] Step 1: Take n=6 as an example, you can Figure 2B During the calibration process, an external 64ohm reference resistor (this value is for example only and has no limiting effect) is used, VREF=1 / 2*VCCO; NMOS is turned off. <6> , to RRAM_PD <6> Tube input regulation signal; turn on NMOS <6> , compare the PAD voltage with VREF in the comparator DCI_COMP; <6> Adjust the resistance to 64ohm and record the input RRAM_PD at this time <6> Then Figure 2C Turn off NMOS <6> ,Will Figure 2B Input RRAM_PD recorded in <6> The regulation signal of the tube is input to Figure 2C RRAM_PD in <6> tube, realizing RRAM PD <6> Resistance adjustment;

[0152] Step 2: Follow step 1 above and update RRAM_PD<5:0> one by one. Adjust the resistance value of RRAM_PD<5:0> to 32ohm, 16ohm, 8ohm, 4ohm, 2ohm, and 1ohm respectively. Record the resistance value. Figure 2B The corresponding input RRAM_PD<5:0> tube adjustment signal, in Figure 2C The corresponding NMOS<5:0> tube is turned off, and the corresponding adjustment signal is input into the RRAM_PD<5:0> of USERIO to adjust the resistance value of each RRAM_PD<5:0>.

[0153] Step 3: Figure 2A Follow steps 1-2 above to gradually turn off the PMOS<6:0> transistors and adjust the resistance values ​​of RRAM_PU<6:0> to 64ohm, 32ohm, 16ohm, 8ohm, 4ohm, 2ohm, and 1ohm respectively. Record the resistance values. Figure 2B The corresponding input RRAM_PU<6:0> tube adjustment signal, in Figure 2C In the example, RRAM_PU<6:0> is updated in sequence, and the corresponding adjustment signal is input into RRAM_PU<6:0> of USERIO to adjust the resistance value of each RRAM_PU<6:0>.

[0154] After the resistance adjustment of each RRAM channel is completed, the resistance value is determined, and the NMOS<6:0> and PMOS<6:0> switches can be used for impedance matching.

[0155] Specifically, in the embodiment of the present invention, the impedance matching process of the multi-channel RRAM network structure is expressed as:

[0156] This embodiment proposes a fast impedance calibration algorithm: a binary method, which uses the binary RRAM network structure to perform impedance matching.

[0157] Figure 3A The following waveforms show the binary matching algorithm for the multi-channel 1T1R impedance matching network of the N-side reference IO. Matching starts with all NMOS<6:0> transistors turned off. The PAD voltage is detected by the comparator. VREF is set to 240mV (this value is only an experimental example and has no limiting effect):

[0158] The first clock PAD voltage is equal to VCCO, and the DCI comparison result is 1, so it is fed back to the resistor network NMOS. <6> =1;

[0159] The next clock PAD voltage is equal to 630mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS. <5> =1;

[0160] The next clock PAD voltage is equal to 310mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS. <4> =1;

[0161] The next clock PAD voltage is equal to 150mV, and the DCI comparison result is still 0, so it is fed back to the resistor network NMOS. <3> =0;

[0162] The next clock PAD voltage is equal to 230mV, and the DCI comparison result is still 0, so it is fed back to the resistor network NMOS. <2> =0;

[0163] The next clock PAD voltage is equal to 270mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS. <1> =1;

[0164] The next clock PAD voltage is equal to 250mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS. <0> =1;

[0165] The next clock PAD voltage is equal to 240mV, and the matching is completed at this time.

[0166] The impedance can be accurately calibrated using the binary method in just 7 clocks. In this embodiment, the 7 DCI comparison results are 1110011 respectively, and the results are fed back to the N-side NMOS<6:0> of USERIO.

[0167] Figure 3B The following waveforms show the binary matching algorithm for the multi-channel 1T1R impedance matching network with reference IO on the P side. Matching starts with all PMOS<6:0> turned off, the PAD voltage is detected by the comparator, and VREF is set to 1090mV (this value is only an experimental example and has no limiting effect):

[0168] The first clock PAD voltage is equal to GND, and the DCI comparison result is 0, so it is fed back to the resistor network PMOS. <6> =0;

[0169] The next clock PAD voltage is equal to 640mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS. <5> =0;

[0170] The next clock PAD voltage is equal to 960mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS. <4> =0;

[0171] The next clock PAD voltage is equal to 1120mV, and the DCI comparison result is still 1, so it is fed back to the resistor network PMOS. <3> =1;

[0172] The next clock PAD voltage is equal to 1040mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS. <2> =0;

[0173] The next clock PAD voltage is equal to 1080mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS. <1> =0;

[0174] The next clock PAD voltage is equal to 1100mV, and the DCI comparison result is still 1, so it is fed back to the resistor network PMOS <0> =1;

[0175] The next clock PAD voltage is equal to 1090mV, and the matching is completed at this time.

[0176] The impedance can be accurately calibrated using the binary method in just 7 clocks. In this embodiment, the 7 DCI comparison results are 0001001 respectively, and the results are fed back to the P-side PMOS<6:0> of USERIO.

[0177] In completion Figure 3A and Figure 3B After the steps, the resistance values ​​of all RRAMs in USERIO have been adjusted, and the on and off states of the switches corresponding to each RRAM are also configured through the N-side NMOS<6:0> transistor and the P-side PMOS<6:0> transistor. At this time, the circuit completes impedance calibration.

[0178] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0179] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention.< / n> < / n>

Claims

1. An impedance calibration circuit for a multi-channel 1T1R resistor network, comprising a positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module, and a DCI adjustment module, wherein: The 1T1R refers to a series structure of one transistor and one RRAM unit, the transistor is used to control the on-off of the current, the positive impedance calibration module and the negative impedance calibration module are respectively connected to the PAD in the DCI adjustment module, wherein the DCI adjustment module includes a PAD, and the user impedance calibration module is respectively connected to the DCI adjustment module, the positive impedance calibration module and the negative impedance calibration module. The user impedance calibration module is used to obtain the positive impedance adjustment signal of the positive impedance calibration module and the negative impedance adjustment signal of the negative impedance calibration module when the DCI adjustment module determines that the positive impedance calibration module and the negative impedance calibration module do not need to adjust the resistance connection state. It is characterized in that the positive impedance calibration module and the negative impedance calibration module both include a multi-channel RRAM network structure, wherein the RRAM network structure is used as a dynamically adjustable resistor; The RRAM network structure comprises a plurality of branch RRAM structures, wherein the branch RRAM structures are distributed in a matrix-like relationship, wherein the matrix-like distribution relationship means that the RRAM network structure includes a plurality of parallel word lines WL and a plurality of BL bit line groups perpendicular to the word lines WL, wherein the BL bit line groups are composed of parallel BL bit lines and BLN bit lines, and a line segment is formed between each BL bit line group and each word line WL, and each line segment is connected to an improved RRAM unit, wherein two ends of the improved RRAM unit are respectively connected to the BL bit line and the BLN bit line to form a parallel connection with the line segment, and the gate of the transistor in the improved RRAM unit is connected to the line segment; The branch RRAM structure is composed of a plurality of improved RRAM cells, wherein the improved RRAM cell is composed of a transistor and an RRAM cell connected in series; Each RRAM network structure in the positive impedance calibration module includes two PMOSs and one RRAM network structure, forming a series structure of PMOS-RRAM network structure-PMOS. The current direction is VCCO, PMOS, RRAM network structure, PMOS and PAD in the DCI adjustment module in sequence. VCCO is outside the RRAM network structure in the positive impedance calibration module. The positive impedance calibration module is used to adjust the resistance connection state in the RRAM network structure to obtain a positive impedance adjustment signal. Wherein, each RRAM network structure in the negative electrode impedance calibration module includes two NMOSs and one RRAM network structure, forming a series structure of NMOS-RRAM network structure-NMOS, and the current direction is PAD, NMOS, RRAM network structure, NMOS and ground in sequence, wherein the ground is outside the RRAM network structure in the negative electrode impedance calibration module, and the negative electrode impedance calibration module is used to adjust the resistance connection state in the RRAM network structure to obtain a negative electrode impedance adjustment signal; The DCI adjustment module is used to determine whether the positive electrode impedance calibration module and the negative electrode impedance calibration module need to perform an adjustment operation on the resistance connection state.

2. The impedance calibration circuit of a multi-channel 1T1R resistor network according to claim 1, wherein: The positive electrode impedance calibration module includes: The positive impedance calibration module is composed of a default voltage source, a ground line, a reference potential interface, a transistor, a multi-channel RRAM network structure, a PAD, a post-stage comparator, and a precisely matched resistor connection, wherein the default voltage source is used to generate VCCO, and the ground line is used for grounding; One PMOS in each RRAM network structure is connected to the default voltage source, and the other PMOS at the other end of the RRAM network structure is connected to the PAD; One end of the precise matching resistor is connected to the ground line, and the other end of the precise matching resistor is connected to the PAD; The first input interface of the post-stage comparator is connected to the PAD, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the post-stage comparator is connected to the DCI adjustment module; The transistors are distributed at both ends of the RRAM network structure and are used to control the on / off state of the RRAM network structure in the positive electrode impedance calibration module; The positive electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a positive electrode impedance adjustment signal, wherein the positive electrode impedance adjustment signal is the switching state of each transistor in the multi-channel RRAM network structure.

3. The impedance calibration circuit of a multi-channel 1T1R resistor network according to claim 2, wherein: The negative electrode impedance calibration module includes: The negative electrode impedance calibration module is composed of the default voltage source, the ground line, the reference potential interface, the PAD, a second transistor, a multi-channel second RRAM network structure, a second post-stage comparator and a second precise matching resistor connection; One NMOS in each of the second RRAM network structures is connected to the ground line, and the other NMOS at the other end of the RRAM network structure is connected to the PAD; One end of the second precise matching resistor is connected to the default voltage source, and the other end of the second precise matching resistor is connected to the PAD; The first input interface of the second post-stage comparator is connected to the PAD, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the second post-stage comparator is connected to the DCI adjustment module; The second transistors are distributed to both ends of the second RRAM network structure and are used to control the on / off state of the second RRAM network structure in the negative electrode impedance calibration module; The negative electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a negative electrode impedance adjustment signal, wherein the negative electrode impedance adjustment signal is the switching state of each second transistor in the multi-channel second RRAM network structure.

4. The impedance calibration circuit of a multi-channel 1T1R resistor network according to claim 3, wherein: The DCI adjustment module includes: The DCI adjustment module is configured to determine whether the positive impedance calibration module needs to perform an adjustment operation on the resistance connection state according to the output result of the post-stage comparator; The DCI adjustment module is further configured to determine whether the negative electrode impedance calibration module needs to perform an adjustment operation on the resistance connection state according to the output result of the second post-stage comparator.

5. A method for impedance calibration of a multi-channel 1T1R resistor network, for controlling the impedance calibration circuit of the multi-channel 1T1R resistor network according to claim 1, wherein: The 1T1R refers to a series structure of one transistor and one RRAM unit, wherein the method includes: According to a pre-established DCI calibration rule, the connection state of the resistors in the pre-established RRAM network structure is adjusted to obtain a positive impedance adjustment signal, and the connection state of the resistors in the pre-established second RRAM network structure is adjusted to obtain a negative impedance adjustment signal, wherein the DCI calibration rule includes a preset calibration algorithm and a preset rule, wherein the current direction in the RRAM network structure is VCCO, PMOS, RRAM network structure, PMOS, and PAD in the DCI adjustment module in order, and the current direction in the second RRAM network structure is PAD, NMOS, RRAM network structure, NMOS, and ground in order, the preset rule is a binary arrangement, and the preset calibration algorithm is a dichotomy method; According to the positive impedance adjustment signal and the negative impedance adjustment signal, an assignment operation based on a resistor connection state is performed on a circuit network obtained by connecting the RRAM network structure and the second RRAM network structure in parallel to obtain a matching external resistance value.

6. The impedance calibration method for a multi-channel 1T1R resistor network according to claim 5, wherein: The method of adjusting the connection state of resistors in the pre-constructed RRAM network structure according to the pre-constructed DCI calibration rule to obtain a positive impedance adjustment signal, and adjusting the connection state of resistors in the pre-constructed second RRAM network structure to obtain a negative impedance adjustment signal, includes: Using a preset rule in a pre-built DCI calibration rule, the resistance value of each branch RRAM structure in the RRAM network structure in the positive electrode impedance calibration module is adjusted to obtain an initialized positive electrode impedance adjustment signal; According to a preset calibration algorithm in a pre-built DCI calibration rule, an update rule of the RRAM network structure is configured to obtain a positive electrode update rule; Iteratively updating the initialized positive electrode impedance adjustment signal according to the positive electrode update rule to obtain a positive electrode impedance adjustment signal; Using a preset rule in the DCI calibration rule, adjusting the resistance value of each branch RRAM structure in the RRAM network structure in the negative electrode impedance calibration module to obtain an initialization negative electrode impedance adjustment signal; According to the preset calibration algorithm in the DCI calibration rule, an update rule of the RRAM network structure in the negative electrode impedance calibration module is configured to obtain a negative electrode update rule, wherein the positive electrode update rule and the negative electrode update rule both represent the switching rule of each transistor of each branch RRAM structure; According to the negative electrode update rule, the initialized negative electrode impedance adjustment signal is iteratively updated to obtain a negative electrode impedance adjustment signal.

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