LIN Driver Circuit Integrating Current Limiting and Slope Control

Abstract

The present invention discloses a LIN driving circuit integrating current limiting and slope control, which includes a slope control circuit, a slope monitoring and sampling circuit, a source follower circuit, a driving circuit, a current sampling circuit, and a current limiting control circuit. The slope monitoring and sampling circuit samples the LIN output signal generated by the driving circuit; the slope control circuit generates a slope control signal according to the input signal and the output signal of the slope monitoring and sampling circuit; the slope control signal controls the driving circuit through the source follower circuit, so that the driving circuit generates a LIN output signal with a predetermined slope; the current sampling circuit samples the current flowing through the driving circuit; the current limiting control circuit compares the sampled voltage with the reference voltage, and when the sampled voltage is greater than the reference voltage, the current limiting control circuit turns off the driving circuit, so that the maximum output current of the LIN driving circuit is limited to a predetermined level.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a LIN driver circuit integrating current limiting and slope control. Background Art

[0002] Local Interconnect Network (LIN) is a low-cost, low-speed serial communication network solution, which is widely used in various distributed electronic systems with low requirements for network bandwidth, performance, and fault tolerance functions, such as vehicle-mounted systems, household appliances, etc.

[0003] A LIN node includes a LIN driver circuit for outputting a driving signal, and a load device executes a response based on the driving signal output by the LIN driver circuit. A common fault in the LIN driver circuit is that the internal driving transistor is short-circuited to the high-voltage power supply VS. When the driving ability of the LIN driver circuit is relatively strong, the output current during a short-circuit fault is too large, damaging the LIN driver circuit and seriously affecting other LIN nodes of the entire system. The driving ability of the LIN driver circuit cannot be too weak either, otherwise the output current is too low, which will affect the signal transmission rate and duty cycle of the LIN node, resulting in poor communication quality.

[0004] On the other hand, the slope of the driving signal output by the LIN driver circuit needs to be appropriately controlled. If the slope is too high, the generated EMI will have a greater impact on the EMC characteristics of the entire system; if the slope is too low, the requirements for signal transmission rate and duty cycle cannot be met, thus affecting communication quality.

[0005] In view of these problems, the present invention proposes a LIN driver circuit integrating current limiting and slope control, which has a simple circuit, is easy to implement, and is convenient for low-cost integration. Summary of the Invention

[0006] The present invention proposes a LIN driver circuit integrating current limiting and slope control, which can effectively limit the maximum output current of the LIN driver circuit to a predetermined level while maintaining a relatively strong driving ability of the LIN driver circuit. Even in the event of a short-circuit fault, no excessive output current will be generated. At the same time, the LIN driver circuit of the present invention integrates a slope control circuit, which well solves the problems of electromagnetic interference and poor communication quality in the LIN driver circuit.

[0007] The technical solution of the present invention is as follows:

[0008] The present invention proposes a LIN driver circuit integrating current limiting and slope control, including:

[0009] A slope control circuit, a slope monitoring and sampling circuit, a source follower circuit, a driving circuit, a current sampling circuit, and a current limiting control circuit;

[0010] The slope monitoring and sampling circuit samples the LIN output signal generated by the driving circuit;

[0011] The slope control circuit generates a slope control signal according to the input signal and the output signal of the slope monitoring and sampling circuit;

[0012] The slope control signal controls the driving circuit through the source follower circuit, so that the driving circuit generates a LIN output signal with a predetermined slope;

[0013] The current sampling circuit samples the current flowing through the driving circuit;

[0014] The current limiting control circuit compares the sampled voltage with the reference voltage. When the sampled voltage is greater than the reference voltage, the current limiting control circuit turns off the driving circuit, so that the maximum output current of the driving circuit is limited to a predetermined level.

[0015] It also includes a buffer circuit for buffering the input signal to match the voltage domain of the input signal and the LIN driving circuit.

[0016] The slope control circuit includes a first current source, a second current source, a first transistor, and a second transistor. The first current source, the first transistor, the second transistor, and the second current source are connected in series in sequence.

[0017] The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

[0018] The slope monitoring and sampling circuit includes a sampling capacitor. One end of the sampling capacitor is connected to the output end of the LIN driving circuit, and the other end is connected to the connection point of the first transistor and the second transistor.

[0019] The source follower circuit includes a third transistor and a third current source connected in series. The slope control signal is input to the gate of the third transistor to generate a driving signal.

[0020] The driving circuit includes a zener diode and a fourth transistor connected in series. The driving signal is input to the gate of the fourth transistor to drive the fourth transistor to generate a LIN output signal.

[0021] The third transistor and the fourth transistor are NMOS transistors.

[0022] The current sampling circuit includes a sampling resistor, and the fourth transistor is grounded through the sampling resistor.

[0023] The current-limiting control circuit includes an operational amplifier and a fifth transistor. The sampled voltage is input to the first input terminal of the operational amplifier, the reference voltage is input to the second input terminal of the operational amplifier, the output terminal of the operational amplifier is connected to the gate of the fifth transistor, the input terminal of the fifth transistor is connected to the gate of the fourth transistor, and the output terminal of the fifth transistor is grounded.

[0024] The operational amplifier compares the sampled voltage with the reference voltage. When the sampled voltage is greater than the reference voltage, the operational amplifier controls the fourth transistor to turn off through the fifth transistor.

[0025] In the present invention, a current-limiting circuit including a current-limiting feedback loop is provided in the LIN driving circuit, making the current-limiting value more accurate and ensuring that the driving signal output by the LIN driving circuit is more reliable and stable. The present invention integrates the current-limiting circuit and the slope control circuit in the LIN driving circuit, which can not only achieve current limiting and slope control, but also has a simple circuit, is easy to implement, and is convenient for low-cost integration.

[0026] The features and advantages of the present invention will become clear by referring to the following drawings and the detailed description of the specific embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shows a schematic diagram of the LIN driving circuit of the present invention.

[0028] Figure 2 Shows a circuit diagram of the LIN driving circuit of the present invention.

[0029] Figure 3 Shows a waveform schematic diagram of the key node voltage signal of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] In order to make the technical solution of the present invention clearer and more understandable, the following will be further described in detail with reference to the drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0031] Figure 1 Shows a schematic diagram of the LIN driving circuit of the present invention.

[0032] The LIN driving circuit includes a buffer circuit, a slope control circuit, a slope monitoring and sampling circuit, a source follower circuit, a driving circuit, a current sampling circuit, a current-limiting control circuit, and a pull-up circuit. The current sampling circuit and the current-limiting control circuit constitute the current-limiting circuit of the present invention.

[0033] TXD is the input signal of the LIN driver circuit. After passing through the buffer circuit, it serves as one of the input signals of the slope control circuit. The slope monitoring and sampling circuit samples the LIN output signal and serves as the other input signal of the slope control circuit. The slope control circuit generates a slope control signal based on the buffered input signal and the output signal of the slope monitoring and sampling circuit. The slope control signal controls the driver circuit through a source follower circuit, enabling the driver circuit to generate a LIN output signal with a predetermined slope.

[0034] To achieve precise current limiting control of the driving ability, the current sampling circuit samples the current flowing through the driver circuit, and the current limiting control circuit controls the driver circuit based on the sampled voltage, restricting the maximum output current of the LIN driver circuit to a predetermined level. Even in the event of a short-circuit fault, excessive output current will not be generated.

[0035] Figure 2 Shows the circuit diagram of the LIN driver circuit of the present invention.

[0036] The buffer circuit Buffer is used to implement the buffering function. Here, it can also be replaced with a level conversion circuit to solve the problem of voltage domain mismatch between the input signal TXD and the LIN driver circuit. The input signal TXD is input into the buffer circuit Buffer, generating a buffered input signal TXD_BF that is compatible with the LIN driver circuit.

[0037] The slope control circuit includes a digital control circuit DAC_Control, current sources IDAC_P and IDAC_N, a first transistor S1, and a second transistor S2. The first current source IDAC_P, the first transistor S1, the second transistor S2, and the second current source IDAC_N are connected in series in sequence. The input terminal of the first current source IDAC_P is connected to the high level VDD, and the output terminal of the second current source IDAC_N is grounded. The buffered input signal TXD_BF is input to the gates of the first transistor S1 and the second transistor S2, used to control the conduction and cutoff of the first transistor S1 and the second transistor S2. The digital control signal generated by the digital control circuit DAC_Control is used to control the current values output by the current sources IDAC_P and IDAC_N. Among them, the first transistor S1 is a PMOS transistor, and the second transistor S2 is an NMOS transistor. The connection point of the first transistor S1 and the second transistor S2 forms the output terminal of the slope control circuit, used to output the slope control signal Vslope.

[0038] The source follower circuit includes a third transistor ND and a third current source Inbias1. The third transistor ND and the third current source Inbias1 are connected in series. The input terminal of the third transistor ND is connected to the high level VDD, and the output terminal of the third current source Inbias1 is grounded. The slope control signal Vslope is input to the gate of the third transistor ND, which is used to control the source follower circuit to generate the drive signal Vdrive. Among them, the third transistor ND is an NMOS transistor. The connection point of the third transistor ND and the third current source Inbias1 forms the output terminal of the source follower circuit, which is used to output the drive signal Vdrive.

[0039] The drive circuit includes a fourth transistor N1 and a zener diode D0. The zener diode D0 and the fourth transistor N1 are connected in series. The drive signal Vdrive is input to the gate of the fourth transistor N1 to drive the fourth transistor N1 to generate the LIN output signal. The zener diode D0 is used to provide negative voltage protection for the fourth transistor N1. The positive electrode of the zener diode D0 is connected to the pull-up circuit. The connection point of the zener diode D0 and the pull-up circuit forms the output terminal of the LIN drive circuit, which is used to output the LIN output signal. Among them, the fourth transistor N1 is an NMOS transistor.

[0040] The pull-up circuit includes a resistor R0 and a diode D1 connected in series. The input terminal of the resistor R0 is connected to the power supply voltage VS, and the output terminal of the diode D1 is connected to the positive electrode of the zener diode D0. The pull-up circuit provides a high-voltage power supply for the drive circuit.

[0041] The slope monitoring and sampling circuit includes a sampling capacitor C. One end of the sampling capacitor C is connected to the output terminal of the LIN drive circuit, and the other end is connected to the output terminal of the slope control circuit. The sampling capacitor C is used to monitor and sample the LIN output signal. The slope control circuit generates a desired slope control signal according to the output signal of the sampling capacitor C, and then controls the drive circuit to generate a LIN output signal with a predetermined slope.

[0042] When TXD is at a high level, TXD_BF is a high-level voltage compatible with the LIN drive circuit, controlling the first transistor S1 to be cut off and the second transistor S2 to be turned on. Due to the existence of the sampling capacitor C, the voltage of the slope control signal Vslope forms the Miller effect, and it does not decrease linearly, but decreases from VDD to the voltage Vmiller = V th_ND +V th_N1 and then maintains a Miller plateau time Trise, and then continues to decrease to 0V. Among them, V th_ND is the threshold voltage of the NMOS type third transistor ND, and V th_N1 is the threshold voltage of the NMOS type fourth transistor N1.

[0043] The driving signal Vdriver follows the slope control signal Vslope, and its value is Vdriver = Vslope - V th_N1 , and then drives the fourth transistor N1. The LIN output signal linearly rises within the Miller plateau time, and its rising slope is:

[0044]

[0045] where ΔVLIN is the voltage change at the output terminal of the LIN driving circuit. When rising, the output terminal voltage rises from 0V to the power supply voltage VS; when falling, the output terminal voltage falls from the power supply voltage VS to 0V. IDAC_N is the current value output by the current source IDAC_N. C is the capacitance value of the sampling capacitor C.

[0046] IDAC_N and C determine the slope Slewrate rise . In the actual products of our company, the recommended typical slope value is 1.2V / uS, which can generate lower EMI.

[0047] Similarly, when TXD is at a low level, TXD_BF is a low-level voltage compatible with the LIN driving circuit, controlling the first transistor S1 to conduct and the second transistor S2 to cut off. Due to the existence of the sampling capacitor C, the voltage of the slope control signal Vslope forms the Miller effect and does not rise linearly, but rises from 0V to the voltage Vmiller = V th_ND +V th_N1 and then maintains a Miller plateau time Tfall, and then continues to rise to VDD. The driving signal Vdriver follows the slope control signal Vslope, and then drives the fourth transistor N1. The LIN output signal linearly falls within the Miller plateau time, and its falling slope is

[0048]

[0049] DAC_P is the current value output by the current source IDAC_P.

[0050] Through simple derivation, it can be obtained that:

[0051]

[0052]

[0053] If IDAC_N = IDAC_P, then Trise is the same as Tfall, and the rising slope is the same as the falling slope. In order to satisfy the consistency of the rising slope and the falling slope of the LIN output signal, it is often required that IDAC_N = IDAC_P. However, in the actual scheme, it is not mandatory to be the same, but can be adjusted according to the EMI evaluation test results.

[0054] The current sampling circuit includes a sampling resistor Rsense. The fourth transistor N1 is grounded through the sampling resistor Rsense. The current flowing through the fourth transistor N1 generates a sampling voltage Vsense across the sampling resistor Rsense.

[0055] The current limiting control circuit includes an operational amplifier OP and a fifth transistor N0. The sampling voltage Vsense is input to the first input terminal of the operational amplifier OP, and the reference voltage Vref_limit is input to the second input terminal of the operational amplifier OP. The output terminal of the operational amplifier OP is connected to the gate of the fifth transistor N0. The input terminal of the fifth transistor N0 is connected to the gate of the fourth transistor N1, and the output terminal of the fifth transistor N0 is grounded. Among them, the fifth transistor N0 is an NMOS transistor. The operational amplifier OP compares the sampling voltage Vsense with the reference voltage Vref_limit. When the sampling voltage Vsense is greater than the reference voltage Vref_limit, the current limiting control circuit turns off the drive circuit. Specifically, the operational amplifier OP controls the fourth transistor N1 to turn off through the fifth transistor N0, so that the maximum output current of the drive circuit is limited to a predetermined level.

[0056] During the normal operation stage of the LIN slave node, because the resistor R0 is usually relatively large (for example, 30KΩ), the maximum current Imax flowing through the fourth transistor N1 is approximately VS / R0, and Imax is less than the preset current limiting value Ilimit, so the current limiting protection function will not be triggered. However, when TXD is at a high level and the fourth transistor N1 is short-circuited to the power supply voltage VS, the output voltage VLIN of the LIN drive circuit is VS. At this time, Imax will be very large, triggering the current limiting circuit to start working. Through the action of negative feedback, Vsense can be forced not to exceed Vref_limit. At this time, Imax = Ilimit = Vref_limit / Rsense. Thus, the present invention can limit the maximum output current of the LIN drive circuit to a predetermined level, and even in the event of a short-circuit fault, an excessive output current will not be generated.

[0057] In order to integrate the current limiting circuit and the slope control circuit in the LIN drive circuit, the present invention provides a source follower circuit.

[0058] The source follower circuit can provide voltage isolation. There is a gate-source voltage Vgs of the third transistor ND between the output and the input of the source follower circuit. Therefore, the gate voltage of the fourth transistor N1 can be made unaffected by the capacitor C, thereby providing a stable voltage supply for the fourth transistor N1. At the same time, the influence of the gate capacitance Cg of the fourth transistor N1 on the capacitor C can be isolated, making the sampling result of the sampling capacitor C more accurate.

[0059] On the other hand, during current limiting, the source follower circuit can provide a DC bias for the normal operation of the fifth transistor N0 in the current limiting circuit, and at the same time provide a high-frequency pole for the output terminal of the fifth transistor N0, which is beneficial to maintaining the stability of the operating point of the fourth transistor N1 and does not affect the stability of the current limiting circuit.

[0060] The high-frequency pole provided by the output terminal of the fifth transistor N0 is:

[0061] P N0_d ≈G m_ND / Cpar

[0062] Wherein, P N0_d is the pole of the drain terminal node of the fifth transistor N0; G m_ND is the transconductance of the third transistor ND; Cpar is the total parasitic capacitance of the drain terminal node of the fifth transistor N0, including the gate-source capacitance Cgs of the fourth transistor N1 and the drain-source capacitance Cds of the fifth transistor N0, etc.

[0063] In addition, the source follower circuit can act as a protection circuit to provide a certain protection function to prevent damage caused by the gate voltage of the fourth transistor N1 being too high or too low.

[0064] Therefore, the source follower circuit can provide voltage isolation, signal stability and protection functions, and is an important part of the circuit design of the present invention.

[0065] Figure 3 shows a waveform diagram of the key node voltage signal of the present invention. As shown in the figure, the present invention can make the drive signal output by the LIN drive circuit have an appropriate slope.

[0066] The present invention integrates the current limiting circuit and the slope control circuit into the LIN drive circuit. By setting the source follower circuit, not only can current limiting and slope control be well realized, but also the circuit is simple, easy to implement, and convenient for low-cost integration.

[0067] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural transformation made under the concept of the present invention by using the content of the specification and drawings of the present invention, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. LIN driver circuit integrating current limiting and slope control, comprising: Slope control circuit, slope monitoring and sampling circuit, source follower circuit, driving circuit; The slope monitoring and sampling circuit samples the LIN output signal generated by the driving circuit; The slope control circuit generates a slope control signal according to the input signal and the output signal of the slope monitoring and sampling circuit; the slope control signal controls the driving circuit through the source follower circuit, so that the driving circuit generates a LIN output signal with a predetermined slope; it is characterized in that it further includes: a current sampling circuit and a current limiting control circuit; The current sampling circuit samples the current flowing through the driving circuit; The current sampling circuit includes a sampling resistor that generates a sampling voltage, and the driving circuit is grounded through the sampling resistor; The current limiting control circuit compares the sampling voltage with a reference voltage. When the sampling voltage is greater than the reference voltage, the current limiting control circuit turns off the driving circuit, so that the maximum output current of the driving circuit is limited to a predetermined level Ilimit, Ilimit = Vref_limit / Rsense, where Vref_limit is the reference voltage level and Rsense is the resistance value of the sampling resistor; The current limiting control circuit includes an operational amplifier and a fifth transistor. The sampling voltage is input to the first input terminal of the operational amplifier, the reference voltage is input to the second input terminal of the operational amplifier, the output terminal of the operational amplifier is connected to the gate of the fifth transistor, the input terminal of the fifth transistor is connected to the input terminal of the driving circuit and the output terminal of the source follower circuit, and the output terminal of the fifth transistor is grounded, The source follower circuit provides a DC bias for the fifth transistor and provides a high-frequency pole for the output terminal of the fifth transistor, The operational amplifier compares the sampling voltage with the reference voltage. When the sampling voltage is greater than the reference voltage, the operational amplifier turns off the driving circuit through the fifth transistor.

2. The LIN driving circuit according to claim 1 further comprises: A buffer circuit for buffering the input signal to match the voltage domain of the input signal and the LIN driving circuit.

3. The LIN driving circuit according to claim 1, wherein, The slope control circuit includes a first current source, a second current source, a first transistor, and a second transistor, and the first current source, the first transistor, the second transistor, and the second current source are connected in series in sequence.

4. The LIN driving circuit according to claim 3, wherein, The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

5. The LIN driving circuit according to claim 3 or 4, wherein, The slope monitoring and sampling circuit includes a sampling capacitor, one end of the sampling capacitor is connected to the output terminal of the LIN driving circuit, and the other end is connected to the connection point of the first transistor and the second transistor.

6. The LIN driving circuit according to claim 1, wherein, The source follower circuit includes a third transistor and a third current source connected in series. The slope control signal is input to the gate of the third transistor, and the connection point of the third transistor and the third current source forms the output terminal of the source follower circuit to generate a driving signal.

7. The LIN driving circuit according to claim 6, wherein, The driving circuit includes a zener diode and a fourth transistor connected in series. The driving signal is input to the gate of the fourth transistor to drive the fourth transistor to generate a LIN output signal.

8. The LIN driving circuit according to claim 7, wherein the third transistor and the fourth transistor are NMOS transistors.

9. The LIN driving circuit according to claim 7 or 8, wherein the input end of the fifth transistor is connected to the source electrode of the third transistor and the gate electrode of the fourth transistor; The high-frequency pole of the output end of the fifth transistor is: P N0_d ≈G m_ND / Cpar Among them, P N0_d is the pole of the drain of the fifth transistor; G m_ND is the transconductance of the third transistor; Cpar is the total parasitic capacitance of the drain of the fifth transistor, including the gate-source capacitance Cgs of the fourth transistor and the drain-source capacitance Cds of the fifth transistor.

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