High voltage level shifting circuit with adaptive dead band

Abstract

The application provides a high-voltage level shift circuit with adaptive dead zone, and the level shift circuit comprises a level shift module, a dv / dt noise detection module, a blank signal control module and an output module. The blank-off technology is used to prevent the dv / dt noise from affecting the output through the signal chain. The blank time is adaptively adjusted by the dv / dt noise detection module when facing different dv / dt noises, so that the limitation of the minimum on time of the input signal in the application is solved. A low transmission delay, high dv / dt noise resistance and low minimum input signal on time are obtained, and the application requirements of a DCDC system and a driving circuit system are met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power MOS driving circuit, in particular to a high-voltage level shift circuit with adaptive dead zone. BACKGROUND

[0002] GaN power MOS has lower FOM value than Si power MOS, and is widely used in high-frequency high-performance power driving circuit; in order to fully exert the performance of GaN power MOS, it is necessary to customize high-frequency, high-efficiency and high-reliability level shift circuit. In high-frequency half-bridge GaN driving chip, the level shift circuit converts the input logic signal from low level to high level logic output for controlling the high-voltage side GaN power MOS. The characteristics of GaN driving chip put forward high requirements for the design of level shift circuit. Especially in high-frequency application, GaN driving chip works at tens of megahertz of working frequency, which requires the level shift circuit to work normally and have low propagation delay, and the minimum on-time limit of the input signal should be small enough. In order to maintain efficiency and avoid overheating of GaN driving chip, the power consumption of level shift circuit should be as low as possible, and the limited charge on the bootstrap capacitor between high-voltage domain power supply rails should be as small as possible. The input and output capacitance of GaN power MOS is extremely small, which will cause more than 100V / ns high dv / dt noise during driving, which will affect the output logic of level shift circuit, so that the reliability of level shift circuit cannot be guaranteed, which requires the level shift circuit to have high dv / dt noise resistance. GaN power MOS has no body diode, when the half-bridge driving chip works in dead zone time, the negative voltage transient of high-voltage domain ground can be lower than about-2V, which requires the level shift circuit to have high negative power supply tolerance. SUMMARY

[0003] Based on this, the present application aims to provide a high-voltage level shift circuit with adaptive dead zone, which can not only ensure the high reliability of level shift circuit when driving GaN, but also reduce the minimum on-time limit of input signal as much as possible.

[0004] In order to achieve the above purpose, the present application provides a high-voltage level shift circuit with adaptive dead zone, which comprises a level shift module, a dv / dt noise detection module, a blank signal control module and an output module.

[0005] The level shift module comprises: LDMOS tube M1, LDMOS tube M2, monostable trigger circuit one shoot1, monostable trigger circuit one shoot2, PMOS tube M4, PMOS tube M5, PMOS tube M7, PMOS tube M8, PMOS tube M10, PMOS tube M11, resistor R1, resistor R2, resistor R4, resistor R5, diode D1, diode D2, wherein the input signal is connected to the gate of the LDMOS tube M1 through one shoot1, the input signal is connected to the gate of the LDMOS tube M2 through an inverter and one shoot2, the sources of the LDMOS tubes M1 / M2 are grounded VSS, the sources of the PMOS tubes M4 / M5 are connected to a high-voltage power supply VDDH, the gates and the drains are short-circuited and connected to the drains of the LDMOS tubes M1 / M2 and the PMOS tubes M7 / M8, the sources of the NMOS tubes M10 / M11 are connected to a high-voltage ground VSW, and the gates and the drains are short-circuited and connected to the drains of the PMOS tubes M7 / M8, and are recorded as signals VO2 / VO1, the signals VO2 / VO1 are connected to the high-voltage ground VSW through resistors R4 / R5 respectively, the resistors R1 / R2 are respectively between the drains and the sources of the PMOS tubes M4 / M5, and the high-voltage ground VSW is connected to the drains of the LDMOS tubes M1 / M2 through diodes D1 / D2 respectively.

[0006] The dv / dt noise detection module comprises: LDMOS tube M3, PMOS tube M6, PMOS tube M9, NMOS tube M12, resistor R3, resistor R6, diode D3, wherein the LDMOS tube M3 is biased in the cutoff region, the gate and the source are grounded VSS, the drain is connected to the gate and the drain of the PMOS tube M6 and the drain of the PMOS tube M9, the sources of the PMOS tubes M6 and M9 are connected to a high-voltage power supply VDDH, the gate and the drain of the NMOS tube M12 are short-circuited and connected to the drain of the PMOS tube M9, recorded as a signal VO3, the signal VO3 is connected to a high-voltage ground VSW through a resistor R6, the high-voltage ground VSW is connected to the drain of the LDMOS tube M3 through a diode D3, and the resistor R3 is connected in parallel between the drain and the source of the PMOS tube M6.

[0007] The above scheme of the present application at least has the following beneficial effects:

[0008] In the embodiment of the present application, the large dv / dt immunity capability is realized by cutting off the signal path through the switch, and for the input pulse width limitation problem caused thereby, the dv / dt noise detection circuit is adopted to realize the copying of the influence of the dv / dt noise of the signal path under the condition of process, voltage and temperature variation, so as to generate adaptive BLK pulse width to reduce the pulse width limitation on the input PWM signal; therefore, the final level shift circuit has low delay, high dv / dt noise immunity capability, low input pulse width limitation and good robustness.

[0009] Other features and advantages of the present application will be illustrated in the following description, or can be inferred from the description or determined without doubt, or can be known by implementing the above-mentioned technologies of the present application.

[0010] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are specifically described, and the accompanying drawings are referred to for detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 Structure diagram of the level shift circuit with adaptive dead zone and high dv / dt noise immunity in the embodiment of the present application;

[0012] Figure 2 Structure diagram of the traditional level shift circuit;

[0013] Figure 3 Structure diagram of the level shift module circuit in the embodiment of the present application;

[0014] Figure 4 Structure diagram of the dv / dt noise detection module circuit in the embodiment of the present application;

[0015] Figure 5 Structure diagram of the blank signal control module and output module circuit in the embodiment of the present application;

[0016] Explanation of reference signs:

[0017] 1 Level shift module circuit

[0018] 2 dv / dt noise detection module circuit

[0019] 3 blank signal control module and output module circuit

[0020] VDDH floating voltage domain high power rail power terminal

[0021] VSW floating voltage domain high power rail ground terminal

[0022] VDD power terminal

[0023] GND ground terminal

[0024] GND ground

[0025] IN level shift circuit input end

[0026] EN enable signal input end DETAILED DESCRIPTION

[0027] For the purpose of facilitating the understanding of the present application, a more complete understanding of the present application will be provided in the following with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided for the purpose of making the disclosure of the present application more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application herein only for the purpose of describing the specific embodiments and is not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0029] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and is not limited to the embodiments described herein.

[0030] Please refer to FIGS. 2 to 5 Figure 5 As shown in FIGS. 2 to 5, the present application proposes a high-voltage level shift circuit with adaptive dead zone, and introduces four specific circuit structures, including a level shift module 1, a dv / dt noise detection module 2, a blank signal control module, and an output module 3.

[0031] In the embodiment of the present application, the level shift module comprises: LDMOS tube M1, LDMOS tube M2, monostable trigger circuit one shoot1, monostable trigger circuit one shoot2, PMOS tube M4, PMOS tube M5, PMOS tube M7, PMOS tube M8, PMOS tube M10, PMOS tube M11, resistor R1, resistor R2, resistor R4, resistor R5, diode D1, diode D2; wherein the input signal is connected to the gate of the LDMOS tube M1 through one shoot1, the input signal is connected to the gate of the LDMOS tube M2 through an inverter and one shoot2, the sources of the LDMOS tubes M1 / M2 are grounded VSS; the sources of the PMOS tubes M4 / M5 are connected to a high-voltage power supply VDDH, the gates and the drains are short-circuited and connected to the drains of the LDMOS tubes M1 / M2 and the PMOS tubes M7 / M8; the sources of the NMOS tubes M10 / M11 are connected to a high-voltage ground VSW, and the gates and the drains are short-circuited and connected to the drains of the PMOS tubes M7 / M8, which are recorded as signals VO2 / VO1; the signals VO2 / VO1 are connected to the high-voltage ground VSW through resistors R4 / R5 respectively; the resistors R1 / R2 are respectively between the drains and the sources of the PMOS tubes M4 / M5; the high-voltage ground VSW is connected to the drains of the LDMOS tubes M1 / M2 through diodes D1 / D2 respectively.

[0032] In the embodiment of the present application, the dv / dt noise detection module comprises: LDMOS tube M3, PMOS tube M6, PMOS tube M9, NMOS tube M12, resistor R3, resistor R6, diode D3; wherein the LDMOS tube M3 is biased in the cutoff region, the gate and the source are grounded VSS, the drain is connected to the gate and the drain of the PMOS tube M6 and the drain of the PMOS tube M9; the sources of the PMOS tube M6 and the PMOS tube M9 are connected to a high-voltage power supply VDDH; the gate and the drain of the NMOS tube M12 are short-circuited and connected to the drain of the PMOS tube M9, which is recorded as a signal VO3; the signal VO3 is connected to a high-voltage ground VSW through a resistor R6; the high-voltage ground VSW is connected to the drain of the LDMOS tube M3 through a diode D3; the resistor R3 is connected in parallel between the drain and the source of the PMOS tube M6.

[0033] In the specific embodiments of the application, the blank signal control module and the output module comprise: a switch SW1, a switch SW2, a monostable trigger circuit one shoot 3, a monostable trigger circuit one shoot 4, a SR latch SR latch 1, a SR latch SR latch 2, and a plurality of logic gate circuits; the signal VO2 / signal VO1 is connected to the set end S1 and the reset end R1 of the SR latch SR latch 1 through the switch SW1 / switch SW2 and an inverter, respectively; the signal VO3 is connected to the input end of the monostable trigger circuit one shoot 3 through two inverters, and the output of the input end of the one shoot 4 is connected to the enable signal EN and is recorded as a reset signal RN; the set end S1 of the SR latch 1 is connected to the input of the monostable trigger circuit one shoot 3, and the output of the one shoot 3 is connected to the set end S2 of the SR latch SR latch 2; the reset end of the SR latch SR latch 2 is connected to the reset signal RN, and the output signal is recorded as a signal BLK through an inverter and is recorded as a signal BLKB through another inverter; the signals BLK and BLKB together control the opening and closing of the switch SW1 and the switch SW2.

[0034] Specifically, the level shift module is configured to: receive an input PWM signal, generate a single short pulse signal for driving an LDMOS through a monostable circuit; generate a pull-down current through the LDMOS, and the pull-down current is copied on an NMOS working in a high-voltage domain through a current mirror and generates a characteristic signal.

[0035] Specifically, the dv / dt noise detection module is configured to: when no da / dt event occurs, the entire dv / dt noise detection module has a static power consumption of 0 due to the LDMOS tube being biased in the cut-off region, so as to ensure the low-power consumption requirement of the circuit; when the floating voltage domain (VSW-VDDH) is pumped from a low voltage to a high voltage, a Cds*(dv / dt) current is generated on the large parasitic capacitance between the drain and the source of the LDMOS; since the detection module and the signal link module work in the same condition at this time, the detection module can generate an equal Cds*(dv / dt) current for judging whether the dv / dt event is over.

[0036] Specifically, the blank signal control module is configured to: when the level shift module receives the input PWM signal, the characteristic signal is transmitted to the output, at this time the blank signal control module generates the BLK signal to control the switch SW1 / SW2 on the signal chain to be off, preventing the subsequent dv / dt noise from affecting the output through the switch, and the switch SW1 / SW2 is not reset until the dv / dt noise detection module detects that the dv / dt event ends, so as to be ready for the next input, that is, the width of the BLK signal is adaptively adjusted to reduce the limitation on the input signal pulse width.

[0037] Specifically, the output module is configured to: receive the logic signal to be output by the previous stage, and has a latching and driving capability.

[0038] Finally, it should be noted that: the above-described embodiments are only specific implementations of the present application, which are used to illustrate the technical solutions of the present application, but not to limit it, the protection scope of the present application is not limited to this, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: any person skilled in the art within the technical range disclosed by the present application, it can still modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A high voltage level shift circuit with adaptive dead zone, the level shift circuit comprising a level shift module, a dv / dt noise detection module, a blank signal control module, an output module; characterized in that, The level shift module comprises: an LDMOS tube M1, an LDMOS tube M2, a monostable trigger circuit one shoot1, a monostable trigger circuit one shoot2, a PMOS tube M4, a PMOS tube M5, a PMOS tube M7, a PMOS tube M8, an NMOS tube M10, an NMOS tube M11, a resistor R1, a resistor R2, a resistor R4, a resistor R5, a diode D1, and a diode D2; wherein an input signal is connected to the gate of the LDMOS tube M1 through the one shoot1, the input signal is connected to the gate of the LDMOS tube M2 through an inverter and the one shoot2, the source of the LDMOS tube M1 is grounded VSS, and the source of the LDMOS tube M2 is grounded VSS; the source of the PMOS tube M4 is connected to a high-voltage power supply VDDH, the gate and the drain of the PMOS tube M4 are short-circuited, and are connected to the drain of the LDMOS tube M1 and the source of the PMOS tube M7; the source of the PMOS tube M5 is connected to the high-voltage power supply VDDH, the gate and the drain of the PMOS tube M5 are short-circuited, and are connected to the drain of the LDMOS tube M2 and the source of the PMOS tube M8; the source of the NMOS tube M10 is connected to a high-voltage ground VSW, the gate and the drain of the NMOS tube M10 are short-circuited, and are connected to the drain of the PMOS tube M7, and the connection point is recorded as a signal VO2; the source of the NMOS tube M11 is connected to the high-voltage ground VSW, the gate and the drain of the NMOS tube M11 are short-circuited, and are connected to the drain of the PMOS tube M8, and the connection point is recorded as a signal VO1; the signal VO2 is connected to the high-voltage ground VSW through the resistor R4; the signal VO1 is connected to the high-voltage ground VSW through the resistor R5; the resistor R1 is connected between the drain and the source of the PMOS tube M4; the resistor R2 is connected between the drain and the source of the PMOS tube M5; the high-voltage ground VSW is connected to the drain of the LDMOS tube M1 through the diode D1; and the high-voltage ground VSW is connected to the drain of the LDMOS tube M2 through the diode D2; the dv / dt noise detection module comprises: an LDMOS tube M3, a PMOS tube M6, a PMOS tube M9, an NMOS tube M12, a resistor R3, a resistor R6, and a diode D3; wherein the gate and the source of the LDMOS tube M3 are grounded VSS, the drain is connected to the gate and the drain of the PMOS tube M6 and the drain of the PMOS tube M9; the sources of the PMOS tube M6 and the PMOS tube M9 are connected to the high-voltage power supply VDDH; the gate and the drain of the NMOS tube M12 are short-circuited, and are connected to the drain of the PMOS tube M9, and the connection point is recorded as a signal VO3; the signal VO3 is connected to the high-voltage ground VSW through the resistor R6; the high-voltage ground VSW is connected to the drain of the LDMOS tube M3 through the diode D3; and the resistor R3 is connected in parallel between the drain and the source of the PMOS tube M6.The blank signal control module and output module include: switch SW1, switch SW2, monostable trigger circuit one shoot3, monostable trigger circuit one shoot4, SR latch SR latch1, SR latch SR latch2, and several logic gate circuits; the signal VO2 is connected with the set end S1 of the SR latch SR latch1 after passing through the switch SW1 and the first inverter; the signal VO1 is connected with the reset end R1 of the SR latch SR latch1 after passing through the switch SW2 and the second inverter; the signal VO3 is connected with the input end of the monostable trigger circuit one shoot3 after passing through the third inverter and the fourth inverter; the input end of the monostable trigger circuit one shoot4 is connected with the enable signal EN to generate the reset signal RN; the set end S1 of the SR latch SR latch1 is connected with the input of the monostable trigger circuit one shoot3, and the output of the monostable trigger circuit one shoot3 is connected to the set end S2 of the SR latch SR latch2; the reset end of the SR latch SR latch2 is connected with the reset signal RN, and the output signal of the SR latch SR latch2 is recorded as the signal BLK after passing through the fifth inverter, and the signal BLK is recorded as the signal BLKB after passing through the sixth inverter; the signals BLK and BLKB are used for controlling the opening and closing of the switch SW1 and the switch SW2.

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