Low-complexity real-time nonlinear compensation method for short-distance optical fiber link system

By using Volterra algorithm and non-uniform quantization and pruning methods in the optical link system, the problem of excessive complexity of non-linear distortion calculation in the optical link system is solved, and real-time non-linear compensation is achieved in low complexity, reducing power consumption and maintaining efficient signal transmission.

CN119652420AActive Publication Date: 2025-03-18FUDAN UNIVERSITY
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Patent Information

Application Number
CN202411668952.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-21
Publication Date
2025-03-18
Estimated Expiration
2044-11-21

AI Technical Summary

Technical Problem

In the high-speed signal transmission, the existing optical link system has caused too much computational complexity and is difficult to achieve real-time nonlinear compensation.

Method used

The Volterra algorithm is used to perform nonlinear damage compensation, and the complexity is reduced through non-uniform quantization and pruning methods to achieve real-time non-linear compensation in low complexity.

Benefits of technology

It successfully reduces complexity and power consumption, and achieves successful transmission of 25km single-mode fibers with 29.4912Gbit/s PAM4 signal, maintaining nonlinear compensation capabilities.

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Abstract

The invention belongs to the technical field of optical fiber communication, and particularly relates to a low-complexity real-time nonlinear compensation method for a short-distance optical fiber link system. According to the method, nonlinear damage compensation is realized by adopting a Wollaston algorithm, the algorithm is regarded as a filter for adaptively updating taps, and the algorithm is divided into a linear term finite impulse response filter calculation module, a nonlinear term finite impulse response filter calculation module, an error calculation module and a tap coefficient updating module; and low-complexity processing of nonlinear compensation is further realized through pruning and non-uniform quantization. According to the invention, the problem of nonlinear distortion caused by devices and transmission in an intensity modulation direct detection system is solved, the realization is simpler, and the complexity is greatly reduced, so that more power consumption is saved, and the method is verified on an FPGA development board; a basis is provided for realizing nonlinear compensation on hardware, and a foundation is laid for further development of a future optical fiber communication system.
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Description

Technical Field

[0001] The invention belongs to the technical field of optical fiber communication, and in particular relates to a low-complexity real-time nonlinear compensation method. Background Art

[0002] As society enters the new information age, global network traffic has exploded, which has brought huge challenges to existing communication networks. Therefore, achieving large-capacity data transmission under limited bandwidth has become an important task in the communications industry. Recent studies have shown that intensity modulation direct detection (IM / DD) systems play an important role in supporting high-speed signal transmission.

[0003] Generally, bandwidth limitation and nonlinearity in optical links have serious impacts on high-speed signal transmission. In addition, there are nonlinear distortions caused by devices and transmission in IM / DD systems. However, the compensation for nonlinear loss is usually very complex. Due to limited hardware resources, the problem of excessive computational complexity needs to be solved in order to implement real-time nonlinear compensation. If low-complexity real-time nonlinear compensation technology can be successfully implemented, it can play a key role in future communications. Summary of the invention

[0004] The purpose of the present invention is to provide a low-complexity real-time nonlinear compensation method that can be implemented on a hardware platform, which is used for intensity modulation direct detection of single-carrier pulse amplitude modulation signals in short-distance optical fiber link systems to solve the nonlinear distortion problem caused by devices and transmission.

[0005] The real-time nonlinear compensation method for a short-distance optical fiber link system provided by the present invention specifically includes two parts: compensation of nonlinear damage and reduction of complexity. The description is as follows:

[0006] 1. Nonlinear damage compensation:

[0007] The present invention adopts a nonlinear compensation algorithm to realize nonlinear damage compensation. The nonlinear compensation algorithm is specifically the Volterra algorithm (Jia Kejun, Lei Lei, Lin Ying, et al. Design and research of Volterra hybrid equalizer based on memory polynomial [J]. Optical Communication Research, 2024, (03): 40-48. DOI: 10.13756 / j.gtxyj.2024.230077.), which can be regarded as a filter that adaptively updates taps. The algorithm is divided into a linear term finite impulse response filter calculation module, a nonlinear term finite impulse response filter calculation module, an error calculation module and a tap coefficient update module. Wherein:

[0008] The sum of the outputs of the linear finite impulse response filter and the nonlinear finite impulse response filter is a complete output linear part and nonlinear part. The calculation expressions of the two calculation modules are as follows:

[0009]

[0010] Among them, w l1 (k) and w l1,l2 (k) represents the tap coefficients corresponding to the linear part and the nonlinear part respectively, N1 and N2 represent the memory lengths of the linear part and the nonlinear part. The parameter k represents the current time point. In discrete signal processing, k is a discrete time index, indicating the current sampling moment. The left side of the formula y(k) is the output signal at the current moment. x(k) represents the input signal, l1, l2 represent the time delay index of the input signal x(k). x(k-l1) represents the value of the input signal delayed by l1 at the current moment k. Similarly, x(k-l2) represents the value delayed by l2.

[0011] The error calculation module is equipped with a decision maker, which is implemented by a conditional decision statement. Specifically, three threshold values ​​of 0.5, 0, and -0.5 are set to make a decision, and the output signal is decided to be -0.75, -0.25, 0.25, and 0.75. The sum of the outputs of the above two filters is subtracted from the standard constellation point output by the decision maker to obtain the error. The calculation expression is as follows:

[0012] e(k)=d(k)-y(k) , (2)

[0013] d(k) is the standard constellation point output by the decision device, y(k) is the output signal of the above two filters, and e(k) is the error.

[0014] The tap coefficient update module is used to update the tap values ​​required in the finite impulse response filter calculation module. The required inputs include the filter output and the error calculated by the error calculation module. The calculation expression is as follows:

[0015] w(k+1)=w(k)+μe(k)x * (k) , (3)

[0016] w(k) refers to the coefficient before updating, w(k+1) refers to the coefficient after updating, μ is the iteration step, e(k) is the error calculated by the error module, and x(k) is the input signal.

[0017] The Volterra algorithm is implemented using a hardware description language and deployed in a field programmable gate array development board. The hardware platform is arranged in an intensity modulation direct detection communication system and is used to process the received signal at the receiving end in real time. The receiving end converts the received pulse amplitude modulation signal into a digital sequence through an analog-to-digital converter (ADC), and then sends the digital sequence to the field programmable gate array development board. By distributing the digital sequence to the digital signal processing module deployed on the field programmable gate array development board, the linear term of the input signal and the corresponding tap coefficient are calculated, the nonlinear term of the input signal is generated, and the nonlinear term and the corresponding tap coefficient are calculated in the linear term finite impulse response filter calculation module and the nonlinear term finite impulse response filter calculation module. The error is calculated in the error calculation module and the tap coefficient update module, and the linear term and the nonlinear term corresponding tap coefficient are updated. For the specific calculation and update process, please refer to the above formulas (1), (2), and (3).

[0018] After the Volterra algorithm used in the present invention is implemented on a field programmable gate array platform, it can be equivalent to an equalizer with a nonlinear compensation capability that updates taps adaptively. The first operation after the equalizer starts working uses the initially set tap value. As the calculation proceeds, the tap coefficient is updated based on the minimum mean square error until the tap coefficient converges to achieve an ideal nonlinear compensation effect.

[0019] (II) Reduce complexity processing:

[0020] The difficulty in implementing real-time nonlinear compensation on a hardware platform mainly comes from the large computational complexity caused by too many multiplication calculations. To address this problem, the present invention uses pruning and non-uniform quantization methods to reduce the complexity.

[0021] In the short-distance optical link system, by sorting out the tap coefficients after convergence, we found that the tap coefficient part corresponding to the linear term is exponentially distributed, and the tap weights at the same position of different power points are relatively stable. Therefore, by quantizing the taps at some positions through non-uniform quantization, the multipliers consumed by updating the taps at this position can be saved. This scheme is very suitable for deployment in the linear part of the algorithm. On the field programmable gate array development board, by adopting non-uniform quantization based on the exponential of two, the multipliers consumed by multiplying the input signal with the tap can also be saved, because in the hardware description language (Verilog), the multiplication of the exponential of two can be realized by arithmetic shift. The quantization formula is as follows:

[0022]

[0023] b is the number of quantization bits. The larger the number of quantization bits, the higher the accuracy. u is the quantization level.

[0024] By sorting out and observing the tap coefficients corresponding to the nonlinear part, we found that they are sparsely distributed, and the tap weights at most locations are very small, which has a very small impact on the final result. Therefore, a threshold value T can be found. This value takes into account the balance between performance and resources. By setting the weights less than the threshold value to zero, the multiplication consumed by tap updates and multiplication of nonlinear terms and taps can be saved. This solution is very suitable for deployment in the nonlinear part of the algorithm. The pruning formula is as follows:

[0025] W Nonlinear (k)=0,if |W Nonlinear (k)|<T , (5)

[0026] Among them, W Nonlinear is the tap coefficient corresponding to the nonlinear part, and T is the pruning threshold. The threshold cannot be too large, otherwise too much performance will be lost. If it is too small, too few resources will be released. By setting a small initial value for T and then performing simulation, the performance loss is judged by the bit error rate. If the performance loss is acceptable, the T value is increased and iterative updates are performed until an acceptable balance point is found, that is, the performance loss is not too much and the released resources are objective.

[0027] The present invention can provide nonlinear damage compensation capability while greatly reducing complexity and saving power consumption, thus providing a basis for realizing nonlinear compensation in hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The invention utilizes the short-distance optical link real-time communication system architecture.

[0029] Figure numerals: 1 is the transmitting end of the short-distance optical link communication system, which includes a DAC; 2 is the system optical fiber link; 3 is the receiving end of the system, which includes an ADC; 4 is a hardware platform for deploying a real-time DSP algorithm, which may adopt an FPGA development board; 5 is a linear compensation algorithm; 6, 7 and 8 are the processes of the present invention, wherein 6 is a nonlinear compensation algorithm, 7 and 8 are respectively complexity reduction schemes deployed in 6, 7 is a non-uniform quantization scheme, and 8 is a pruning scheme. DETAILED DESCRIPTION

[0030] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0031] The low-complexity real-time nonlinear compensation method for short-distance optical fiber link system provided by the present invention has been experimentally verified. It has been successfully deployed on a field programmable gate array development board to verify the performance of the low-complexity real-time nonlinear compensation algorithm. It has also successfully transmitted 29.4912Gbit / s PAM4 signals over 25km of single-mode optical fiber. Figure 1As shown, it specifically includes three parts: "nonlinear compensation", "non-uniform quantization" and "pruning":

[0032] (1) “Non-linear compensation” section:

[0033] When the pulse amplitude modulated signal is sent from the transmitter 1, it is transmitted through the optical fiber link 2 to the receiver 3. The received pulse amplitude modulated signal is converted into a digital sequence by the analog-to-digital converter (ADC) at the receiver. The digital sequence is then sent to the hardware platform and distributed to the parallel digital signal processing module according to the filter length. In the digital signal processing module, the linear term of the input signal and the corresponding tap coefficient are calculated, the nonlinear term of the input signal is generated, the nonlinear term and the corresponding tap coefficient are calculated, the output error is calculated, and the tap coefficients corresponding to the linear term and the nonlinear term are updated. The calculation process and coefficient update process are shown in formulas (1)(2)(3) above. N1 and N2 represent the memory length of the linear part and the nonlinear part. Through simulation verification, N1 is selected as 15 and N2 is selected as 5. The coefficient updates of the linear part and the nonlinear part are performed separately, that is, two different iterative compensations are required. Through simulation verification, the iterative step value required for the tap update corresponding to the linear part is selected as 2. -7 , select the iterative step value required for the tap update corresponding to the nonlinear part as 2 -11 The advantage of this selection is that it can save the use of multiplication, because in the hardware description language, the multiplication of the exponent of two can be implemented by arithmetic shift, thereby reducing the use of the precious resource of multipliers.

[0034] (2) “Non-uniform quantization” part:

[0035] In the short-distance optical link system, by sorting out the tap coefficients after convergence, we found that the tap coefficient part corresponding to the linear term is exponentially distributed, and the tap weights at the same position of different power points are relatively stable. Therefore, by quantizing the taps at some positions through non-uniform quantization, the multipliers consumed by updating the taps at this position can be saved. On the FPGA platform, by adopting non-uniform quantization based on the exponential of two, the multipliers consumed by multiplying the input signal and the tap can also be saved, because in the hardware description language, the multiplication of the exponential of two can be realized by arithmetic shift. The quantization formula is shown in formula (4) above. Through simulation verification, the number of quantization bits b is selected as 4, that is, Q u There are 16 quantization levels, which are accurate enough. By non-uniformly quantizing the taps of some linear parts, that is, setting some taps to a fixed value corresponding to the quantization interval and no longer updating them, resources can be released while the performance degradation is acceptable.

[0036] (3) “Pruning” part:

[0037] In the short-distance optical link system, by sorting out the tap coefficients after convergence, we found that the tap coefficients corresponding to the nonlinear term are sparsely distributed, and the tap weights at most locations are very small, which has a very small impact on the final result. Therefore, a threshold value T can be found. This value takes into account the balance between performance and resources. By setting the weights less than the threshold value to zero, the multiplication consumed by tap updates and multiplication of nonlinear terms and taps can be saved. The pruning formula is shown in formula (5) above. The selection of the pruning threshold value T is carried out through simulation. A small initial value of 0.0001 is set for the T value. After convergence, the taps less than this value are set to 0 and are no longer updated or involved in the calculation. The performance loss is judged by the bit error rate of the output signal, and then the T value is continuously increased until a balanced threshold value is found. The final threshold value is set to 0.002.

[0038] In the experiment, the low-complexity nonlinear compensation algorithm was successfully deployed on a programmable gate array platform, and the 29.4912Gbit / s PAM4 signal was successfully transmitted over a 25km single-mode optical fiber. The algorithm was compared and verified with an algorithm that did not deploy the low-complexity solution. The experimental results show that the low-complexity nonlinear compensation algorithm reduces power consumption by 26.2%, reduces the use of multipliers by 75.3%, and the performance degradation is acceptable, while the nonlinear compensation capability is still retained.

[0039] The present invention uses non-uniform quantization and pruning schemes to implement a low-complexity nonlinear compensation technology suitable for hardware platform deployment, effectively solving the implementation difficulty problem caused by the high complexity of nonlinear compensation calculations. The nonlinear compensation technology reduces redundant calculations and replaces multiplication with arithmetic shifts, so the hardware implementation is very friendly, greatly reducing complexity while reducing power consumption. The technology was successfully verified in a 25km single-mode optical fiber transmission experiment of a 29.4912Gbit / s PAM4 signal, and can be applied to receiver modules in the future to bring better receiving capacity and performance.

Claims

1. A real-time nonlinear compensation method for a short-distance optical fiber link system, characterized in that: A nonlinear damage compensation is realized by using a nonlinear compensation algorithm, which is specifically the Volterra algorithm. The algorithm is regarded as a filter that adaptively updates taps, and is divided into a linear term finite impulse response filter calculation module, a nonlinear term finite impulse response filter calculation module, an error calculation module, and a tap coefficient update module. Among them: The sum of the outputs of the linear finite impulse response filter and the nonlinear finite impulse response filter is a complete output linear part and nonlinear part. The calculation expressions of the two calculation modules are as follows: Among them, w l1 (k) and w l1,l2 (k) represents the tap coefficients corresponding to the linear part and the nonlinear part respectively, N1 and N2 represent the memory lengths of the linear part and the nonlinear part, parameter k represents the current time point, y(k) is the output signal at the current moment, x(k) represents the input signal, l1, l2 represent the time delay index of the input signal x(k); x(k-l1) represents the value of the input signal delayed l1 forward at the current moment k; similarly, x(k-l2) represents the value delayed l2 forward; The error calculation module is equipped with a decision maker, and the specific decision is realized by a conditional decision statement, wherein three threshold values ​​of 0.5, 0, and -0.5 are set to make a decision, and the output signal is decided to be -0.75, -0.25, 0.25, and 0.

75. The sum of the outputs of the above two filters is subtracted from the standard constellation point output by the decision maker to obtain the error, and the calculation formula is as follows: e(k)=d(k)-y(k) , (2) d(k) is the standard constellation point output by the decision device, y(k) is the output signal of the above two filters, and e(k) is the error; The tap coefficient update module is used to update the tap values ​​required in the finite impulse response filter calculation module. The required inputs include the filter output and the error calculated by the error calculation module. The calculation expression is as follows: w(k+1)=w(k)+μe(k)x * (k) , (3) w(k) refers to the coefficient before updating, w(k+1) refers to the coefficient after updating, μ is the iteration step, e(k) is the error calculated by the error module, and x(k) is the input signal; The Volterra algorithm is implemented by hardware description language and deployed in a field programmable gate array development board. The field programmable gate array development board is arranged as a hardware platform in an intensity modulation direct detection communication system for real-time processing of signals received by a receiving end. The receiving end converts the received pulse amplitude modulation signal into a digital sequence through an analog-to-digital converter (ADC). Then the digital sequence is sent to the field programmable gate array development board. By distributing the digital sequence to the digital signal processing module deployed in the field programmable gate array development board, the linear term of the input signal and the corresponding tap coefficient are calculated, the nonlinear term of the input signal is generated, and the nonlinear term and the corresponding tap coefficient are calculated in the linear term finite impulse response filter calculation module and the nonlinear term finite impulse response filter calculation module. The error is calculated in the error calculation module and the tap coefficient update module, and the tap coefficients corresponding to the linear term and the nonlinear term are updated. For the specific calculation and update process, please refer to the above formulas (1), (2), and (3). After the Volterra algorithm is implemented on a field programmable gate array platform, it can be equivalent to an equalizer with adaptive tap update and nonlinear compensation capability. The first operation after the equalizer starts working uses the initially set tap value. As the calculation proceeds, the tap coefficient is updated based on the minimum mean square error until the tap coefficient converges to achieve an ideal nonlinear compensation effect.

2. The real-time nonlinear compensation method for a short-distance optical fiber link system according to claim 1, characterized in that: It also includes complexity reduction processing, as follows: In short-distance optical link systems, since the tap coefficients corresponding to the linear terms are exponentially distributed and the tap weights at the same position at different power points are relatively stable, the taps at some positions are quantized by non-uniform quantization to save the multipliers consumed by updating the taps at that position. Therefore, on the field programmable gate array development board, by adopting non-uniform quantization based on the exponent of two, the multiplication of the exponent of two can be realized by arithmetic shift in the hardware description language. The quantization formula is as follows: b is the number of quantization bits. The larger the number of quantization bits, the higher the accuracy. u is the quantitative level; Since the tap coefficients corresponding to the nonlinear part are sparsely distributed, the tap weights at most positions are very small, which has a very small impact on the final result. Therefore, a threshold value T can be found. This value takes into account the balance between performance and resources. By setting the weights less than the threshold value to zero for pruning, the multiplication consumed by tap updates and multiplication of nonlinear terms with taps can be saved. The pruning formula is as follows: W Nonlinear (k)=0,if |W Nonlinear (k)|<T , (5) Among them, W Nonlinear is the tap coefficient corresponding to the nonlinear part, and T is the pruning threshold value. The threshold value cannot be too large, otherwise too much performance will be lost. If it is too small, too few resources will be released. By setting a smaller initial value for T and then performing simulation, the performance loss is judged by the bit error rate. If the performance loss is acceptable, the T value is increased and iterative updates are performed until an acceptable balance point is found, that is, the performance loss is not too much and the released resources are objective.

Citation Information

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