Compensation and calibration circuit for intermediate frequency direct current bias

Abstract

The invention discloses a compensation and calibration circuit for intermediate frequency direct current bias, which belongs to the technical field of radio frequency microwave testing and comprises an IQ mixer, two direct current bias adjustment circuits, two differential amplifiers, a baseband amplifier, an ADC (analog-to-digital converter) and an FPGA (field programmable gate array). The I-path output of the IQ mixer is connected with the positive end of the differential amplifier through a line, the direct current bias adjustment circuit is connected with the negative end of the differential amplifier through a line, and the differential amplifier, the baseband amplifier, the ADC and the FPGA are sequentially connected through lines. The direct-current bias of the output end of the mixer is calibrated and compensated through the direct-current bias result collected by the final output end, the direct-current bias problems caused by various reasons can be systematically compensated and calibrated in a unified mode, and therefore the dynamic range of the zero-intermediate-frequency receiving system is widened.

Description

Technical Field

[0001] The invention belongs to the technical field of radio frequency microwave testing, and in particular relates to a compensation and calibration circuit for intermediate frequency direct current bias. Background Art

[0002] The DC offset of the IF in a zero-IF receiver will degrade the IF signal and affect the effective number of bits of the ADC. In more serious cases, it will cause the amplifier after the demodulator or IQ mixer to saturate or operate in a nonlinear region, deteriorating the indicators of the receiving channel. The main source of DC offset is LO leakage, which appears as an increased DC offset in the I or Q signal path. The reason is that the LO is directly coupled to the RF signal path and is coherently down-converted to the output, resulting in mixer products, which appear as DC offsets.

[0003] The DC offset problem is a key issue in zero-IF receivers. Currently, there are several methods to reduce the DC offset:

[0004] 1. AC coupling method: directly adding DC blocking capacitors in the baseband IF signal path after the IQ mixer can remove DC bias most effectively and simply. However, this method will lead to information loss and is only applicable to baseband signals where signal energy deviates from DC. When a large number of baseband signals are concentrated near DC, the information carried by the signal will be severely lost.

[0005] 2. Digital elimination method: when the local oscillator signal exists but there is no valid signal at the RF input end, the DC offset signal is detected through the baseband acquisition and processing circuit, and the DC offset is directly removed from the result.

[0006] 3. Feedforward elimination method: add an auxiliary channel to the baseband intermediate frequency signal path after the IQ mixer, first suppress the required signal through a low-pass filter, and then amplify the DC bias signal through an amplifier; the main signal and the included DC bias signal are amplified normally; the main signal and the auxiliary signal are subtracted at the output of the amplifier. If the two DC offset signals are amplified by the same multiple, only the required signal will be present after subtraction at the output, thereby eliminating the DC bias.

[0007] 4. The DC negative feedback loop elimination method uses a negative feedback loop connected across the entire baseband link to detect the DC offset component in the final output of the receiver, convert it into a differential current or voltage and subtract it from the input end to adjust the final output. It is necessary to construct an N-channel signal that is opposite to the main M-channel signal, and it is necessary to reasonably control the closed-loop gain and corner frequency, etc.

[0008] The implementation methods of the prior art have the following shortcomings:

[0009] The existing methods for reducing DC offset mainly include AC coupling, digital elimination, feedforward elimination, and negative feedback elimination. The AC coupling method is relatively simple, but it will lose effective signals close to DC; the digital elimination method is also relatively simple, but only digital methods are used to eliminate it. When the actual DC offset is relatively large, it will still saturate the baseband amplifier and ADC at the back end, reducing the dynamic range; the feedforward elimination method circuit is relatively complex and has high requirements for circuit design. It requires the main and auxiliary gains to be the same to effectively eliminate the DC offset, but due to the mismatch of devices in practice, it is difficult to achieve completeness. At the same time, this method can only eliminate the DC offset signal before the input end of the feedforward circuit, and has no effect on the DC offset generated at the back end. The negative feedback elimination method circuit is also relatively complex and has high requirements for circuit design. The range of DC offset elimination depends on the feedback current in the feedback circuit. If the mixer is a passive mixer, it is also necessary to convert the detected output DC offset signal into a differential current, which flows through the resistor connected in series with the mixer output and is converted into a differential voltage again to compensate the mixer output. Summary of the invention

[0010] In view of the above technical problems existing in the prior art, the present invention proposes a compensation and calibration circuit for intermediate frequency DC bias, which has a reasonable design, overcomes the shortcomings of the prior art, and has good effects.

[0011] In order to achieve the above object, the present invention adopts the following technical solution:

[0012] A compensation and calibration circuit for intermediate frequency DC bias comprises an IQ mixer, two DC bias adjustment circuits, two differential amplifiers, a baseband amplifier, an ADC and an FPGA; an I-channel output of the IQ mixer is connected to a positive input terminal of the differential amplifier through a line, a DC bias adjustment circuit is connected to a negative input terminal of the differential amplifier through a line, and the differential amplifier, the baseband amplifier, the ADC and the FPGA are connected in sequence through the line;

[0013] An IQ mixer configured to mix an input signal;

[0014] A DC bias adjustment circuit is configured to compensate and calibrate the intermediate frequency DC bias;

[0015] a differential amplifier configured to convert a single-ended signal into a differential signal;

[0016] a baseband amplifier configured to condition the amplitude;

[0017] an ADC configured to sample the signal;

[0018] The FPGA is configured to perform data processing on the signal.

[0019] Preferably, the two DC bias adjustment circuits are respectively a first DC bias adjustment circuit and a second DC bias adjustment circuit; the first DC bias adjustment circuit includes a resistor R, a resistor Ri, and a first DAC; the second DC bias adjustment circuit includes a resistor R, a resistor Ri, and a second DAC; the resistor R is much larger than Ri; the first DC bias adjustment circuit and the second DC bias adjustment circuit are independent of each other, and the DC bias of the I and Q paths of the IQ mixer can be adjusted individually by adjusting the values ​​of the first DAC and the second DAC.

[0020] In addition, the present invention also provides a compensation and calibration method for intermediate frequency DC bias, which adopts the compensation and calibration circuit for intermediate frequency DC bias as described above, and specifically includes the following steps:

[0021] Step 1: According to the DC bias value collected in the FPGA, the first DAC value of the first DC bias adjustment circuit I is adjusted with a relatively large step;

[0022] Step 2: When the DC bias is adjusted to the minimum, the second DAC value of the Q path of the second DC bias adjustment circuit is adjusted with a relatively large step;

[0023] Step 3: When the DC bias is adjusted to the minimum, the first DAC value of the first DC bias I path is repeatedly adjusted in relatively small steps;

[0024] Step 4: When the DC bias is adjusted to the minimum, the second DAC value of the second DC bias Q path is adjusted in a relatively small step;

[0025] Step 5: Repeat this cycle until the DC bias is minimized.

[0026] Beneficial technical effects brought by the present invention:

[0027] 1. By adding a DC bias adjustment circuit to the negative end of the intermediate frequency differential amplifier of the mixer output I and Q, the DC bias is reliably and effectively reduced, and the dynamic range of the zero intermediate frequency receiving system is improved.

[0028] 2. By designing the resistor R in the DC bias adjustment circuit to be much larger than Ri, the resolution of voltage tuning is effectively improved, the DC component is minimized, the requirements for high-precision DAC are reduced, and the design difficulty and complexity of the DC bias adjustment circuit are effectively reduced.

[0029] 3. The DC bias result collected at the final output end is used to calibrate and compensate the DC bias at the mixer output end. This can systematically compensate and calibrate the DC bias problems caused by various reasons, thereby improving the dynamic range of the zero intermediate frequency receiving system. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The schematic diagram of the compensation and calibration circuit for intermediate frequency DC bias of the present invention is shown in FIG. DETAILED DESCRIPTION

[0031] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0032] The technical solution of the present invention is as follows Figure 1 As shown, the input signal outputs two intermediate frequency signals, IQ, after passing through the passive IQ mixer. Due to the local oscillator leakage problem, the intermediate frequency end has a high DC bias. By adding a corresponding DC bias adjustment circuit at the mixer output end, the intermediate frequency DC bias is compensated and calibrated, which can effectively eliminate the DC bias problem caused by using a passive IQ mixer as a demodulation chip in a zero intermediate frequency receiver.

[0033] like Figure 1 As shown, a compensation and calibration circuit for intermediate frequency DC bias includes an IQ mixer, two DC bias adjustment circuits, two differential amplifiers, a baseband amplifier, an ADC and an FPGA; an I-channel output of the IQ mixer is connected to a positive input terminal of the differential amplifier through a line, a DC bias adjustment circuit is connected to a negative input terminal of the differential amplifier through a line, and the differential amplifier, the baseband amplifier, the ADC and the FPGA are connected in sequence through lines;

[0034] An IQ mixer configured to mix an input signal;

[0035] A DC bias adjustment circuit is configured to compensate and calibrate the intermediate frequency DC bias;

[0036] a differential amplifier configured to convert a single-ended signal into a differential signal;

[0037] a baseband amplifier configured to condition the amplitude;

[0038] an ADC configured to sample the signal;

[0039] The FPGA is configured to perform data processing on the signal.

[0040] The two DC bias adjustment circuits are respectively a first DC bias adjustment circuit and a second DC bias adjustment circuit; the first DC bias adjustment circuit includes a resistor R, a resistor Ri, and a first DAC; the second DC bias adjustment circuit includes a resistor R, a resistor Ri, and a second DAC; the resistor R is much larger than Ri; the first DC bias adjustment circuit and the second DC bias adjustment circuit are independent of each other, and the DC bias of the I and Q paths of the IQ mixer can be adjusted separately by adjusting the values ​​of the first DAC and the second DAC.

[0041] The IQ mixer outputs two intermediate frequency signals, IQ, and uses a differential amplifier to convert the single-ended signal into a differential signal for processing. However, there is a very high intermediate frequency offset at the output of the IQ mixer, which will cause compression of the baseband amplifier and ADC used for amplitude conditioning at the back end. Therefore, a circuit for adjusting the DC bias is added to the output of the mixer to adjust the DC voltage at point A, thereby adjusting the DC bias of the entire system. The IQ mixer is a 50-ohm matching system. The I output is connected to the positive end of the differential amplifier, and the negative end of the differential amplifier is connected to the DC bias adjustment circuit. Ri is the resistance value of 50 ohms and 100 ohms in parallel, which is 33 ohms. The first DAC divides the voltage to the common point of the differential amplifier through the resistor R. The resistor R is much larger than Ri, thereby effectively improving the resolution of the voltage tuning and minimizing the DC component. Moreover, since R is much larger than Ri, the output impedance of the first DAC can be ignored for the differential circuit. At the same time, the first DAC needs to have the ability to adjust the negative output. The Q-channel output uses the same circuit structure as the I-channel. After passing through the DC bias adjustment circuit and the differential amplifier, the four differential signals of I+, I-, Q+, and Q- enter the baseband amplifier for amplitude conditioning, and then enter the ADC sampling and FPGA data processing. When the system is working normally and there is a local oscillator signal, but the RF input signal is not added, due to the influence of local oscillator leakage, the back-end processing circuit will collect the DC bias signal, and alternately adjust the values ​​of the first DAC and the second DAC to reduce the DC bias. Since the DC bias has different responses at different frequencies, the values ​​of the first DAC and the second DAC are different at different frequencies. Therefore, we need to calibrate the DC bias according to the different frequencies. Usually, the calibration software changes the value of the local oscillator frequency in 100MHz steps to calibrate and form a calibration file. In actual use, different values ​​of the first DAC and the second DAC are called according to the frequency value set by the user, so as to realize the compensation and calibration of the DC bias of the entire system.

[0042] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A compensation and calibration circuit for intermediate frequency DC bias, characterized in that: It includes an IQ mixer, two DC bias adjustment circuits, two differential amplifiers, a baseband amplifier, an ADC and an FPGA; an I-channel output of the IQ mixer is connected to a positive input terminal of the differential amplifier through a line, a DC bias adjustment circuit is connected to a negative input terminal of the differential amplifier through a line, and the differential amplifier, the baseband amplifier, the ADC and the FPGA are connected in sequence through lines; An IQ mixer configured to mix an input signal; A DC bias adjustment circuit is configured to compensate and calibrate the intermediate frequency DC bias; a differential amplifier configured to convert a single-ended signal into a differential signal; a baseband amplifier configured to condition the amplitude; an ADC configured to sample the signal; The FPGA is configured to perform data processing on the signal.

2. The compensation and calibration circuit for intermediate frequency DC bias according to claim 1, characterized in that: The two DC bias adjustment circuits are respectively a first DC bias adjustment circuit and a second DC bias adjustment circuit; the first DC bias adjustment circuit and the second DC bias adjustment circuit are independent of each other, and the DC bias of the I and Q paths of the IQ mixer can be adjusted individually by adjusting the values ​​of the first DAC and the second DAC.

3. A compensation and calibration method for intermediate frequency DC bias, characterized in that: The compensation and calibration circuit for intermediate frequency DC bias as claimed in claim 1 specifically comprises the following steps: Step 1: According to the DC bias value collected in the FPGA, the first DAC value of the first DC bias adjustment circuit I is adjusted with a relatively large step; Step 2: When the DC bias is adjusted to the minimum, the second DAC value of the Q path of the second DC bias adjustment circuit is adjusted with a relatively large step; Step 3: When the DC bias is adjusted to the minimum, the first DAC value of the first DC bias I path is repeatedly adjusted in relatively small steps; Step 4: When the DC bias is adjusted to the minimum, the second DAC value of the second DC bias Q path is adjusted in a relatively small step; Step 5: Repeat this adjustment cycle until the DC bias is minimized.

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