Data transmission method based on upper computer communication protocol

Abstract

The invention discloses a data transmission method based on an upper computer communication protocol, and belongs to the technical field of chip testing, and the method specifically comprises the following steps: an upper computer obtains all test items and configuration information of any test machine, packages the test items and configuration information to generate a first write operation packet and sends the first write operation packet to an FPGA on the test machine, the FPGA analyzes the data packet to obtain configuration information and analysis time, and the configuration information and the analysis time are sent to the test machine; testing according to the configuration information to obtain test data and test time; any testing machine is selected, the computing resource consumption of the upper computer in the monitoring period is obtained, a time-varying curve f (t) of the consumption is generated, and a plurality of testing machine sets are determined; and selecting any one test machine set, and acquiring configuration information of all test machines in the set. The upper computer packs the configuration information according to a preset format, generates a second write operation packet and synchronously sends the second write operation packet to the FPGA of the group of test machines, the FPGA analyzes the data packet to obtain the configuration information and test the configuration information to obtain the test data, and the chip test efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a data transmission method based on a host computer communication protocol. Background Art

[0002] ATE (Automatic Test Equipment) is an automatic test equipment. It is a collection of test instruments controlled by high-performance computers. It is a test system composed of a tester and a computer. The computer controls the test hardware by running the instructions of the test program. Semiconductor chip testers are used to detect the integrity of the functions and performance of integrated circuits. They are important equipment to ensure the quality of integrated circuits in the integrated circuit manufacturing process. The most basic requirement of the test system is to ensure the speed, reliability and stability of the test function. Among them, speed is particularly important. How to improve the test speed of chips is a common issue in the semiconductor tester industry.

[0003] In the prior art, during the chip testing process of the ATE system, the chip testing program will use multiple testers to work together, and usually frequently access the data of each FPGA in the tester, including data transmission, register information writing and reading. When the main control board runs the chip testing program, it is necessary to perform parameter reading and writing operations on the registers designed for each FPGA chip of each tester; at the end of the chip test, it is necessary to collect the chip test result data by reading the FPGA register for further analysis and comparison; finally, it is determined whether the chip has passed the test. Repeating the above process to test the next chip will result in very frequent write / read communications between the PC and the tester, resulting in a large amount of time spent on data configuration and reading actions, low communication efficiency, and serious impact on the chip test efficiency. Therefore, a stable host computer communication protocol is needed to ensure the accuracy and real-time performance of the test and improve the chip communication efficiency. Summary of the invention

[0004] The purpose of the present invention is to provide a data transmission method based on a host computer communication protocol to solve the following technical problems: In the prior art, during the chip testing process of the ATE system, the chip testing program will use multiple testers to work together, and usually frequently access the data of each FPGA in the tester, including data transmission, register information writing and reading. When the main control board runs the chip testing program, it is necessary to perform parameter reading and writing operations on the registers designed for each FPGA chip of each tester; at the end of the chip test, it is necessary to collect the chip test result data by reading the FPGA register for further analysis and comparison; finally, it is determined whether the chip has passed the test. Repeating the above process to test the next chip will result in very frequent write / read communications between the PC and the tester, resulting in a large amount of time spent on data configuration and reading actions, low communication efficiency, and serious impact on the chip test efficiency. Therefore, a stable host computer communication protocol is needed to ensure the accuracy and real-time performance of the test and improve the chip communication efficiency.

[0005] The purpose of the present invention can be achieved by the following technical solutions: A data transmission method based on a host computer communication protocol specifically comprises the following steps: S1, obtain all test items and their corresponding configuration information of any test machine, the host computer packages the configuration information according to the preset header information format, generates a first write operation packet and sends it to the FPGA on the test machine, the FPGA receives the first write operation packet and parses it, obtains the configuration information and parsing time tj, performs testing according to the configuration information, obtains test data and test time tc, and obtains the parsing time and test time corresponding to all test machines; S2, select any test machine, and add the analysis time tj and the test time tc corresponding to the test machine to obtain the monitoring period corresponding to the test machine, obtain the computing resource consumption of the host computer in real time during the monitoring period, generate a change curve f(t) of computing resource consumption over time, and obtain the change curve of all test machines; determine a number of test machine groups according to the change curve; S3, select any test group and obtain all configuration information corresponding to the test group, the upper computer packages the configuration information according to the preset header information format, generates a second write operation packet and synchronously sends it to the FPGA on each test machine in the test group, the FPGA on each test machine receives the second write operation packet and parses it to obtain the configuration information, and performs testing according to the configuration information to obtain test data.

[0006] As a further solution of the present invention: in S1, the preset header information format is: The preset header information format is composed of the preamble (PREAMBLE), frame start character (SFD), destination address (DA), source address (SA), user information (INFORMATION) and check frame (FCS) in sequence, among which PREAMBLE is used to synchronize the signals of the host computer and the test machine; SFD is used to mark the beginning of a frame of data to separate the address and sequence information; DA is used to specify the FPGA register address on the test machine; SA is used for the original address sent by the host computer; LENGTH is used to indicate the byte length of the transmitted data; INFORMATION is used to contain the actual transmitted data. If the byte length of the actual transmitted data is between 46 and 1500 bytes, it is the normal mode; if the byte length of the actual transmitted data is between 46 and 9014 bytes, it is the extra-large packet mode; FCS is used to verify the integrity and correctness of the data packet.

[0007] As a further solution of the present invention: it also includes obtaining the byte length of the first write operation packet. If the byte length is less than 60 bytes, a padding byte (PAD) is added after the check frame (FCS) until the byte length of the first write operation packet is equal to 60 bytes.

[0008] As a further solution of the present invention: in S2, the determination process of the test unit is: S11, obtaining the monitoring cycles corresponding to all test machines, and selecting the test machine with the largest monitoring cycle as the target test machine; obtaining the change curve corresponding to the target test machine, taking the starting point of the change curve as the starting point, and evenly determining Y reference time nodes on the change curve at a preset time interval Δt; wherein the starting point is the first time point of the change curve; S12, starting from the first reference time node, calculate the total computing resource consumption of the reference time node , where f i (t) represents the computing resource consumption of the i-th test machine corresponding to the reference time node, t represents the reference time node, and n represents the total number of test machines; If the computing resource consumption C is greater than or equal to Q-ΔQ, the test machine corresponding to the maximum computing resource consumption at the current reference time node is eliminated, and the resource consumption C is recalculated until the resource consumption at the first time node satisfies C less than Q-ΔQ; wherein Q represents the total computing resource consumption of the upper computer, and ΔQ represents the preset computing resource consumption threshold; repeat the above process until the computing resource consumption C of all test machines that have not been eliminated at each reference time node is less than Q-ΔQ, and all test machines that have not been eliminated are classified as a test machine group; S13, obtain all the eliminated test machines, repeat S12, and obtain all the test machine groups.

[0009] As a further solution of the present invention: in S12, if there are two or more test machines whose computing resource consumption is equal and both are maximum values, the monitoring periods of the test machines are obtained, and the test machine with the shortest monitoring period is eliminated; If there is no reference time node e in the change curve corresponding to any test machine, the computing resource consumption corresponding to the reference point e is calibrated to 0 and used as the computing resource consumption corresponding to the test machine at the reference time node e, where e belongs to Y.

[0010] As a further solution of the present invention: in S3, the specific generation process of the second write operation packet is: Obtain the monitoring cycles of all test machines in the test machine group, arrange them in ascending order of the monitoring cycles to obtain a monitoring cycle sequence, sort the configuration information of each test machine according to the monitoring cycle sequence, merge the sorted configuration information into a data packet according to a preset header information format, and obtain a second write operation packet.

[0011] As a further solution of the present invention: S3 also includes receiving a read communication packet from the host computer, the FPGA on the test machine receives the read communication packet and parses it to obtain read information, determines test data based on the read information, packages the test data according to a preset header information format, generates a test data packet and sends it to the host computer.

[0012] As a further solution of the present invention: if the parsing of reading the communication packet fails, the test data packet is set to a specific value 0XAAAA and sent to the host computer.

[0013] Beneficial effects of the present invention: The present invention first obtains the parsing time and test time of any test machine when completing all test items, which is the basis for subsequent analysis. It can be understood that the chip test program will use multiple test machines to work together, and each test machine corresponds to one or more test items. At the same time, each test machine has different test items, so the configuration information corresponding to each test machine is also different. So each test machine will have different parsing time and test time when receiving the corresponding data packet. According to the comprehensive calculation of the parsing time and the test time, the monitoring period of each test machine is obtained, and the computing resource consumption of the host computer during the monitoring period is obtained. It can be understood that after each test item is completed, the host computer will read the test result data on the FPGA register on the test machine for further data analysis, thereby consuming the computing resources of the host computer. When performing data analysis on the test results corresponding to different test machines, different computing resources are consumed, which can be It is understood that the resources of the host computer are limited. If there are projects on multiple test machines that complete the test at the same time and send them to the host computer for data analysis, it may lead to exhaustion of computing resources and further the phenomenon of host computer crash, which greatly affects the chip testing efficiency. If the test data of any test machine is analyzed in turn, it will not only waste computing resources but also lead to low testing efficiency. Therefore, it is necessary to flexibly select a suitable test machine group according to the computing resource consumption curve, and combine the configuration information of the test machine group into a second data packet, and send the second data packet to all test machines in the test machine group for synchronous testing at the same time, avoiding multiple separate transmissions of configuration information to each test machine, which not only reduces the number of visits of the host computer to the test machine FPGA, saves communication time, and improves communication efficiency, but also avoids the phenomenon of resource exhaustion when the host computer performs test data analysis when multiple test machines are tested simultaneously, thereby improving chip testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention will be further described below in conjunction with the accompanying drawings.

[0015] Figure 1 The present invention is a flow chart of a data transmission method based on a host computer communication protocol. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] See also Figure 1 As shown, the present invention is a data transmission method based on a host computer communication protocol, which specifically includes the following steps: S1, obtain all test items and their corresponding configuration information of any test machine, the host computer packages the configuration information according to the preset header information format, generates a first write operation packet and sends it to the FPGA on the test machine, the FPGA receives the first write operation packet and parses it, obtains the configuration information and parsing time tj, performs testing according to the configuration information, obtains test data and test time tc, and obtains the parsing time and test time corresponding to all test machines; S2, select any test machine, and add the analysis time tj and the test time tc corresponding to the test machine to obtain the monitoring period corresponding to the test machine, obtain the computing resource consumption of the host computer in real time during the monitoring period, generate a change curve f(t) of computing resource consumption over time, and obtain the change curve of all test machines; determine a number of test machine groups according to the change curve; S3, select any test group and obtain all configuration information corresponding to the test group, the upper computer packages the configuration information according to the preset header information format, generates a second write operation packet and synchronously sends it to the FPGA on each test machine in the test group, the FPGA on each test machine receives the second write operation packet and parses it to obtain the configuration information, and performs testing according to the configuration information to obtain test data.

[0018] The present invention first obtains the parsing time and test time of any test machine when completing all test items, which is the basis for subsequent analysis. It can be understood that the chip test program will use multiple test machines to work together, and each test machine corresponds to one or more test items. At the same time, each test machine has different test items, so the configuration information corresponding to each test machine is also different. So each test machine will have different parsing time and test time when receiving the corresponding data packet. According to the comprehensive calculation of the parsing time and the test time, the monitoring period of each test machine is obtained, and the computing resource consumption of the host computer during the monitoring period is obtained. It can be understood that the host computer needs to package the configuration information into data packets. This process involves data processing and conversion, which will consume the computing resources of the host computer. At the same time, after each test item is completed, the host computer will read the test result data on the FPGA register on the test machine for further data analysis, further consuming the upper computer. The computing resources of the host computer are used for data analysis of the test results corresponding to different test machines. Different computing resources are consumed. It is understandable that the resources of the host computer are limited. If the projects of multiple test machines complete the test at the same time and send them to the host computer for data analysis, it may lead to the exhaustion of computing resources and further the phenomenon of host computer crash, which greatly affects the chip testing efficiency. If the test data of any test machine is analyzed in turn, it will not only waste computing resources but also lead to low testing efficiency. Therefore, it is necessary to flexibly select the appropriate test machine group according to the computing resource consumption curve, and combine the configuration information of the test machine group into a second data packet, and send the second data packet to all test machines in the test machine group at the same time, which not only reduces the number of visits of the host computer to the test machine FPGA, saves communication time, and improves communication efficiency, but also avoids the phenomenon of resource exhaustion when multiple test machines are testing synchronously, thereby improving chip testing efficiency.

[0019] It is worth noting that in the present invention, the FPGA timing control of the test machine includes comm_clock, which is the main clock for FPGA to collect read and write; o_comm_wr_vaild is the write enable of FPGA, and the write data is valid when it is pulled high; o_comm_address is the FPGA read / write address. Provides real-time address for reading and writing; o_comm_wr_data is the FPGA write data, providing write data; i_comm_wr_busy is the FPGA write busy, and when it is pulled low, the write is valid; o_comm_rd_rdy is the FPGA read preparation, and when it is pulled high, the read address is valid; i_comm_rd_data is the FPGA read data, providing read data; i_comm_wr_rdy is the FPGA write preparation. When it is pulled high, the read data is valid. It can be understood that the FPGA of each test machine is subject to the above timing control. By finely controlling the read and write timing of the FPGA, the accuracy, effectiveness and synchronization of data transmission can be ensured, thereby improving the stability, efficiency and reliability of the system, avoiding incorrect timing conflicts or data loss, and thus improving the chip testing efficiency.

[0020] In a preferred embodiment of the present invention, in S1, the preset header information format is: The preset header information format is composed of the preamble (PREAMBLE), frame start character (SFD), destination address (DA), source address (SA), user information (INFORMATION) and check frame (FCS) in sequence, among which PREAMBLE is used to synchronize the signals of the host computer and the test machine; SFD is used to mark the beginning of a frame of data to separate the address and sequence information; DA is used to specify the FPGA register address on the test machine; SA is used for the original address sent by the host computer; LENGTH is used to indicate the byte length of the transmitted data; INFORMATION is used to contain the actual transmitted data. If the byte length of the actual transmitted data is between 46 and 1500 bytes, it is the normal mode; if the byte length of the actual transmitted data is between 46 and 9014 bytes, it is the extra-large packet mode; FCS is used to verify the integrity and correctness of the data packet.

[0021] In another preferred embodiment of the present invention, it also includes obtaining the byte length of the first write operation packet. If the byte length is less than 60 bytes, a padding byte (PAD) is added after the check frame (FCS) until the byte length of the first write operation packet is equal to 60 bytes.

[0022] The padding bytes make the length of the first write operation packet reach 60 bytes, which helps to ensure that the data packet format meets the requirements of the communication protocol, reduce communication problems caused by small packets or misaligned packets, and optimize the efficiency of hardware processing and network transmission, improving the stability and performance of the entire system.

[0023] In another preferred embodiment of the present invention, in S2, the determination process of the test unit is: S11, obtaining the monitoring cycles corresponding to all test machines, and selecting the test machine with the largest monitoring cycle as the target test machine; obtaining the change curve corresponding to the target test machine, taking the starting point of the change curve as the starting point, and evenly determining Y reference time nodes on the change curve at a preset time interval Δt; wherein the starting point is the first time point of the change curve; S12, starting from the first reference time node, calculate the total computing resource consumption of the reference time node , where f i (t) represents the computing resource consumption of the i-th test machine corresponding to the reference time node, t represents the reference time node, and n represents the total number of test machines; If the computing resource consumption C is greater than or equal to Q-ΔQ, the test machine corresponding to the maximum computing resource consumption at the current reference time node is eliminated, and the resource consumption C is recalculated until the resource consumption at the first time node satisfies C less than Q-ΔQ; wherein Q represents the total computing resource consumption of the upper computer, and ΔQ represents the preset computing resource consumption threshold; repeat the above process until the computing resource consumption C of all test machines that have not been eliminated at each reference time node is less than Q-ΔQ, and all test machines that have not been eliminated are classified as a test machine group; S13, obtain all the eliminated test machines, repeat S12, and obtain all the test machine groups.

[0024] It is understandable that when there are multiple testers performing synchronous testing, according to the barrel effect, the test time of a chip is affected by the maximum monitoring cycle in the tester. Therefore, the tester with the largest monitoring cycle is used as the target tester. Several reference points are determined based on the change curve of the target tester. In fact, this is to ensure that no tester exceeds the expected time during the entire test process.

[0025] In another preferred embodiment of the present invention, in S12, if there are two or more test machines whose computing resource consumption is equal and both are maximum values, the monitoring periods of the test machines are obtained, and the test machine with the shortest monitoring period is eliminated; If there is no reference time node e in the change curve corresponding to any test machine, the computing resource consumption corresponding to the reference point e is calibrated to 0 and used as the computing resource consumption corresponding to the test machine at the reference time node e, where e belongs to Y.

[0026] In another preferred embodiment of the present invention, in S3, the specific generation process of the second write operation packet is: Obtain the monitoring cycles of all test machines in the test machine group, arrange them in ascending order of the monitoring cycles to obtain a monitoring cycle sequence, sort the configuration information of each test machine according to the monitoring cycle sequence, merge the sorted configuration information into a data packet according to a preset header information format, and obtain a second write operation packet.

[0027] In another preferred embodiment of the present invention, S3 also includes receiving a read communication packet from the host computer, the FPGA on the test machine receives the read communication packet and parses it to obtain read information, determines test data based on the read information, packages the test data according to a preset header information format, generates a test data packet and sends it to the host computer.

[0028] In another preferred embodiment of the present invention, if the parsing of reading the communication packet fails, the test data packet is set to a specific value 0XAAAA and sent to the host computer.

[0029] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A data transmission method based on a host computer communication protocol, characterized in that: The specific steps include: S1, obtain all test items and their corresponding configuration information of any test machine, the host computer packages the configuration information according to the preset header information format, generates a first write operation packet and sends it to the FPGA on the test machine, the FPGA receives the first write operation packet and parses it, obtains the configuration information and parsing time tj, performs testing according to the configuration information, obtains test data and test time tc, and obtains the parsing time and test time corresponding to all test machines; S2, select any test machine, and add the analysis time tj and the test time tc corresponding to the test machine to obtain the monitoring period corresponding to the test machine, obtain the computing resource consumption of the host computer in real time during the monitoring period, generate a curve f(t) of computing resource consumption over time, obtain the change curve of all test machines, and determine a number of test machine groups according to the change curve; S3, select any test group and obtain all configuration information corresponding to the test group, the upper computer packages the configuration information according to the preset header information format, generates a second write operation packet and synchronously sends it to the FPGA on each test machine in the test group, the FPGA on each test machine receives the second write operation packet and parses it to obtain the configuration information, and performs testing according to the configuration information to obtain test data.

2. A data transmission method based on a host computer communication protocol according to claim 1, characterized in that: In S1, the preset header information format is: The preset header information format is composed of a preamble, a frame start character, a destination address, a source address, user information and a check frame in sequence, wherein the preamble is used to synchronize the signals of the host computer and the test machine; the frame start character is used to mark the beginning of a frame of data to separate the address and sequence information; the destination address is used to specify the FPGA register address on the test machine; the source address is used for the original address sent by the host computer; the user information is used to contain the actual transmission data. If the byte length of the actual transmission data is between 46 and 1500 bytes, it is a normal mode; if the byte length of the actual transmission data is between 46 and 9014 bytes, it is an extra-large packet mode; the check frame is used to verify the integrity and correctness of the data packet.

3. A data transmission method based on a host computer communication protocol according to claim 2, characterized in that: The method also includes obtaining the byte length of the first write operation packet. If the byte length is less than 60 bytes, padding bytes are added after the check frame until the byte length of the first write operation packet is equal to 60 bytes.

4. A data transmission method based on a host computer communication protocol according to claim 1, characterized in that: In S2, the determination process of the test unit is as follows: S11, obtaining the monitoring cycles corresponding to all test machines, and selecting the test machine with the largest monitoring cycle as the target test machine; obtaining the change curve corresponding to the target test machine, taking the starting point of the change curve as the starting point, and evenly determining Y reference time nodes on the change curve at a preset time interval Δt; wherein the starting point is the first time point of the change curve; S12, starting from the first reference time node, calculate the total computing resource consumption of the reference time node , where f i (t) represents the computing resource consumption of the i-th test machine corresponding to the reference time node, t represents the reference time node, and n represents the total number of test machines; If the computing resource consumption C is greater than or equal to Q-ΔQ, the test machine corresponding to the maximum computing resource consumption at the current reference time node is eliminated, and the resource consumption C is recalculated until the resource consumption at the first time node satisfies C less than Q-ΔQ; wherein Q represents the total computing resource consumption of the host computer, and ΔQ represents the preset computing resource consumption threshold; repeat the above process until the computing resource consumption C of all uneliminated test machines at each reference time node is less than Q-ΔQ, and all uneliminated test machines are classified as a test machine group; S13, obtain all the eliminated test machines, repeat S12, and obtain all the test machine groups.

5. A data transmission method based on a host computer communication protocol according to claim 4, characterized in that: In S12, if there are two or more test machines whose computing resource consumption is equal and both are maximum values, the monitoring periods of the test machines are obtained, and the test machine with the shortest monitoring period is eliminated; If there is no reference time node e in the change curve corresponding to any test machine, the computing resource consumption corresponding to the reference point e is calibrated to 0 and used as the computing resource consumption corresponding to the test machine at the reference time node e, where e belongs to Y.

6. A data transmission method based on a host computer communication protocol according to claim 1, characterized in that: In S3, the specific generation process of the second write operation packet is: Obtain the monitoring cycles of all test machines in the test machine group, arrange them in ascending order of the monitoring cycles to obtain a monitoring cycle sequence, sort the configuration information of each test machine according to the monitoring cycle sequence, merge the sorted configuration information into a data packet according to a preset header information format, and obtain a second write operation packet.

7. A data transmission method based on a host computer communication protocol according to claim 1, characterized in that: The S3 also includes receiving a read communication packet from the host computer. The FPGA on the test machine receives the read communication packet and parses it to obtain read information, determines test data based on the read information, packages the test data according to a preset header information format, generates a test data packet and sends it to the host computer.

8. A data transmission method based on a host computer communication protocol according to claim 7, characterized in that: If the parsing of the communication packet fails, the test data packet is set to a specific value 0XAAAA and sent to the host computer.

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