Preparation method of semiconductor structure, semiconductor structure, device and equipment

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment. The method comprises the following steps: forming a pair of first active structures and a pair of second active structures on two regions of a substrate along a first direction; respectively forming isolation structures on the two regions of the substrate to expose the pair of first active structures; forming a pair of front side transistors based on the pair of first active structures; performing chip reversing and exposing a pair of second active structures; forming a pair of back side transistors based on the pair of second active structures; and after the pair of first active structures and / or the pair of second active structures are exposed, etching the isolation structure in the logic region, so that the height of the active structure in the logic region is higher than that of the active structure in the storage region. Different heights of active structures of the logic area and the storage area can be achieved, and the requirements of different areas of a chip for transistor properties are met.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Flip-chip stacked transistors (stacked transistors) further improve the integration density of transistors by integrating two layers of transistors in a vertical space, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In the related art, a logic part (e.g., logic transistors) and a storage part (e.g., static random-access memory (SRAM)) can be integrated into a single chip. However, the internal structures of the logic part or the storage part within the same chip are the same, which cannot meet the requirements of different properties of transistors in different areas of the chip. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus, which can realize different heights of active structures in a logic area and a storage area, and is beneficial to the requirements of transistor properties in different areas of a chip.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising: forming a pair of first semiconductor structures on two regions along a first direction on a substrate, the pair of first semiconductor structures comprising at least a pair of first active structures and a pair of second active structures, the pair of first active structures being away from the substrate relative to the pair of second active structures, and the two regions comprising a logic region and a storage region; forming isolation structures on the two regions of the substrate respectively to expose the pair of first active structures; forming a pair of front transistors based on the pair of first active structures, the pair of front transistors comprising a first front transistor located in the logic region and a second front transistor located in the storage region; flipping the pair of front transistors and exposing a pair of second active structures; forming a pair of back transistors based on the pair of second active structures, the pair of back transistors comprising a first back transistor located in the logic region and a second back transistor located in the storage region; after exposing the pair of first active structures and / or the pair of second active structures, etching the isolation structure located in the logic region so that the height of the active structure located in the logic region is higher than the height of the active structure located in the storage region.

[0006] In one possible embodiment, after exposing a pair of first active structures, etching the isolation structure located in the logic area includes: forming a first mask on the isolation structure and the first active structure located in the storage area; etching the isolation structure based on the first mask so that the height of the first active structure located in the logic area is higher than the height of the first active structure located in the storage area; forming a pair of front transistors based on the pair of first active structures, including: forming a first front transistor based on the first active structure located in the logic area, and forming a second front transistor based on the first active structure located in the storage area.

[0007] In one possible embodiment, exposing a pair of second active structures includes: removing the substrate; thinning the isolation structure to a preset height to expose the pair of second active structures; after exposing the pair of second active structures, etching the isolation structure located in the logic area, including: forming a second mask on the retained isolation structure and the second active structure located in the storage area; based on the second mask, etching the retained isolation structure to a preset height so that the height of the second active structure located in the logic area is higher than the height of the second active structure in the storage area; based on the pair of second active structures, forming a pair of back transistors, including: forming a first back transistor based on the second active structure located in the logic area, and forming a second back transistor based on the second active structure located in the storage area.

[0008] In one possible embodiment, the method further includes: when an SRAM is formed between a first front transistor and a first back transistor and the first front transistor is an N-type transistor, after exposing a pair of first active structures, etching an isolation structure located within the storage area so that a height of the first active structure located within the storage area is higher than a height of the second active structure located within the storage area.

[0009] In one possible embodiment, after exposing a pair of first active structures, etching the isolation structure located in the storage area includes: forming a third mask on the isolation structure located in the logic area and the first active structure; etching the isolation structure based on the third mask so that the height of the exposed first active structure located in the storage area is higher than the height of the first active structure located in the logic area; exposing a pair of second active structures includes: removing the substrate; thinning the isolation structure to a preset height to expose the pair of second active structures, wherein the height of the second active structure located in the storage area is lower than the height of the first active structure located in the storage area.

[0010] In one possible embodiment, a pair of first semiconductor structures are formed on two regions of a substrate along a first direction, including: providing a substrate; forming a first material layer and a second material layer on the substrate along the first direction; etching the second material layer, the first material layer and a portion of the substrate to form a pair of first semiconductor structures, the second material layer after etching is a first active structure, the portion of the substrate after etching is a second active structure, and the first material layer after etching is an isolation layer, which is used to isolate the first active structure from the second active structure.

[0011] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is manufactured using the preparation method described in the first aspect and any one of the embodiments thereof, and includes: a pair of front transistors and a pair of back transistors, the pair of front transistors including a first front transistor located in a logic area and a second front transistor located in a storage area, and a pair of back transistors including a first back transistor located in the logic area and a second back transistor located in the storage area; wherein the height of the active structure located in the logic area is higher than the height of the active structure located in the storage area.

[0012] In a possible implementation, when the first front transistor and the first back transistor form an SRAM and the first front transistor is an N-type transistor, a height of the first active structure located in the storage region is higher than a height of the second active structure located in the storage region.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the second aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, a pair of first active structures and a pair of second active structures are formed on two regions of the substrate along a first direction; isolation structures are formed on two regions of the substrate to expose a pair of first active structures; a pair of front transistors are formed based on the pair of first active structures; the chip is flipped and a pair of second active structures are exposed; a pair of back transistors are formed based on the pair of second active structures; after exposing the pair of first active structures and / or the pair of second active structures, the isolation structure located in the logic region is etched so that the height of the active structure located in the logic region is higher than the height of the active structure located in the storage region. Therefore, the present application can prepare logic transistors and SRAM on two regions of the substrate at the same time, and can realize different heights of active structures in logic transistors and SRAM, which is beneficial to the requirements of transistor properties in different regions of the chip.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0019] Figure 2 A schematic top view of a semiconductor structure in an embodiment of the present application;

[0020] Figures 3 to 8 This is a schematic diagram of the structure of the semiconductor structure in the first preparation process in an embodiment of the present application;

[0021] Fig. 9 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application;

[0022] Fig.10 A schematic top view of a semiconductor structure in a logic area or a storage area in an embodiment of the present application;

[0023] Fig.11 This is a schematic diagram of the second structure of the semiconductor structure in the embodiment of the present application.

[0024] The above pictures:

[0025] 10. Front transistor located in the storage area; 11. Front transistor located in the logic area; 101. First fin structure located in the storage area; 111. First fin structure located in the logic area; 112. First source-drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 115. First source-drain metal; 116. First metal interconnect layer; 12. Back transistor located in the logic area; 121. Second fin structure located in the logic area; 122. Second source-drain structure; 123. Second interlayer dielectric layer; 124. Second gate structure; 125. Second source-drain metal; 126. Second metal interconnect layer; 13. Back transistor located in the storage area; 131. Second fin structure located in the storage area; 20. Substrate; 21. First isolation structure; 22. First sidewall; 23. Insulation layer; 24. Carrier wafer; 25. Mask; 26. Second isolation structure; 27. Second sidewall; 28. MDI layer / BOX layer. DETAILED DESCRIPTION

[0026] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0027] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0028] With the continuous development of transistor technology, flip-chip stacking technology has come into being. Flip-chip stacking transistors take into account the consistency, defect density, alignment and thermal budget of the active areas of the upper and lower transistors. This solution solves the long-standing problems of the existing mainstream technical solutions for stacked transistors, such as complex processes, fixed polarity (monolithic solution), difficult alignment, and high defect density of upper semiconductor materials (sequential solution), thereby promoting the industrialization of transistor stacking technology.

[0029] Currently, logic transistors and SRAM can be integrated into the same chip. However, the internal structure of the logic part or the storage part within the same chip is the same, which cannot meet the different properties of transistors in different areas of the chip.

[0030] Based on this, an embodiment of the present application provides a method for preparing a semiconductor structure, which can achieve different heights of active structures of logic transistors and SRAM based on the formation method of flip-chip stacked transistors, which is beneficial to the requirements of transistor properties in different areas of the chip.

[0031] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as processors and logic devices.

[0032] In some embodiments, the semiconductor structure may include a pair of front-side transistors and a pair of back-side transistors, the pair of front-side transistors including a first front-side transistor located in a logic region and a second front-side transistor located in a storage region, and the pair of back-side transistors including a first back-side transistor located in the logic region and a second back-side transistor located in the storage region; wherein a height of the first active structure located in the logic region is higher than a height of the first active structure located in the storage region, and / or a height of the second active structure located in the logic region is higher than a height of the second active structure located in the storage region.

[0033] In some embodiments, when the first front transistor and the first back transistor form an SRAM and the first front transistor is an N-type transistor, a height of the first active structure located in the storage region is higher than a height of the second active structure located in the storage region.

[0034] In some embodiments, the type of transistor may be, for example, a fin field effect transistor (FinFET).

[0035] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application. Figure 1 As shown, the method for preparing the semiconductor structure in the embodiment of the present application may include:

[0036] Step S110: forming a pair of first semiconductor structures on two regions of the substrate along a first direction.

[0037] In some embodiments, the pair of first semiconductor structures at least includes a pair of first active structures and a pair of second active structures, the pair of first active structures are farther away from the substrate than the pair of second active structures, and the two regions include a logic region and a storage region.

[0038] It can be understood that the embodiment of the present application forms two first semiconductor structures in different regions (logic region and storage region) of the substrate, and then subsequently forms logic transistors and SRAMs based on the two first semiconductor structures, respectively. The first direction is a direction perpendicular to the growth direction of the substrate.

[0039] In one embodiment, when the first semiconductor structure only includes active structures (first active structure and second active structure), the substrate may be a silicon substrate. It is understandable that the substrate may also be made of other semiconductor materials, which is not limited in the present embodiment.

[0040] In one embodiment, when the first semiconductor structure includes a first active structure, a second active structure, and an isolation layer between the first active structure and the second active structure, the substrate may be a silicon-on-insulator (SOI) substrate.

[0041] In one embodiment, the SOI substrate includes a three-layer structure: a thin top silicon layer, a buried oxide (BOX) layer, and a supporting bottom silicon wafer (base silicon) layer. That is, a buried oxide (BOX) layer is provided between the top silicon layer and the back silicon substrate, and the BOX layer is subsequently used as an isolation layer between the first active structure and the second active structure. Then, the SOI substrate can realize the dielectric isolation of components in the integrated circuit and eliminate the parasitic latch effect in the bulk silicon CMOS circuit. The integrated circuit prepared by using the SOI substrate also has the advantages of small parasitic capacitance, high integration density, fast speed, simple process, small short channel effect and is particularly suitable for low-voltage and low-power circuits.

[0042] After providing the substrate, a portion of the substrate may be etched to form a plurality of active structures standing upright on the substrate. In one example, the substrate may be anisotropically etched to obtain an active structure, the active structure comprising a first active structure away from the substrate and a second active structure close to the substrate. The etching process may be, for example, at least one of dry etching, wet etching, reactive ion etching, and chemical oxide removal process, which is not specifically limited in the embodiments of the present application.

[0043] In addition, in the case where the first semiconductor structure includes a first active structure, a second active structure, and an isolation layer located between the first active structure and the second active structure, the implementation process of step S110 can be: providing a substrate; forming a first material layer and a second material layer on the substrate along a first direction; etching the second material layer, the first material layer and a portion of the substrate to form a pair of first semiconductor structures, wherein the second material layer after etching is the first active structure, the portion of the substrate after etching is the second active structure, and the first material layer after etching is a sacrificial layer.

[0044] In one embodiment, a silicon germanium (SiGe) material layer may be epitaxially grown on the original silicon substrate, and then an epitaxial silicon material layer may be epitaxially grown. After etching, the epitaxial silicon material layer above the silicon germanium material layer serves as a device layer of the front transistor, and the original silicon material layer below the silicon germanium material layer serves as a device layer of the back transistor, while the silicon germanium material layer is a sacrificial layer, and an isolation layer may be formed after subsequent etching. This will be described later and will not be described in detail here.

[0045] Step S120: forming isolation structures on two regions of the substrate respectively to expose a pair of first active structures.

[0046] It is understandable that after the active structure is formed, an insulating material may be deposited on the substrate and the active structure to form an isolation structure that wraps the pair of second active structures. In this case, the isolation structure located in the logic area and the isolation structure located in the storage area have the same height, and the isolation structure has a higher height and can also wrap a portion of the pair of first active structures.

[0047] For example, the isolation structure may also be referred to as a shallow trench isolation (STI) structure. The insulating material forming the isolation structure may be, for example, silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO).

[0048] In some embodiments, in order to facilitate subsequent processing, after the isolation structure is formed, the isolation structure can be polished or chemical-mechanical planarization (CMP) is performed, so that when the isolation structure is subsequently etched, different areas of the isolation structure have the same etching depth, thereby making the top height of the exposed active structure the same.

[0049] Step S130: forming a pair of front transistors based on a pair of first active structures.

[0050] In some embodiments, the pair of front transistors includes a first front transistor located in the logic region and a second front transistor located in the storage region. The implementation process of step S130 may be: forming the first front transistor based on the first active structure located in the logic region, and forming the second front transistor based on the first active structure located in the storage region.

[0051] It can be understood that after the first active structure in the logic area and the storage area is exposed, the front device of the logic transistor and the front device of the SRAM can be formed simultaneously based on the exposed first active structure. Since the operations of forming the front device of the logic transistor and the front device of the SRAM are the same, the following is explained by taking the formation of a front transistor as an example.

[0052] In some embodiments, the implementation process of step S130 may be: epitaxially growing a first source-drain structure on the first active structure; forming a first gate structure based on the first active structure; and depositing a metal material on the first source-drain structure to form a first source-drain metal.

[0053] It is understandable that after forming the isolation structure, a semiconductor material may be deposited in the gate region of the semiconductor structure to form a first dummy gate structure; a first spacer is formed on both sides of the first dummy gate structure; and a first source-drain structure is formed on the first active structure on both sides of the first dummy gate structure and the first spacer. The first spacer is used to isolate the first source-drain structure from the first gate structure, and the structure of the first spacer may be set according to actual needs, and the embodiment of the present application does not specifically limit this.

[0054] In some embodiments, the semiconductor material forming the first dummy gate structure may be polysilicon (Poly Si), amorphous silicon, etc. For example, the first spacer may have a single layer structure, and the entire structure may be made of the same material, such as porous silicon carbon oxyhydride (SiCOH).

[0055] In the case of forming the sacrificial layer as mentioned above, after forming the first dummy gate structure, the sacrificial layer between the first active structure and the second active structure can be selectively removed to form a first groove. Then, a dielectric material is filled in the first groove to form an isolation layer. Since the first dummy gate structure can provide structural support to the first active structure during the selective removal process, the position of the first active structure in the front transistor does not change, and the first active structure and the second active structure remain self-aligned. Among them, the dielectric material can be, for example, a lowK material. The isolation layer can achieve electrical isolation between the front transistor and the back transistor by isolating the first active structure and the second active structure.

[0056] In some embodiments, the implementation process of forming the first source-drain structure on the first dummy gate structure and the first active structure on both sides of the first sidewall may be: etching the first active structure of the front transistor in the source-drain region to form a first source-drain groove, performing source-drain epitaxial growth at the first source-drain groove to form the first source-drain structure.

[0057] It is understandable that strained materials such as silicon germanium or silicon carbide can be formed in the source and drain grooves by selective epitaxial growth to fill the source and drain grooves of the front transistor, and then a first source and drain structure is formed on the strained material by a heavy doping process.

[0058] In some embodiments, ion implantation may also be performed on a portion of the first active structure on both sides of the first pseudo-gate structure and the first sidewall to form a first source-drain structure. Here, the implanted ions may include N-type ions or P-type ions, for example, nitrogen ions, phosphorus ions, arsenic ions, etc. When the implanted ions are N-type ions, the front transistor is an N-type transistor, and when the implanted ions are P-type ions, the front transistor is a P-type transistor.

[0059] In some embodiments, after the first source-drain structure is formed, an interlayer dielectric may be deposited on the first source-drain structure to form a first interlayer dielectric layer.

[0060] For example, an insulating material (such as silicon dioxide) may be deposited on the first source-drain structure and the first active structure and planarized to form a first interlayer dielectric layer, and the first interlayer dielectric layer may cover the first source-drain structure and the first active structure.

[0061] After the first source-drain structure is formed, a gate structure of the front transistor, that is, a first gate structure, may be formed.

[0062] In some embodiments, the first dummy gate structure formed above can be removed by an etching process to obtain a gate groove, an insulating material can be deposited at the gate groove to form a first gate dielectric layer, and a metal material can be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute a first gate structure.

[0063] For example, the first gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. For example, the first gate electrode layer can be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and aluminum carbide).

[0064] After forming the first gate structure, a metal material may be deposited on the first source-drain structure formed above to form a first source-drain metal.

[0065] In some embodiments, when the first interlayer dielectric layer is formed after the first source-drain structure is formed, a portion of the first interlayer dielectric layer can be etched to expose the first source-drain structure, and a metal material is filled on the first source-drain structure to form a first source-drain metal.

[0066] For ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the first source-drain metal, the first source-drain groove, the second source-drain structure, the second source-drain metal, the second source-drain groove, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0067] In addition, in some embodiments, after the front transistor is prepared, a first metal interconnection layer may be formed on the front transistor.

[0068] It is understood that the first metal interconnect layer can be formed by performing back-end processes (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.) on the front transistor. The first metal interconnect layer can include at least one interconnect dielectric layer and an interconnect metal structure located in the interconnect dielectric layer.

[0069] It should be noted that the first source-drain structure, the first interlayer dielectric layer, the first gate structure, the first source-drain metal and the first metal interconnection layer can all be formed by standard steps of the semiconductor manufacturing process, and the embodiments of the present application do not specifically limit this.

[0070] Step S140: flipping a pair of front-side transistors and exposing a pair of second active structures.

[0071] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the first metal interconnect layer formed above to form an insulating layer, and the insulating layer is bonded to a carrier wafer. Subsequently, a pair of front-side transistors are flipped over and the substrate is placed on top.

[0072] In some embodiments, the implementation process of exposing the second active structure in step S140 may be: removing the substrate; thinning the isolation structure to a preset height to expose a pair of second active structures, and the thinned isolation structure is used to isolate the CMOS transistor and the memory cell. In this case, in the case where the isolation structure located in the logic area is not etched, the height of the isolation structure located in the logic area and the isolation structure located in the memory area are the same. Here, the height of the etched structure can be set to be smaller, so that the height of the exposed second active structure is smaller.

[0073] In one example, after flipping, the substrate may be removed by polishing or chemical mechanical planarization.

[0074] It can be understood that after removing the substrate, the top of the second active structure is flush with the top of the isolation structure, so the isolation structure can be thinned to a preset height to expose the side of the second active structure so that a back transistor can be formed subsequently based on the second active structure exposed on the side.

[0075] Step S150: forming a pair of back-side transistors based on a pair of second active structures.

[0076] In some embodiments, the pair of back side transistors includes a first back side transistor located in the logic region and a second back side transistor located in the storage region. The implementation process of step S130 may be: forming the first back side transistor based on the second active structure located in the logic region, and forming the second back side transistor based on the second active structure located in the storage region.

[0077] It can be understood that after the second active structures in the logic region and the storage region are exposed, the back side devices of the logic transistor and the back side devices of the SRAM can be formed simultaneously based on the exposed second active structures. Since the operations of forming the back side devices of the logic transistor and the back side devices of the SRAM are the same, the following description will be made by taking the formation of a back side transistor as an example.

[0078] In some embodiments, the implementation process of step S150 may be: epitaxially growing a second source-drain structure on the second active structure; forming a second gate structure based on the second active structure; and depositing a metal material on the second source-drain structure to form a second source-drain metal.

[0079] It can be understood that after the isolation structure is formed, semiconductor material can also be deposited in the gate region of the semiconductor structure to form a second dummy gate structure; a second spacer is formed on both sides of the second dummy gate structure; and a second source-drain structure is formed on the second active structure on both sides of the second dummy gate structure and the second spacer.

[0080] It is understandable that strained materials such as silicon germanium or silicon carbide can be formed in the source and drain grooves by selective epitaxial growth to fill the source and drain grooves of the back transistor, and then a second source and drain structure is formed on the strained material by a heavy doping process.

[0081] In some embodiments, ion implantation may also be performed on a portion of the second active structure on both sides of the second pseudo-gate structure and the second sidewall to form a second source-drain structure. Here, the implanted ions may include N-type ions or P-type ions, for example, nitrogen ions, phosphorus ions, arsenic ions, etc. When the implanted ions are N-type ions, the back transistor is an N-type transistor, and when the implanted ions are P-type ions, the back transistor is a P-type transistor.

[0082] In some embodiments, after the second source-drain structure is formed, an interlayer dielectric may be deposited on the second source-drain structure to form a second interlayer dielectric layer.

[0083] After the second source-drain structure is formed, a gate structure of the back transistor, that is, a second gate structure, may be formed.

[0084] In some embodiments, the second dummy gate structure formed above can be removed by an etching process to obtain a gate groove, an insulating material can be deposited at the gate groove to form a second gate dielectric layer, and a metal material can be deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute a second gate structure.

[0085] After forming the second gate structure, a metal material may be deposited on the second source-drain structure formed above to form a second source-drain metal.

[0086] In some embodiments, when a second interlayer dielectric layer is formed after forming the second source-drain structure, a portion of the second interlayer dielectric layer can be etched to expose the second source-drain structure, and a metal material is filled on the second source-drain structure to form a second source-drain metal.

[0087] In addition, in some embodiments, after the back side transistor is prepared, a second metal interconnection layer may be formed on the back side transistor.

[0088] It is understood that a second metal interconnect layer can be formed by performing back-end processes (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.) on the back transistor. The second metal interconnect layer can include at least one interconnect dielectric layer and an interconnect metal structure located in the interconnect dielectric layer.

[0089] It should be noted that the second source-drain structure, the second interlayer dielectric layer, the second gate structure, the second source-drain metal and the second metal interconnect layer can all be formed by standard steps of the semiconductor manufacturing process, and the embodiments of the present application do not specifically limit this.

[0090] Step S160: after exposing the pair of first active structures and / or the pair of second active structures, etching the isolation structure in the logic region so that the height of the active structure in the logic region is higher than the height of the active structure in the storage region.

[0091] The following first introduces a scheme for etching active structures in the logic area on the front side.

[0092] In some embodiments, after exposing the pair of first active structures, the isolation structure located in the logic region may be etched so that a height of the first active structure located in the logic region is higher than a height of the first active structure located in the memory region.

[0093] In some embodiments, the implementation process of etching the isolation structure located in the logic area may be: forming a first mask on the isolation structure located in the storage area and the first active structure; based on the first mask, etching the isolation structure to a preset height so that the height of the first active structure located in the logic area is higher than the height of the first active structure located in the storage area.

[0094] It can be understood that a first mask is first formed above the storage area. After the first mask is formed, the isolation structure is etched based on the first mask. Since the isolation structure located in the storage area is covered by the first mask, only a portion of the isolation structure located in the logic area is etched away. Since the isolation structure wraps a portion of the active structure, after a portion of the isolation structure located in the logic area is etched away, the first active structure wrapped by this portion of the isolation structure will be exposed. In this way, the height of the first active structure located in the logic area will be higher than the height of the first active structure located in the storage area.

[0095] In addition, in the case of etching the isolation structure located in the logic area, the first mask can be removed first in step S130, and then the first front transistor is formed based on the first active structure located in the logic area, and the second front transistor is formed based on the first active structure located in the storage area. Since the height of the first active structure located in the logic area is higher than the height of the first active structure located in the storage area, in the first gate structure of the front transistor formed based on the first active structure, the height of the first gate structure located in the logic area is also higher than the height of the first gate structure located in the storage area. Therefore, the present application can increase the height of the active structure located in the logic area by etching the isolation structure located in the logic area, so that the finally formed logic transistor has a larger effective gate width (effective channel width, Weff). Moreover, the height of the active structure located in the storage area is lower than the height of the active structure located in the logic area, that is, the height of the active structure located in the storage area is smaller, so that the finally formed SRAM can achieve the effect of low leakage and high noise tolerance. Therefore, the embodiment of the present application can achieve different heights of the active structures in the logic area and the storage area by etching the isolation structure located in the logic area, which is beneficial to the requirements of transistor properties in different areas of the chip.

[0096] The following is a scheme for etching active structures in the logic area on the back side.

[0097] In some embodiments, after exposing the pair of second active structures, the isolation structure located in the logic region may be etched so that a height of the second active structure located in the logic region is higher than a height of the second active structure located in the memory region.

[0098] In some embodiments, the implementation process of etching the isolation structure located in the logic area may be: forming a second mask on the retained isolation structure and the second active structure located in the storage area; based on the second mask, etching the retained isolation structure to a preset height so that the height of the second active structure located in the logic area is higher than the height of the second active structure located in the storage area.

[0099] It can be understood that, first, a second mask is formed above the storage area. After the second mask is formed, the reserved isolation structure is etched based on the second mask. Since the reserved isolation structure located in the storage area is covered by the second mask, only a portion of the reserved isolation structure located in the logic area is etched away. Since the reserved isolation structure wraps a portion of the active structure, after a portion of the reserved isolation structure located in the logic area is etched away, the second active structure wrapped by this portion of the isolation structure will be exposed. In this way, the height of the second active structure located in the logic area will be higher than the height of the second active structure located in the storage area.

[0100] Since the height of the second active structure located in the logic area is higher than the height of the second active structure located in the storage area, in the second gate structure of the front transistor formed based on the second active structure, the height of the second gate structure located in the logic area is also higher than the height of the second gate structure located in the storage area. Therefore, the present application can increase the height of the active structure located in the logic area by etching the isolation structure located in the logic area, so that the finally formed logic transistor has a larger effective gate width. Moreover, the height of the active structure located in the storage area is lower than the height of the active structure located in the logic area, that is, the height of the active structure located in the storage area is smaller, so that the finally formed SRAM can achieve the effects of low leakage and high noise tolerance. Therefore, the embodiment of the present application can achieve different heights of the active structures in the logic area and the storage area by etching the isolation structure located in the logic area, which is beneficial to the requirements of transistor properties in different areas of the chip.

[0101] The above is to etch the isolation structure located in the logic area on the front or back side alone, so that the height of the active structure located in the logic area is higher than the height of the active structure located in the storage area. In some embodiments, the isolation structure located in the logic area can also be etched on both the front and back sides, which is not limited in the embodiments of the present application.

[0102] In addition, in some embodiments, when the first front transistor and the first back transistor form an SRAM and the first front transistor is an N-type transistor, after exposing a pair of first active structures, the isolation structure located in the storage area is etched so that the height of the first active structure located in the storage area is higher than the height of the second active structure located in the storage area.

[0103] In some embodiments, after exposing a pair of first active structures, a third mask can be formed on the isolation structure and the first active structure located in the logic region; based on the third mask, the isolation structure is etched so that the height of the first active structure located in the storage region is higher than the height of the first active structure located in the logic region.

[0104] That is, the embodiment of the present application does not etch the isolation structure located in the logic area, but etches the isolation structure located on the side of the N-type transistor in the storage area, so that the height of the active structure on the side of the N-type transistor is higher than the height of the active structure of the P-type transistor.

[0105] It can be understood that when the height of the isolation structure located in the logic area and the isolation structure located in the storage area are the same in step S120, a third mask can be formed above the logic area, and then based on the third mask, the isolation structure is etched to a preset height, and a first front transistor (N-type transistor) is formed based on the exposed first active structure. After flipping the wafer, the height of the etched isolation structure is smaller so that the exposed second active structure is lower than the first active structure, and then a first back transistor (P-type transistor) is formed based on the second active structure. The height of the active structure on the N-type transistor side of the SRAM formed in this way is higher than the height of the active structure of the P-type transistor.

[0106] In SRAM devices, P-type transistors are usually used as pull-up (PU) tubes, while N-type transistors are used as pull-down (PD) tubes and access (PG) tubes. In the read operation of SRAM, the signal needs to be read by relying on the voltage signal difference of the two bit lines. When the stored data is read, the precharge operation makes the voltage of the two bit lines equal, and then the current is allowed to flow by turning on the corresponding access tube, thereby changing the voltage of the bit line. In this process, the P-type transistor acts as a pull-up tube, and its role is to keep the voltage of the unselected bit line stable and provide current to replenish the charge when needed. However, if the driving capability of the P-type transistor is too strong, it may generate unnecessary current during the processing, increase power consumption, and may affect the accuracy of the reading. In contrast, in the read operation, the N-type transistor acts as a pull-down tube, and the voltage of the bit line needs to be quickly pulled down to generate a sufficient voltage difference to read the data. Therefore, the N-type transistor usually needs to have a stronger driving capability to ensure the reading speed. In the write operation, the N-type transistor also acts as one of the access tubes, responsible for writing data into the SRAM cell. Therefore, from a performance perspective, N-type transistors need to have sufficient driving capability and response speed to ensure that data is written correctly. In addition, from the perspective of SRAM stability and power consumption, P-type transistors with weaker driving capability mean that less current is required to maintain voltage stability, which helps reduce power consumption. At the same time, P-type transistors with weaker driving capability can also reduce the noise and interference generated during the reading and writing process, thereby improving the stability of SRAM.

[0107] The smaller the height of the active structure of the transistor, the weaker the driving ability of the transistor. For non-flip-chip stacked devices, the distance between the P-type transistor and the N-type transistor inside an SRAM is relatively close, and it is impossible to selectively etch the isolation structure of a certain transistor to change the height of its active structure. However, for flip-chip stacked devices, the P-type transistor and the N-type transistor inside the SRAM are flipped and arranged on different sides. Therefore, the embodiment of the present application can etch the isolation structure on one side of the N-type transistor so that the height of the active structure on the side of the N-type transistor is higher than the height of the active structure of the P-type transistor, thereby helping to improve the performance of the SRAM device.

[0108] The above description is based on the N-type transistor on the front side. Similarly, when the N-type transistor is on the back side, the isolation structure located in the storage area can also be etched to make the height of the active structure on one side of the N-type transistor higher than the height of the active structure of the P-type transistor. It will not be repeated here.

[0109] In addition, the embodiment of the present application can also etch the isolation structure in the logic area and the isolation structure in the storage area at the same time. In this case, when the transistor on one side of the storage area is an N-type transistor, the isolation structure in the storage area on one side and the isolation structure in the logic area can be etched at the same time, and the isolation structure in the logic area can be etched again on the other side. In this way, the height of the active structure in the logic area can be higher than the height of the active structure in the storage area, and the height of the active structure on the side of the N-type transistor in the storage area is higher than the height of the active structure of the P-type transistor. This can better meet the requirements of different regions for transistor performance.

[0110] In the present application, a pair of first active structures and a pair of second active structures are formed on two regions of the substrate along a first direction; isolation structures are formed on two regions of the substrate to expose a pair of first active structures; a pair of front transistors are formed based on the pair of first active structures; the wafer is flipped and a pair of second active structures are exposed; a pair of back transistors are formed based on the pair of second active structures; wherein, after exposing the pair of first active structures and / or the pair of second active structures, the isolation structure located in the logic region is etched so that the height of the active structure located in the logic region is higher than the height of the active structure located in the storage region. Therefore, the present application can prepare logic transistors and SRAM on two regions of the substrate at the same time, and can realize different heights of active structures in logic transistors and SRAM, which is beneficial to the requirements of transistor properties in different regions of the chip.

[0111] Furthermore, the embodiment of the present application can also etch the isolation structure on one side of the N-type transistor located in the storage area so that the height of the active structure of the N-type transistor located in the storage area is higher than the height of the source structure of the P-type transistor located in the storage area, so as to improve the performance of the SRAM device while reducing power consumption.

[0112] The following describes the first method for preparing the semiconductor structure provided in the embodiment of the present application, taking the active structure as a fin structure as an example, that is, etching the structure in the logic area on the back side so that the height of the active structure of the front transistor in the logic area is smaller than the height of the active structure of the back transistor. Figure 2 This is a schematic top view of the semiconductor structure in the embodiment of the present application. It should be noted that, for ease of understanding, only the active structure, gate structure and source-drain structure are shown in the top view. The AA' direction is the direction of the cross section of the logic region of the semiconductor structure along the gate structure; the BB' direction is the direction of the cross section of the logic region of the semiconductor structure along the source-drain structure; and the CC' direction is the direction of the cross section of the semiconductor structure along the active structure.

[0113] Figures 3 to 8 This is a schematic diagram of the structure of the semiconductor structure of an embodiment of the present application during the first preparation process. Fig. 9 This is a schematic diagram of the first structure of the semiconductor structure of the embodiment of the present application. Figures 3 to 9 (a) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., the AA' direction), Figures 3 to 9 (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction), Figures 3 to 9 (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the active structure (ie, CC' direction).

[0114] In one example, the semiconductor manufacturing process may include the following steps:

[0115] Step 1: Provide an original substrate 20 (such as a Si substrate) to obtain Figure 3 The structure shown.

[0116] Step 2: Etching the substrate 20 to form a first fin structure 111 and a second fin structure 121; then filling with oxide to form a first isolation structure 21, as shown in FIG. Figure 4 As shown in the structure, the first fin structure 111 may include a first fin structure located in the storage area and a first fin structure located in the logic area.

[0117] Step 3: Based on the first fin structures in the two regions, a first front transistor 10 located in the storage region and a second front transistor 11 located in the logic region are formed, and the following is obtained: Figure 5 The structure shown.

[0118] It can be understood that first, a portion of the isolation structure 22 can be etched until the first fin structure is exposed; then the gate area is opened by photolithography, and polysilicon is deposited in the gate area to form a first dummy gate structure; then a first sidewall 22 can be formed on both sides of the first dummy gate structure; based on the first fin structure 111 at the source and drain area, a first source and drain structure 112 is formed by epitaxial growth, and an interlayer dielectric is deposited on the first source and drain structure 112 to form a first interlayer dielectric layer 113; then the first dummy gate structure is removed, a first gate structure 114 is formed in the gate area, and a first source and drain metal 115 is formed on the first source and drain structure 112; and the back-end process of the front transistor is completed to form a first metal interconnect layer 116.

[0119] Since the front transistor 10 in the memory region and the front transistor 11 in the logic region are formed synchronously, Figure 5 The labels of the structures in the front transistor 10 located in the storage area and the front transistor 11 located in the logic area are the same.

[0120] Step 4: According to the standard process, the wafer is bonded and then flipped, the substrate is removed and the first isolation structure 21 is thinned to expose the back active structure, and the following is obtained: Figure 6 The structure shown.

[0121] It can be understood that oxide can be deposited on the first metal interconnect layer 116 to form an insulating layer 23, and the carrier wafer 24 is bonded to the insulating layer 23 above the insulating layer 23, and then the wafer is flipped to place the substrate on top, and then the substrate 20 is removed and the first isolation structure 21 is thinned to expose the second fin structure on the back side.

[0122] Step 5: Form a mask 25 above the storage area to obtain Figure 7 The structure shown.

[0123] Step 6: Based on the mask 25, the first isolation structure 21 is etched to form a second isolation structure 26 located in the logic area, and the following is obtained: Figure 8 The structure shown.

[0124] It can be understood that, since the height of the second isolation structure 26 is lower than that of the first isolation structure 21 , the height of the second fin structure 121 in the logic region is higher than that of the second fin structure 131 in the storage region.

[0125] Step 7: Based on the second fin structure 121 located in the logic area, a back transistor 12 located in the logic area is formed, and based on the second fin structure 131 located in the storage area, a back transistor 13 located in the storage area is formed, and the back transistor 13 located in the storage area is obtained. Fig. 9 The structure shown.

[0126] It can be understood that the mask 25 can be removed first, and then the gate area can be opened synchronously in the two areas, and polysilicon can be deposited in the gate area to form a second dummy gate structure; then a second sidewall 27 can be formed on both sides of the second dummy gate structure; based on the second fin structure 121 at the source and drain area, a second source and drain structure 122 is formed by epitaxial growth, and an interlayer dielectric is deposited on the second source and drain structure 122 to form a second interlayer dielectric layer 123; then the second dummy gate structure is removed, a second gate structure 124 is formed in the gate area, and a second source and drain metal 125 is formed on the second source and drain structure 122; and the back-end process of the back-side transistor is completed to form a second metal interconnection layer 126.

[0127] Since the back side transistor 13 in the memory area and the back side transistor 12 in the logic area are formed synchronously, Fig. 9 The structures of the back transistor 13 located in the storage area and the back transistor 12 located in the logic area have the same labels.

[0128] The second structure of the semiconductor structure is introduced below. Fig.10 This is a schematic top view of the semiconductor structure in the logic area or storage area in the embodiment of the present application. It should be noted that, for ease of understanding, only the active structure, gate structure and source-drain structure are shown in the top view. The AA' direction is the sectional direction of the semiconductor structure along the gate structure; the BB' direction is the sectional direction of the semiconductor structure along the source-drain structure; and the CC' direction is the sectional direction of the semiconductor structure along the active structure.

[0129] Fig.11 This is a second structural schematic diagram of the semiconductor structure of the embodiment of the present application. Different from the first preparation method, the substrate 20 in the first step is an SOI substrate, so after the fin structure is formed, the BOX layer 28 in the SOI substrate can be directly used as an isolation layer between the first fin structure and the second fin structure. Fig.11 Only the A-A' section is shown. Fig.11 (a) is a logic transistor, (b) is an SRAM, and you can see Fig.11 The height of the active structure in the logic transistor is higher than that in the SRAM.

[0130] In addition, in some embodiments, the embodiments of the present application can also isolate the front transistor from the back transistor through an intermediate dielectric isolation (MDI) layer. Referring to the preparation method of the first structure mentioned above, the difference from the preparation method of the first structure is that in the first step, the first material and the second material can be deposited on the substrate 20 in sequence to form a first material layer and a second material layer; the second material layer, the first material layer and a portion of the substrate 20 are etched to form a fin structure, and the etched first material layer can be used as a sacrificial layer, and the etched second material layer forms the portion of the fin structure away from the substrate. Moreover, after the first source and drain structure is formed in the third step, the sacrificial layer can be removed and the isolation material can be filled in the groove formed after the sacrificial layer is removed to form an MDI layer 28, and then the remaining steps are continued. In this way, the MDI layer can serve as an isolation structure between the front transistor and the back transistor.

[0131] Furthermore, the semiconductor structure provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the embodiment of the present application can use a TEM slicing method to detect the above-mentioned semiconductor structure. The detection method is: take the cross-section of the transistors in the logic area and the storage area perpendicular to the direction of the active structure, and measure the height of the active structure on the front and back sides, and four height values ​​can be obtained. As long as the height values ​​of the active structures of the storage area and the logic area on any side (front or back) are different, the detection method can be satisfied.

[0132] The present application provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can refer to the above semiconductor structure, which will not be described in detail here.

[0133] The embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as in the above embodiment, the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be referred to the above memory, which is not repeated here.

[0134] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0135] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: A pair of first semiconductor structures is formed on two regions of the substrate along a first direction, the pair of first semiconductor structures at least comprising a pair of first active structures and a pair of second active structures, the pair of first active structures being away from the substrate relative to the pair of second active structures, and the two regions comprising a logic region and a storage region; forming isolation structures on two regions of the substrate respectively to expose the pair of first active structures; Based on the pair of first active structures, forming a pair of front-side transistors, the pair of front-side transistors comprising a first front-side transistor located in the logic region and a second front-side transistor located in the memory region; Flipping the pair of front-side transistors and exposing the pair of second active structures; Based on the pair of second active structures, forming a pair of back side transistors, the pair of back side transistors comprising a first back side transistor located in the logic region and a second back side transistor located in the memory region; After exposing the pair of first active structures and / or the pair of second active structures, the isolation structure located in the logic region is etched so that the height of the active structure located in the logic region is higher than the height of the active structure located in the storage region.

2. The method according to claim 1, characterized in that After exposing the pair of first active structures, etching the isolation structure located in the logic area comprises: forming a first mask on the isolation structure and the first active structure located in the storage region; Based on the first mask, etching the isolation structure to a preset height, so that the height of the first active structure located in the logic area is higher than the height of the first active structure located in the storage area; The forming of a pair of front transistors based on the pair of first active structures comprises: The first front side transistor is formed based on a first active structure located in the logic region, and the second front side transistor is formed based on a first active structure located in the memory region.

3. The method according to claim 1 or 2, characterized in that: The exposing the pair of second active structures comprises: removing the substrate; Thinning the isolation structure to a predetermined height to expose the pair of second active structures; After exposing the pair of second active structures, etching the isolation structure located in the logic area comprises: forming a second mask on the remaining isolation structure and the second active structure located in the storage region; Based on the second mask, etching the retained isolation structure to a preset height, so that the height of the second active structure located in the logic area is higher than the height of the second active structure located in the storage area; The forming of a pair of back side transistors based on the pair of second active structures comprises: The first back side transistor is formed based on a second active structure located in the logic region, and the second back side transistor is formed based on a second active structure located in the memory region.

4. The method according to claim 1, characterized in that: The method further comprises: When the first front transistor and the first back transistor form a static random access memory SRAM and the first front transistor is an N-type transistor, after exposing the pair of first active structures, the isolation structure located in the storage area is etched so that the height of the first active structure located in the storage area is higher than the height of the second active structure located in the storage area.

5. The method according to claim 4, characterized in that After exposing the pair of first active structures, etching the isolation structure located in the storage area comprises: forming a third mask on the isolation structure and the first active structure located in the logic region; Based on the third mask, etching the isolation structure to a preset height, so that the height of the first active structure located in the storage area is higher than the height of the first active structure located in the logic area; The exposing the pair of second active structures comprises: removing the substrate; The isolation structure is thinned to a preset height to expose the pair of second active structures, wherein the height of the second active structure located in the storage area is lower than the height of the first active structure located in the storage area.

6. The method according to claim 1, characterized in that The step of forming a pair of first semiconductor structures on two regions of the substrate along a first direction comprises: providing a substrate; forming a first material layer and a second material layer on the substrate along a first direction; Etching the second material layer, the first material layer and a portion of the substrate to form the pair of first semiconductor structures, wherein the second material layer after etching is the first active structure, the portion of the substrate after etching is the second active structure, and the first material layer after etching is a sacrificial layer; Before forming a pair of front transistors based on the pair of active structures, the method further includes: removing the sacrificial layer to form a first groove; A dielectric material is filled in the first groove to form an isolation layer, and the isolation layer is used to isolate the first active structure from the second active structure.

7. A semiconductor structure, prepared using the preparation method according to any one of claims 1 to 6, characterized in that: include: A pair of front-side transistors and a pair of back-side transistors, wherein the pair of front-side transistors include a first front-side transistor located in a logic region and a second front-side transistor located in a storage region, and the pair of back-side transistors include a first back-side transistor located in the logic region and a second back-side transistor located in the storage region; wherein the height of the active structure located in the logic region is higher than the height of the active structure located in the storage region.

8. The semiconductor structure according to claim 7, characterized in that: When the first front transistor and the first back transistor form a static random access memory SRAM and the first front transistor is an N-type transistor, a height of a first active structure located in the storage region is higher than a height of a second active structure located in the storage region.

9. A semiconductor device, characterized in that: include: A semiconductor structure as claimed in claim 7 or 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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