Memory device and method of manufacturing the same

Abstract

The invention relates to a memory device and a manufacturing method thereof. A method of manufacturing a memory device is provided herein. The method may include the steps of: forming an ion implantation region in a portion of an exterior of the underlayer structure by implanting ions into the underlayer structure; converting the ion implantation region into an etching stop pattern; forming a target structure on the underlying structure including the etch stop pattern; and performing an etching process to form a first hole and a second hole in the target structure, where a first width of the first hole is different from a second width of the second hole. An etching process is performed until the etch stop pattern is exposed through the first hole and the second hole.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to memory devices and methods of manufacturing the same, and more particularly, to a three-dimensional (3D) memory device. Background Art

[0002] The memory device may include a memory cell array storing data, a peripheral circuit configured to perform a program operation, a read operation, and an erase operation with respect to the memory cell array, and a control circuit configured to control the peripheral circuit.

[0003] The memory cell array may include a plurality of memory blocks, and each memory block may include a plurality of memory cells.

[0004] In order to increase the data storage capacity of a memory device and reduce the size of the memory device, the integration degree of the memory device has gradually increased.

[0005] In conventional memory devices, memory cells are arranged in a direction parallel to a substrate. However, due to physical limitations in increasing integration, memory cells are manufactured in a structure in which memory cells are stacked in a vertical direction from a substrate. The conventional structure in which memory cells are arranged in a direction parallel to a substrate is referred to as a two-dimensional (2D) structure, while the structure in which memory cells are stacked in a direction perpendicular to the substrate is referred to as a three-dimensional (3D) structure.

[0006] A memory device having a three-dimensional structure may include a cell region including a memory cell and a peripheral region including a peripheral circuit for operating the memory cell. Because the structures included in the cell region and the peripheral circuit region may perform different functions, the structures may have different sizes. For example, the width of a cell plug included in the cell region may be different from the width of a contact or a support structure included in the peripheral region. In addition to the cell plug, the contact, and the support structure, the memory device may also include a vertical structure that performs various functions.

[0007] In order to form the vertical structure, an etching process for forming the vertical hole may be performed. For example, the etching process may be an anisotropic dry etching process that may be performed to form the vertical hole. During the anisotropic dry etching process, the bottom of the target structure is removed by an etchant. As the width of the vertical hole increases, the area exposed to the etchant increases, thereby resulting in a difference in etching rate. For example, the depth of the vertical hole may vary depending on the width of the vertical hole. Summary of the invention

[0008] Embodiments of the present disclosure may provide a method for manufacturing a memory device. The method may include the following steps: forming an ion implantation region in a portion of an outer portion of an underlying structure by implanting ions into the underlying structure; converting the ion implantation region into an etch stop pattern; forming a target structure on the underlying structure including the etch stop pattern; and performing an etching process to form a first hole and a second hole in the target structure, wherein a first width of the first hole is different from a second width of the second hole. The etching process may be performed until the etch stop pattern is exposed through the first hole and the second hole.

[0009] Embodiments of the present disclosure may provide a method for manufacturing a memory device. The method may include the following steps: forming an ion implantation region in a portion of an outer portion of a first underlying structure; performing a heat treatment process for changing the ion implantation region into an etch stop pattern; alternately stacking a first material layer and a second material layer on the first underlying structure including the etch stop pattern; and forming a first hole exposing a first portion of the etch stop pattern and a second hole exposing a second portion of the etch stop pattern in the first material layer and the second material layer, wherein the first hole has a first width, and wherein the second hole has a second width greater than the first width.

[0010] Embodiments of the present disclosure may provide a memory device, comprising: an underlying structure comprising a first etch stop pattern and a second etch stop pattern; and a target structure formed above the underlying structure, wherein a first hole having a first aspect ratio and a second hole having a second aspect ratio smaller than the first aspect ratio are formed in the target structure, wherein the first etch stop pattern is exposed through the first hole and the second etch stop pattern is exposed through the second hole; wherein the first etch stop pattern and the second etch stop pattern comprise etch stop ions for stopping an etching process; and wherein the second etch stop pattern comprises an area where the concentration of the etch stop ions is high and an area where the concentration of the etch stop ions is low.

[0011] Embodiments of the present disclosure may provide a method for manufacturing a memory device. The method may include the following steps: forming a target structure above an underlying structure; forming a mask pattern above the target structure; using the mask pattern to implant etch stop ions into the underlying structure through the target structure to form a first etch stop pattern and a second etch stop pattern; and etching the target structure using the mask pattern until the first etch stop pattern is exposed to form a first hole having a first aspect ratio, and etching the target structure until the second etch stop pattern is exposed to form a second hole having a second aspect ratio less than the first aspect ratio; wherein, when the etch stop ions are implanted, the second etch stop pattern includes a region where the concentration of the etch stop ions is high and a region where the concentration of the etch stop ions is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A diagram showing a memory device formed using a conventional method of manufacturing a memory device.

[0013] Figures 2 to 7 Various diagrams showing a memory device formed using the method of manufacturing the memory device according to the first embodiment of the present disclosure.

[0014] Figure 8 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0015] Fig. 9 is a diagram showing a memory block included in a memory device according to an embodiment of the present disclosure.

[0016] Figures 10 to 20 Additional diagrams showing a memory device formed using the method of manufacturing the memory device according to the first embodiment.

[0017] Figure 21 to Figure 26 Various diagrams showing a memory device formed using the method of manufacturing the memory device according to the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The specific structural or functional description disclosed herein is exemplified to describe the embodiments of the concepts according to the present disclosure. The embodiments of the concepts according to the present disclosure should not be interpreted as limited to the embodiments to be described later, and may be modified in various forms and replaced with other equivalent embodiments.

[0019] Although terms such as "first" and "second" may be used herein to describe various elements, the elements are not limited by these terms. Terms are used to distinguish one element from other elements and do not imply size, order, priority, or importance. Terms such as "top" or "bottom" or "above" or "below" or "above" or other terms that imply spatial relationships are provided only for ease of description or reference and are not limiting.

[0020] Figure 1 A diagram showing a memory device formed using a conventional method of manufacturing a memory device.

[0021] Reference Figure 1 In an example of the present invention, a target structure TGS is formed on an underlying structure UDS, and a mask pattern MP is formed on the target structure TGS. The mask pattern MP includes an opening OP that exposes a portion of a top surface or an outer surface of the target structure TGS. For example, each opening OP corresponding to the first hole 1HL may have a first width 1WT, and each opening OP corresponding to the second hole 2HL may have a second width 2WT greater than the first width 1WT. In the layout, each of the first hole 1HL and the second hole 2HL may have a circular shape, an elliptical shape, or a linear shape, respectively.

[0022] The etching process may be an anisotropic dry etching process that may be performed to simultaneously form the first hole 1HL and the second hole 2HL. During the anisotropic dry etching process, the etchant ions E may collide in a direction perpendicular to the bottom surface of the target structure TGS exposed by the opening OP of the mask pattern MP. When the etchant ions E contact the target structure TGS, the atoms or molecules of the target structure TGS may be separated from the body of the target structure TGS by physical impact or chemical change. The target ions T separated from the target structure TGS may be combined with free radicals Ra and discharged to the outside of the chamber.

[0023] Because there is a difference in the area exposed by the first hole 1HL and the second hole 2HL at the bottom surface, the depth of the first hole 1HL and the second hole 2HL may also differ during the etching process. For example, because the second width 2WT of the second hole 2HL is greater than the first width 1WT of the first hole 1HL, the etching rate of the second hole 2HL may be greater than the etching rate of the first hole 1HL. Therefore, when the etching process is performed until the underlying structure UDS is exposed through the first hole 1HL and the second hole 2HL, a depth difference may occur. For example, when the first hole 1HL has a first depth 1DP, the second hole 2HL may have a second depth 2DP deeper than the first depth 1DP. Depth refers to the length or distance from the top surface or uppermost surface of the target structure TGS (relative to the perspective of the drawing) to the bottom surface or lowermost surface of the first hole 1HL or the second hole 2HL (relative to the perspective of the drawing).

[0024] After forming the first hole 1HL and the second hole 2HL having different depths 1DP and 2DP, the first hole 1HL and the second hole 2HL are filled with a gap filling material, and a process of removing the underlying structure UDS is performed. Initially, the gap filling material in the second hole 2HL is exposed to the etching process, and as the etching process continues, the gap filling material in the first hole 1HL is exposed. In this example, as the etching process continues, the etching damage to the gap filling material in the second hole 2HL increases to expose the gap filling material in the first hole 1HL.

[0025] In various embodiments described below, methods of manufacturing memory devices allow holes of different widths to have the same depth. Various embodiments relate to methods of manufacturing memory devices that can advantageously reduce defects in memory devices.

[0026] Figures 2 to 7 Various diagrams showing a memory device formed using the method of manufacturing the memory device according to the first embodiment of the present disclosure.

[0027] Reference Figure 2, the first mask pattern 1MP may be formed on the underlying structure UDS. The underlying structure UDS may be a substrate. For example, the substrate may be an N-type or P-type silicon substrate. The first mask pattern 1MP may be a photoresist pattern, or may include a hard mask pattern and a photoresist pattern stacked on the hard mask pattern. For example, the hard mask pattern may be a mask layer formed of carbon. In order to form the photoresist pattern of the first mask pattern 1MP, an exposure process and a development process using the first photomask 1PM may be performed.

[0028] For example, a photoresist layer may be formed on an underlying structure USD or a hard mask layer, and an exposure process and a development process using a first photomask 1PM may be performed. The first photomask 1PM may include a transmission plate PP and a blocking pattern BP. For example, the transmission plate PP may be a glass plate, and the blocking pattern BP may be formed of chrome. The first photomask 1PM is not limited to the above materials. A first opening 1OP and a second opening 2OP are formed in the blocking pattern BP, wherein a width 1WT of the first opening 1OP is different from a width 2WT of the second opening 2OP. When performing the exposure process, the light source LS may not penetrate the blocking pattern BP, and the photoresist layer may be irradiated through the first opening 1OP and the second opening 2OP. During the development process, a portion of the photoresist layer irradiated by the light source LS may be removed. Therefore, forming the first mask pattern 1MP includes forming the first opening 1OP and the second opening 2OP in the first mask pattern 1MP. When the hard mask layer is formed under the photoresist layer, an etching process may be further performed to remove a portion of the hard mask layer exposed through the first opening 1OP and the second opening 2OP after forming the first opening 1OP and the second opening 2OP in the photoresist layer.

[0029] In the first mask pattern 1MP, each first opening 1OP is formed with a first width 1WT, and each second opening 2OP is formed with a second width 2WT greater than the first width 1WT. In this example, the area of ​​the underlying structure UDS exposed by the first opening 1OP of the first mask pattern 1MP is smaller than the area of ​​the underlying structure UDS exposed by the second opening 2OP.

[0030] Reference Figure 3, an ion implantation process may be performed to form a first ion implantation region 1IP and a second ion implantation region 2IP in the underlying structure UDS, which are exposed through the first opening 1OP and the second opening 2OP of the first mask pattern 1MP, respectively. For example, the ion implantation process may be performed by implanting ions (e.g., etching stop ions) of a material different from the material to be formed on the underlying structure UDS. For example, the ion implantation process may be performed by implanting nitrogen ions into the region of the underlying structure UDS exposed through the first opening 1OP and the second opening 2OP. The first ion implantation region 1IP and the second ion implantation region 2IP of the underlying structure UDS implanted with nitrogen ions may be an amorphous silicon nitride layer (SixNy; where x and y are positive integers). Each of the first ion implantation regions 1IP may have a first width 1WT that is the same as the width of each of the first openings 1OP. Each of the second ion implantation regions 2IP may have a second width 2WT that is the same as the width of each of the second openings 2OP. Each of the first ion implantation region 1IP and the second ion implantation region 2IP may have a third depth 3DP. The third depth 3DP is the length or distance from the top surface, upper surface or uppermost surface (relative to the perspective of the drawing) of the underlying structure UDS to the lowest surface of the implanted ions. The third depth 3DP can be adjusted according to various conditions of the ion implantation process. For example, the third depth 3DP can be adjusted according to the type of gas supplied to the chamber during the ion implantation process, the amount of gas, the moving speed of the ionized positive ions, and / or the temperature inside the chamber.

[0031] The first ion implantation region 1IP and the second ion implantation region 2IP are formed to a third depth 3DP along the outer surface or the top surface (relative to the perspective of the drawing) of the underlying structure UDS, but the ion implantation concentration within the third depth 3DP may vary. For example, the concentration of nitrogen ions may vary within the ion implantation region according to the depth. By adjusting the ion implantation energy during the ion implantation process, a high concentration region HDS of ions and a low concentration region LDS of ions may be obtained, and the concentration of ions may vary within the ion implantation region. The high concentration region HDS has an etching stop ion concentration higher than the low concentration region LDS, in other words, the low concentration region LDS has an etching stop ion concentration lower than the high concentration region HDS. Taking the second ion implantation region 2IP as an example, the second ion implantation region 2IP includes a high concentration region HDS located outside (exposed portion) or on top of the second ion implantation region 2IP in the underlying structure UDS and a low concentration region LDS located below or below the high concentration region HDS (relative to the perspective of the drawing) (i.e., inside the exposed periphery or away from the exposed periphery), for example Figure 3In another example, the second ion implantation region 2IP may include a low concentration region LDS located outside (outermost) or upper and innermost (farthest from the exposed periphery of the second ion implantation region 2IP of the underlying structure UDS) or lower portion of the second ion implantation region 2IP in the underlying structure UDS, and may include a high concentration region HDS located between the low concentration regions LDS, for example Figure 3 In another example, the second ion implantation region 2IP may include a low-concentration region LDS outside (exposed portion) or upper portion of the second ion implantation region 2IP in the underlying structure UDS, and may include a high-concentration region HDS located below or below the low-concentration region LDS (relative to the viewing angle of the drawing) (i.e., inside or away from the exposed periphery), for example Figure 3 As shown in the right cross-sectional view at the bottom of FIG. Etching stop can be achieved more efficiently in the high concentration region HDS than in the low concentration region LDS.

[0032] Reference Figure 4 , a heat treatment process is performed to make the first ion implantation region 1IP and the second ion implantation region 2IP (see Figure 3 ) is recrystallized. The first ion implantation region 1IP and the second ion implantation region 2IP (see Figure 3 ) are used as the first etching stop pattern 1ES and the second etching stop pattern 2ES respectively. For example, the first ion implantation region 1IP (see Figure 3 ) becomes the first etching stop pattern 1ES, and the second ion implantation region 2IP (see Figure 3 ) becomes the second etch stop pattern 2ES. Therefore, the thermal treatment process transforms or changes the ion implantation region into the etch stop pattern, and this process may be referred to as activating the ion implantation region.

[0033] During the heat treatment process, the ions implanted into the first ion implantation region 1IP and the second ion implantation region 2IP diffuse into the underlying structure UDS, so that the size of the first etch stop pattern 1ES may be larger than the size of the first ion implantation region 1IP, and the size of the second etch stop pattern 2ES may also be larger than the size of the second ion implantation region 2IP. For example, each first etch stop pattern 1ES may have a width greater than the first width 1WT (see Figure 3 ), each of the second etch stop patterns 2ES may have a third width 3WT greater than the second width 2WT (see Figure 3). The first etch stop pattern 1ES and the second etch stop pattern 2ES may have a fourth depth 4DP deeper than the depths of the first ion implantation region 1IP and the second ion implantation region 2IP. The first etch stop pattern 1ES and the second etch stop pattern 2ES may have the same depth, but may have different depths according to the concentration of ions implanted in the first ion implantation region 1IP and the second ion implantation region 2IP.

[0034] Reference Figure 5 , the target structure TGS and the second mask pattern 2MP may be sequentially stacked on the underlying structure UDS including the first etch stop pattern 1ES and the second etch stop pattern 2ES. For example, the target structure TGS may be formed of a single layer or multiple layers. In the first embodiment, the type and amount of the material forming the target structure TGS are not limited to specific types and amounts.

[0035] The second mask pattern 2MP may be composed of a photoresist pattern, or may be composed of a hard mask pattern and a photoresist pattern stacked on the hard mask pattern. For example, the hard mask pattern may be a mask layer formed of carbon. In order to form the photoresist pattern of the second mask pattern 2MP, an exposure process and a development process using the second photomask 2PM may be performed. The second photomask 2PM may be similar to the above-mentioned Figure 2 The first photomask 1PM described is the same. When an exposure process and a development process using the second mask pattern 2MP are performed, the second mask pattern 2MP is formed, including forming third openings 3OP and fourth openings 4OP in the second mask pattern 2MP.

[0036] In this example, in the second mask pattern 2MP, each third opening 3OP is formed with a first width 1WT, and each fourth opening 4OP is formed with a second width 2WT greater than the first width 1WT. In this example, the area of ​​the target structure TGS exposed through the third openings 3OP of the second mask pattern 2MP is smaller than the area of ​​the target structure TGS exposed through the fourth openings 4OP.

[0037] In various embodiments, when the first etch stop pattern 1ES and the second etch stop pattern 2ES have not been formed, the target structure TGS may be formed on the underlying structure UDS. The second mask pattern 2MP (or the first mask pattern 1MP) may be formed on the target structure TGS to expose the area where the first opening 1OP and the second opening 2OP will be formed. The ions (i.e., etch stop ions) used to stop the etching in the target structure TGS may be implanted into the top surface or outer surface of the underlying structure UDS by adjusting the implantation energy, for example, through the projected depth of the target structure into the underlying structure UDS. The etch stop ions may be implanted through the target structure. For example, the etch stop ions may be nitrogen ions. The projected depth of the etch stop ions and the concentration of the etch stop ions may be controlled or adjusted based on the aspect ratio of the first opening 1OP and the second opening 2OP or the height and / or width of the first opening 1OP and the second opening 2OP. The etch stop ions may be activated by a thermal treatment such as an annealing process to form the first etch stop pattern 1ES and the second etch stop pattern 2ES.

[0038] For example, when the first opening 1OP has a first aspect ratio and the second opening 2OP has a second aspect ratio smaller than the first aspect ratio, the concentration of the etching stop ions in the first etching stop pattern 1ES to be exposed through the first opening 1OP may be uniform, but the concentration of the etching stop ions of the second etching stop pattern 2ES may vary according to the depth (or thickness) of the second etching stop pattern 2ES. For example, the second etching stop pattern 2ES may include a high concentration region HDS of etching stop ions and a low concentration region LDS of etching stop ions, such as Figure 3 As shown in the cross-sectional view in . The high concentration region may be located in any of the upper portion, the lower portion, and the middle portion between the upper portion and the lower portion of the second etch stop pattern 2ES. The advantage of placing the high concentration region HDS at various positions, layers, or heights in the second etch stop pattern 2ES is to provide control by selectively reducing over-etching. The position of the high concentration region HDS of the second etch stop pattern 2ES may be determined considering the aspect ratio of the first opening 1OP and the second opening 2OP and the degree of over-etching of the bottom area of ​​each of the first opening 1OP and the second opening 2OP. The aspect ratio of a hole (or pattern) may be the ratio of its width to its height.

[0039] Reference Figure 6, an etching process may be performed to form a first hole 1HL and a second hole 2HL in the target structure TGS exposed by the third opening 3OP and the fourth opening 4OP of the second mask pattern 2MP. The etching process may be an anisotropic dry etching process. Because the area exposed by the fourth opening 4OP during the etching process of the target structure TGS is larger than the area exposed by the third opening 3OP, the second hole 2HL may be formed to a deeper depth than the first hole 1HL, in other words, the second hole 2HL may be formed to a height higher than the height of the formed first hole 1HL.

[0040] Therefore, before the first etch stop pattern 1ES is exposed through the first hole 1HL, the second etch stop pattern 2ES may be exposed through the second hole 2HL. Therefore, during the etching process for forming the first hole 1HL at the third depth 3DP (target depth), the depth of the second hole 2HL may be prevented from increasing beyond the target depth. The etching process may be performed until the first etch stop pattern 1ES and the second etch stop pattern 2ES are exposed through the first hole 1HL and the second hole 2HL, respectively.

[0041] Reference Figure 7 , the gap filling layer may be filled in the first hole 1HL and the second hole 2HL to form a first vertical structure 1VS and a second vertical structure 2VS contacting the first etch stop pattern 1ES and the second etch stop pattern 2ES. The first vertical structure 1VS and the second vertical structure 2VS may be formed of the same material to provide the same structure, or may be formed of different materials to provide different structures. For example, the first vertical structure 1VS may be formed in the first hole 1HL, and the second vertical structure 2VS may be formed in the second hole 2HL. The first vertical structure 1VS and the second vertical structure 2VS may be formed to have a third depth 3DP by the first etch stop pattern 1ES and the second etch stop pattern 2ES.

[0042] A method of manufacturing the memory device according to the first embodiment using the above-described manufacturing method is as follows.

[0043] Figure 8 is a diagram illustrating a memory device according to an embodiment of the present disclosure described herein.

[0044] Reference Figure 8 , the memory device 100 may include a memory cell array 110 and a peripheral circuit 170 .

[0045] The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. Each of the first to j-th memory blocks BLK1 to BLKj may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be coupled to each of the first to j-th memory blocks BLK1 to BLKj, and a bit line BL may be commonly coupled to the first to j-th memory blocks BLK1 to BLKj.

[0046] Each of the first to j-th memory blocks BLK1 to BLKj may be formed to have a three-dimensional (3D) structure. Each memory block having a 3D structure may include memory cells stacked on a substrate in a vertical direction. According to a programming scheme, each memory cell may store 1 bit of data or 2 or more bits of data. For example, a scheme for storing 1 bit of data in one memory cell is called a single-level cell (SLC) scheme, and a scheme for storing 2 bits of data in one memory cell is called a multi-level cell (MLC) scheme. A scheme for storing 3 bits of data in one memory cell is called a three-level cell (TLC) scheme, and a scheme for storing 4 bits of data in one memory cell is called a quad-level cell (QLC) scheme. In addition, 5 or more bits of data may be stored in one memory cell.

[0047] The peripheral circuit 170 may perform a program operation including storing data in the memory cell array 110, a read operation including outputting data stored in the memory cell array 110, and an erase operation including erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, an input / output circuit 160, and a control circuit 180.

[0048] The voltage generator 120 may generate various operation voltages Vop for a program operation, a read operation, or an erase operation in response to the operation code OPCD. For example, the voltage generator 120 may generate a program voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the memory block selected by the row decoder 130.

[0049] The programming voltage may be a voltage applied to a selected word line among word lines WL during a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. The on-voltage may be applied to a drain selection line DSL or a source selection line SSL, and may be used to turn on a drain selection transistor or a source selection transistor. The cut-off voltage may be applied to a drain selection line DSL or a source selection line SSL, and may be used to turn off a drain selection transistor or a source selection transistor. For example, the cut-off voltage may be set to 0V. The precharge voltage may be a voltage higher than 0V, and may be applied to a bit line during a read operation. The verification voltage may be used during a verification operation including determining whether the threshold voltage of a selected memory cell has been increased to a target level. The verification voltage may be set to various levels according to the target level, and may be applied to the selected word line. The read voltage may be applied to the selected word line during a read operation performed on the selected memory cell. For example, the read voltage may be set to various levels according to the programming scheme of the selected memory cell. The pass voltage may be a voltage applied to an unselected word line among the word lines WL during a program operation or a read operation, and may be used to turn on the memory cells connected to the unselected word lines. The erase voltage may be used during an erase operation to erase the memory cells included in the selected memory block, and may be applied to the source line SL.

[0050] The row decoder 130 may transmit the operation voltage Vop to the drain select line DSL, the word line WL, the source select line SSL, and the source line SL coupled to the memory block selected according to the row address RADD. For example, the row decoder 130 may be coupled to the voltage generator 120 through the global line GL, and may be coupled to the first memory block BLK1 to the j-th memory block BLKj through the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0051] The page buffer group 140 may include page buffers (not shown) respectively coupled to the first to j-th memory blocks BLK1 to BLKj. The page buffer (not shown) may be coupled to each of the first to j-th memory blocks BLK1 to BLKj through a bit line BL.

[0052] The column decoder 150 may be configured so that data is transferred between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be coupled to the page buffer group 140 through the column line CL, and may send an enable signal through the column line CL. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0053] The input / output circuit 160 may receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller through the input / output line I / O to the control circuit 180, and may transmit data received from the external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller through the input / output line I / O.

[0054] The control circuit 180 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 so that a program operation is performed on a storage block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 so that a read operation is performed on a storage block selected by the address and the read data is output. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 so that an erase operation is performed on the selected storage block.

[0055] Fig. 9 is a diagram illustrating memory blocks included in a memory device according to an embodiment of the present disclosure described herein.

[0056] Reference Fig. 9 , the memory cell array 110 may be located on the peripheral circuit 170, but the locations of the memory cell array 110 and the peripheral circuit are not limited to Fig. 9 For example, the memory cell array 110 may be located on the same plane as the peripheral circuit 170, or the memory cell array and the peripheral circuit may be formed on different substrates and then contact each other.

[0057] The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. The first to j-th memory blocks BLK1 to BLKj may be arranged to be spaced apart from each other in the Y direction. The first to j-th memory blocks BLK1 to BLKj may be configured identically to each other and divided from each other by slit regions 1SR, 2SR, ... Each of the slit regions 1SR, 2SR, ... may extend along the X direction. For example, the first memory block BLK1 and the second memory block BLK2 may be divided from each other by the first slit region 1SR.

[0058] The first to j-th memory blocks BLK1 to BLKj may include a cell region CE and a connection region CN. The cell region CE may include a memory cell, and the connection region CN may include a contact and a support structure. The memory cell may be configured to store data, the contact may be configured to contact a gate line extending from the cell region CE or to contact a peripheral circuit located at a lower portion of the memory block, and the support structure may be configured to support a stacked structure located in the connection region CN.

[0059] Figures 10 to 20 Additional diagrams showing a memory device formed using the method of manufacturing the memory device according to the first embodiment.

[0060] Reference Fig.10 , forming a peripheral structure PST. The peripheral structure PST may include Fig. 9 At least a portion of the peripheral circuit 170 shown. The peripheral structure PST may include a first substrate 1SUB, a transistor TR formed on the first substrate 1SUB, a contact CT, and a peripheral line PL. The first substrate 1SUB may be a silicon substrate. The transistor TR may be formed and included in the peripheral circuit 170 (see Fig. 9 ), the contact CT may be configured to electrically connect the first substrate 1SUB and the peripheral line PL, to electrically connect the peripheral lines PL located at different layers, or to electrically connect the transistor TR and the peripheral line PL. The first interlayer insulator 1ITS may be filled between the transistor TR, the contact CT and the peripheral line PL.

[0061] Reference Fig.11 , the third mask pattern 3MP may be formed on the second substrate 2SUB. The second substrate 2SUB may be a silicon substrate. The third mask pattern 3MP may include a fifth opening 5OP and a sixth opening 6OP that expose a portion of the second substrate 2SUB. In this example, the width of each fifth opening 5OP is smaller than the width of each sixth opening 6OP. Therefore, the area of ​​the second substrate 2SUB exposed by the fifth opening 5OP is smaller than the area of ​​the second substrate 2SUB exposed by the sixth opening 6OP.

[0062] Subsequently, an ion implantation process may be performed to form a third ion implantation region 3IP and a fourth ion implantation region 4IP in the second substrate 2SUB exposed through the fifth opening 5OP and the sixth opening 6OP, respectively. The third ion implantation region 3IP may be formed in the second substrate 2SUB exposed through the fifth opening 5OP, and the fourth ion implantation region 4IP may be formed in the second substrate 2SUB exposed through the sixth opening 6O.

[0063] The ion implantation process may be performed using ions whose etching selectivity may be different from that of the second substrate 2SUB. For example, the ion implantation process may be performed by implanting nitrogen ions into the second substrate 2SUB exposed by the fifth opening 5OP and the sixth opening 6OP. The third ion implantation region 3IP and the fourth ion implantation region 4IP of the second substrate 2SUB implanted with nitrogen ions may become an amorphous silicon nitride layer (SixNy; wherein x and y are positive integers). The depth and width of the third ion implantation region 3IP and the fourth ion implantation region 4IP may be adjusted during the ion implantation process according to the type of gas supplied to the chamber, the amount of gas, the moving speed of the ions, and / or the temperature inside the chamber.

[0064] Reference Fig.12 , a heat treatment process may be performed to make the third ion implantation region 3IP and the fourth ion implantation region 4IP (see Fig.11 ) of the second substrate 2SUB is recrystallized. In this example, the third ion implantation region 3IP and the fourth ion implantation region 4IP (see Fig.11 ) is used as the third etch stop pattern 3ES and the fourth etch stop pattern 4ES. For example, the third ion implantation region 3IP (see Fig.11 ) becomes the third etching stop pattern 3ES, and the fourth ion implantation region 4IP (see Fig.11 ) becomes the fourth etching stop pattern 4ES.

[0065] During the heat treatment process, the ions implanted into the third ion implantation region 3IP and the fourth ion implantation region 4IP may diffuse into the second substrate 2SUB, so that the size of the third etch stop pattern 3ES may be larger than the size of the third ion implantation region 3IP, and the size of the fourth etch stop pattern 4ES may also be larger than the size of the fourth ion implantation region 4IP. The sizes of the third etch stop pattern 3ES and the fourth etch stop pattern 4ES may vary according to the concentration of ions implanted into the second substrate 2SUB.

[0066] Reference Fig.13 A stacked structure STK (which may be referred to as a target structure TGS) including a first material layer 1MT and a second material layer 2MT may be formed on a second substrate 2SUB including a third etch stop pattern 3ES and a fourth etch stop pattern 4ES. For example, the first material layer 1MT may be an oxide layer, and the second material layer 2MT may be a nitride layer. Fig.13As shown in the example of , the first material layers 1MT and the second material layers 2MT may be alternately stacked. Among the first material layers 1MT, the lowermost first material layer 1MT may be thicker than the other first material layers 1MT. Therefore, during the subsequent etching process, the etching conditions change so that the etching selectivity of the first material layer 1MT is higher than the etching selectivity of the third etching stop pattern 3ES and the fourth etching stop pattern 4ES.

[0067] Reference Fig.14 , a fourth mask pattern 4MP including a seventh opening 7OP and an eighth opening 8OP may be formed on the stack structure STK. The fourth mask pattern 4MP may expose a portion of the stack structure STK through the seventh opening 7OP and the eighth opening 8OP. The width of each seventh opening 7OP may be smaller than the width of each eighth opening 8OP. Subsequently, an etching process may be performed to form a third hole 3HL and a fourth hole 4HL in the stack structure STK exposed through the seventh opening 7OP and the eighth opening 8OP.

[0068] The etching process may be an anisotropic dry etching process. Because the area exposed through the eighth opening 8OP during the etching process of the stacked structure STK is greater than the area exposed through the seventh opening 7OP, the fourth hole 4HL may be formed to have a deeper depth than the third hole 3HL. Therefore, before the third etch stop pattern 3ES is exposed through the third hole 3HL, the fourth etch stop pattern 4ES may be exposed through the fourth hole 4HL. During the etching process, when a component of the third etch stop pattern 3ES and the fourth etch stop pattern 4ES is detected, the condition of the etching process may be changed so that the etching selectivity of the first material layer 1MT of the target structure is higher than the etching selectivity of the third etch stop pattern 3ES and the fourth etch stop pattern 4ES.

[0069] Therefore, while performing the etching process to form the third hole 3HL at a target depth, the depth of the fourth hole 4HL may be prevented from increasing beyond the target depth. The etching process may be performed until the third and fourth etch stop patterns 3ES and 4ES are exposed through the third and fourth holes 3HL and 4HL, respectively.

[0070] Reference Fig.15 , the cell plug CP may be formed in the third hole 3HL, and the third vertical structure 3VS may be formed in the fourth hole 4HL.

[0071] The cell plug CP may include a memory cell and a selection transistor, for example, as described with respect to Figure 8 and Fig. 9As described. For example, each cell plug CP corresponding to a memory cell or a selection transistor may include a core column CR, a channel layer CH, and a memory layer ML. The memory layer ML may include a tunnel isolation layer TX, a charge capture layer CG, and a blocking layer BX. The core column CR may have a cylindrical shape and may be formed to include an insulating material or a conductive material. The channel layer CH may have a cylindrical shape surrounding the side of the core column CR and may be formed of polysilicon. The tunnel isolation layer TX may have a cylindrical shape surrounding the side of the channel layer CH and may be formed of an oxide layer. The charge capture layer CG may have a cylindrical shape surrounding the side of the tunnel isolation layer TX and may be formed of a nitride layer. The blocking layer BX may have a cylindrical shape surrounding the side of the charge capture layer CG and may be formed of an oxide layer.

[0072] The third vertical structure 3VS may be a support structure or a contact. When the third vertical structure 3VS is a support structure, the third vertical structure 3VS may be formed to include an insulating material, or may be formed to include the same material as the cell plug. When the third vertical structure 3VS is formed as a contact, the third vertical structure 3VS may include a conductive material, and may further include an insulator surrounding the side of the conductive material.

[0073] Since the depths of the third and fourth holes 3HL and 4HL are similar to each other due to the placement of the third and fourth etch stop patterns 3ES and 4ES, the heights of the cell plugs CP and the third vertical structures 3VS formed in the third and fourth holes 3HL and 4HL are also similar to each other.

[0074] Reference Fig.16 , the second material layer 2MT (see Fig.15 ) is replaced by the third material layer 3MT. For example, a slit that divides the memory block may be formed, and the second material layer 2MT exposed by the slit may be removed. Subsequently, the third material layer 3MT may be formed in the area where the second material layer 2MT is removed. Since the third material layer 3MT is used as a word line or a selection line, the third material layer 3MT may be formed of a conductive material. For example, the third material layer 3MT may be formed to include a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co), and nickel (Ni), or a semiconductor material such as silicon (Si) or polycrystalline silicon (Poly-Si).

[0075] Reference Fig.17 The contact CT, the bit line BL, and the second interlayer insulator 2ITS may be formed on the entire structure including the cell plug CP and the third vertical structure 3VS. For example, the contact CT and the bit line BL may be formed on the cell plug CP.

[0076] Reference Fig.18 , optionally, refer to Fig.17The entire structure described can be flipped, in other words, rotated 180 degrees vertically relative to the view of the drawing or flipped in other ways to facilitate further processing. The flipped structure is in contact with the peripheral structure PST, for example, with reference to Fig.10 For example, when referring to Fig.17 When the entire structure described is flipped, the second substrate 2SUB may be located at the top of the structure relative to the perspective of the drawing, and the second interlayer insulator 2ITS and the bit line BL may be located at the bottom of the flipped structure relative to the perspective of the drawing. Although not shown in the figure, the bit line BL may contact the contact included in the peripheral structure PST, and the second interlayer insulator 2ITS may contact the first interlayer insulator 1ITS of the peripheral structure PST (see Fig.10 ). Reference Fig.17 The entire structure described may be referred to as a handling structure having a first end opposite a second end, wherein in this example a second substrate 2SUB or underlying structure UDS is disposed at the first end of the handling structure and a second interlayer insulator 2ITS is disposed at the second end of the handling structure.

[0077] Reference Fig.19 Optionally, the second substrate 2SUB (see Fig.18 ) is removed. The second substrate 2SUB may be removed by a wet etching process. Due to the difference in etching selectivity from the second substrate 2SUB, the third etching stop pattern 3ES and the fourth etching stop pattern 4ES may remain. During the etching process for removing the second substrate 2SUB, the cell plug CP and the third vertical structure 3VS may be advantageously protected by the third etching stop pattern 3ES and the fourth etching stop pattern 4ES, thereby preventing the cell plug CP and the vertical structure 3VS from being damaged due to the etching process.

[0078] Reference Fig. 20 , the third etch stop pattern 3ES and the fourth etch stop pattern 4ES (see Fig.18 ) may be removed. For example, the third etch stop pattern 3ES and the fourth etch stop pattern 4ES may be removed by a dry etching process. When the third etch stop pattern 3ES and the fourth etch stop pattern 4ES are removed, portions of the cell plug CP and the third vertical structure 3VS may protrude from the top of the entire structure (e.g., the first material layer 1MT) relative to the perspective of the drawing. The protruding portion of the third vertical structure 3VS is referred to as a first protrusion 1PT, and the protruding portion of the cell plug CP is referred to as a second protrusion 2PT. The first protrusion 1PT and the second protrusion 2PT may have the same height HT.

[0079] Figure 21 to Figure 26 Various diagrams showing a memory device formed using the method of manufacturing the memory device according to the second embodiment of the present disclosure.

[0080] Reference Fig.21, the first mask pattern 1MP may be formed on the underlying structure UDS. The first mask pattern 1MP may include a first opening 1OP and a second opening 2OP that expose a portion of the underlying structure UDS. An ion implantation process is performed to form a first ion implantation region 1IP and a second ion implantation region 2IP in the underlying structure UDS exposed by the first opening 1OP and the second opening 2OP of the first mask pattern 1MP. For example, the ion implantation process may be performed by implanting nitrogen ions into the underlying structure UDS exposed by the first opening 1OP and the second opening 2OP. The first ion implantation region 1IP and the second ion implantation region 2IP of the underlying structure UDS implanted with nitrogen ions may become an amorphous silicon nitride layer (SixNy; where x and y are positive integers). Each first ion implantation region 1IP may have a first width 1WT that is the same as the width of each first opening 1OP. Each second ion implantation region 2IP may have a second width 2WT that is the same as the width of each second opening 2OP.

[0081] Reference Fig. 22 , a heat treatment process is performed to make the first ion implantation region 1IP and the second ion implantation region 2IP (see Fig.21 ) of the underlying structure UDS is recrystallized. The first ion implantation region 1IP and the second ion implantation region 2IP (see Fig.21 ) is used as the first etching stop pattern 1ES and the second etching stop pattern 2ES. For example, the first ion implantation region 1IP (see Figure 3 ) becomes the first etching stop pattern 1ES, and the second ion implantation region 2IP (see Figure 3 ) becomes the second etching stop pattern 2ES.

[0082] During the heat treatment process, ions implanted into the first ion implantation region 1IP and the second ion implantation region 2IP may diffuse into the underlying structure UDS, so that the size of the first etch stop pattern 1ES is larger than the size of the first ion implantation region 1IP, and the size of the second etch stop pattern 2ES is larger than the size of the second ion implantation region 2IP. The sizes of the first etch stop pattern 1ES and the second etch stop pattern 2ES may vary according to ion concentration.

[0083] Reference Fig.23, portions of the first etch stop pattern 1ES and the second etch stop pattern 2ES exposed through the first opening 1OP and the second opening 2OP of the first mask pattern 1MP may be oxidized to form an auxiliary etch stop pattern AES. For example, the outer or outermost portions of the first etch stop pattern 1ES and the second etch stop pattern 2ES may be oxidized to form the auxiliary etch stop pattern AES. The auxiliary etch stop pattern AES may be a silicon oxide layer (SixOy; where x and y are positive integers). As an oxidation process for forming the auxiliary etch stop pattern AES, a wet oxidation process or a dry oxidation process may be performed.

[0084] Reference Fig.24 , the target structure TGS and the second mask pattern 2MP may be sequentially stacked on the underlying structure UDS including the auxiliary etch stop pattern AES. For example, the target structure TGS may be formed of a single layer or multiple layers. In the second embodiment, the type and amount of materials forming the target structure TGS are not limited.

[0085] The second mask pattern 2MP may be composed of a photoresist pattern, or may be composed of a hard mask pattern and a photoresist pattern stacked on the hard mask pattern. For example, the hard mask pattern may be a mask layer formed of carbon. The second mask pattern 2MP may include a third opening 3OP and a fourth opening 4OP exposing a portion of the target structure TGS.

[0086] In the second mask pattern 2MP, in this example, each third opening 3OP is formed with a first width 1WT, and each fourth opening 4OP is formed with a second width 2WT greater than the first width 1WT. In this example, the area of ​​the target structure TGS exposed through the third openings 3OP of the second mask pattern 2MP is smaller than the area of ​​the target structure TGS exposed through the fourth openings 4OP.

[0087] Reference Fig.25 , an etching process may be performed to form a first hole 1HL and a second hole 2HL in the target structure TGS exposed by the third opening 3OP and the fourth opening 4OP of the second mask pattern 2MP. The etching process may be an anisotropic dry etching process. Because the area exposed by the fourth opening 4OP during the etching process of the target structure TGS is larger than the area exposed by the third opening 3OP, the second hole 2HL may be formed to have a deeper depth than the first hole 1HL, in other words, the second hole 2HL may be formed to have a height higher than the height of the formed first hole 1HL.

[0088] Therefore, before the auxiliary etch stop pattern AES is exposed through the first hole 1HL, the auxiliary etch stop pattern AES may be exposed through the second hole 2HL. Even if the auxiliary etch stop pattern AES is first exposed through the second hole 2HL, the etching process of the second hole 2HL may be suppressed while the etching process of forming the first hole 1HL is performed. Therefore, while the etching process of forming the first hole 1HL to the third depth 3DP (target depth) is performed, the depth of the second hole 2HL may be prevented from increasing beyond the target depth. The etching process may be performed until the auxiliary etch stop pattern AES or the first and second etch stop patterns 1ES and 2ES are exposed through the first and second holes 1HL and 2HL. For example, a central portion of the auxiliary etch stop pattern AES may be partially or completely removed, leaving the periphery of the auxiliary etch stop pattern AES, such as Fig.25 and Fig.26 shown.

[0089] Reference Fig.26 , the gap filling layer may be filled in the first hole 1HL and the second hole 2HL to form a first vertical structure 1VS and a second vertical structure 2VS contacting the first etch stop pattern 1ES and the second etch stop pattern 2ES, respectively. The first vertical structure 1VS and the second vertical structure 2VS may be formed of the same material to provide the same structure, or may be formed of different materials to provide different structures. For example, the first vertical structure 1VS may be formed in the first hole 1HL, and the second vertical structure 2VS may be formed in the second hole 2HL. Through the first etch stop pattern 1ES and the second etch stop pattern 2ES, the first vertical structure 1VS and the second vertical structure 2VS may be formed to have a third depth 3DP.

[0090] According to the present disclosure, an etch stop pattern and holes of different widths are easily formed at the same depth.

[0091] CROSS-REFERENCE TO RELATED APPLICATIONS

[0092] This application claims the priority of Korean Patent Application No. 10-2023-0122816 filed on September 15, 2023 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method for manufacturing a memory device, the method comprising the steps of: forming an ion implantation region in a portion of an outer portion of the underlying structure by implanting ions into the underlying structure; converting the ion implantation region into an etch stop pattern; forming a target structure on the underlying structure including the etch stop pattern; as well as performing an etching process to form a first hole and a second hole in the target structure, wherein a first width of the first hole is different from a second width of the second hole; Wherein, the etching process is performed until the etching stop pattern is exposed through the first hole and the second hole.

2. The method according to claim 1, wherein: The step of forming the ion implantation region comprises the following steps: forming a mask pattern including openings having different widths on the underlying structure; and The ions are implanted into a region within the underlying structure, the region being exposed through the opening.

3. The method according to claim 1, wherein: The ions are nitrogen ions.

4. The method according to claim 1, wherein: The ion implantation region includes a region where the ion concentration of ions is relatively high and a region where the ion concentration of ions is relatively low according to energy of the ion implantation process.

5. The method according to claim 1, wherein: A thermal treatment process is performed to transform the ion implantation region into the etch stop pattern.

6. The method according to claim 1, further comprising the steps of: Before forming the target structure, an auxiliary etch stop pattern is formed in a portion of an outer portion of the etch stop pattern.

7. The method according to claim 6, wherein: The auxiliary etch stop pattern is formed by performing a wet oxidation process or a dry oxidation process.

8. The method according to claim 1, wherein: When components of the etch stop pattern are detected during the etching process, conditions of the etching process are adjusted to increase etching selectivity of the target structure.

9. A method of manufacturing a memory device, the method comprising the steps of: forming an ion implantation region in a portion of an outer portion of the first underlying structure; performing a thermal treatment process for changing the ion implantation region into an etch stop pattern; alternately stacking first material layers and second material layers on the first underlying structure including the etch stop pattern; as well as A first hole exposing a first portion of the etch stop pattern and a second hole exposing a second portion of the etch stop pattern are formed in the first material layer and the second material layer, wherein the first hole has a first width, and wherein the second hole has a second width greater than the first width.

10. The method according to claim 9, wherein: When one of the first material layers contacts the etch stop pattern of the first underlying structure, an etch selectivity of the first material layer is greater than an etch selectivity of the etch stop pattern.

11. The method according to claim 9, wherein: The ion implantation region is formed by implanting nitrogen ions into the first underlying structure.

12. The method according to claim 11, wherein: The etch stop pattern is formed by recrystallizing the ion implantation region of the first underlying structure through the heat treatment process.

13. The method according to claim 9, wherein: The etch stop pattern is a silicon nitride layer.

14. The method according to claim 9, further comprising the steps of: After the heat treatment process is performed, a portion of an outer portion of the etch stop pattern is changed into an oxide layer.

15. The method according to claim 14, wherein: A wet oxidation process is performed to change the portion of the outer portion of the etch stop pattern into the oxide layer.

16. The method according to claim 14, wherein: A dry oxidation process is performed to change the portion of the outer portion of the etch stop pattern into the oxide layer.

17. The method according to claim 9, wherein: The first underlying structure is a silicon substrate.

18. The method according to claim 9, further comprising, after forming the first hole and the second hole: forming a cell plug in the first hole; forming a vertical structure in the second hole; replacing the second material layer with a third material layer to obtain a processing structure having a first end and a second end opposite to the first end, wherein the first underlying structure is disposed at the first end of the processing structure; contacting the second end of the handling structure with a peripheral structure; removing a substrate included in the first underlying structure to expose the etch stop pattern; as well as The etch stop pattern exposed by the removal of the substrate is removed.

19. The method according to claim 18, wherein: The peripheral structure includes a second underlying structure and a peripheral circuit formed on the second underlying structure.

20. A memory device, the memory device comprising: an underlying structure including a first etch stop pattern and a second etch stop pattern; as well as a target structure formed above the underlying structure, wherein a first hole having a first aspect ratio and a second hole having a second aspect ratio less than the first aspect ratio are formed in the target structure, wherein the first etch stop pattern is exposed through the first hole and the second etch stop pattern is exposed through the second hole; wherein the first etch stop pattern and the second etch stop pattern include etch stop ions for stopping an etching process; and The second etching stop pattern includes a region having a high concentration of etching stop ions and a region having a low concentration of etching stop ions.

21. The memory device of claim 20, wherein: A concentration of the etch stop ions in the first etch stop pattern is uniform.

22. The memory device of claim 20, wherein: The etch stop ions include nitrogen ions.

23. The memory device of claim 20, wherein: Each of the first hole and the second hole has a circular shape, an elliptical shape, or a linear shape.

24. A method of manufacturing a memory device, the method comprising the steps of: forming a target structure above an underlying structure; forming a mask pattern over the target structure; implanting etch stop ions into the underlying structure through the target structure using the mask pattern to form a first etch stop pattern and a second etch stop pattern; as well as etching the target structure using the mask pattern until the first etch stop pattern is exposed to form a first hole having a first aspect ratio, and etching the target structure until the second etch stop pattern is exposed to form a second hole having a second aspect ratio less than the first aspect ratio; Wherein, when the etching stop ions are implanted, the second etching stop pattern includes a region having a high concentration of etching stop ions and a region having a low concentration of etching stop ions.

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