Chip packaging structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a chip packaging structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor packaging, and aims to solve the problem of low integration level of a storage device. The chip packaging structure comprises a substrate, an adapter plate, a first semiconductor assembly and a second semiconductor assembly. The substrate and the adapter plate are oppositely arranged, the first semiconductor assembly and the second semiconductor assembly are arranged between the substrate and the adapter plate, the first semiconductor assembly is connected with the substrate, the second semiconductor assembly is connected with the adapter plate, and the substrate and the adapter plate are connected through a plurality of connecting wires.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] With the development of the electronics industry, the demand for high-performance, high-speed and compact chip packaging structures in electronic devices continues to increase. Summary of the invention

[0003] Embodiments of the present disclosure provide a chip packaging structure and a method for manufacturing the same, a storage system, and an electronic device, aiming to solve the problem of low integration of storage devices.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, a chip packaging structure is provided. The chip packaging structure includes a substrate, an adapter board, a first semiconductor component and a second semiconductor component. The adapter board is arranged opposite to the substrate. The first semiconductor component and the second semiconductor component are arranged between the substrate and the adapter board, the first semiconductor component is connected to the substrate, and the second semiconductor component is connected to the adapter board. The substrate and the adapter board are connected by a plurality of connecting wires.

[0006] In the disclosed embodiment, the substrate is only connected to the first semiconductor component, and the second semiconductor component is connected to the adapter board. Compared with the embodiment in which both the first semiconductor component and the second semiconductor component are connected to the substrate, the wiring density in the substrate of the present embodiment is reduced, the number of wirings that can be set in the substrate is increased, and the number of semiconductor structures of the first semiconductor component connected to the substrate is increased; coupled with the number of wirings that can be set on the adapter board, the adapter board can be connected to the semiconductor structure of the second semiconductor component, thereby increasing the number of semiconductor structures accommodated between the substrate and the adapter board, thereby improving the integration of the chip packaging structure, and further improving the integration of the storage device.

[0007] In some embodiments, the first semiconductor component includes a plurality of first semiconductor structures arranged in a stacked manner, and the second semiconductor component includes a plurality of second semiconductor structures arranged in a stacked manner.

[0008] In some embodiments, the first semiconductor component includes a plurality of first conductive pillars, the first ends of the first conductive pillars are connected to the substrate, the second ends of the first conductive pillars penetrate into the first semiconductor structure, and the sidewalls of the first conductive pillars are provided with a dielectric layer. The second semiconductor component includes a plurality of second conductive pillars, the first ends of the second conductive pillars are connected to the adapter plate, the second ends of the second conductive pillars penetrate into the second semiconductor structure, and the sidewalls of the second conductive pillars are provided with a dielectric layer.

[0009] In some embodiments, the first semiconductor structure includes one of a DRAM cell and a NAND cell, and the second semiconductor structure includes the other of the DRAM cell and the NAND cell. The chip package structure further includes an adhesive layer disposed between the first semiconductor component and the second semiconductor component.

[0010] In some embodiments, the first semiconductor structure includes a DRAM cell and the second semiconductor structure includes a NAND cell.

[0011] In some embodiments, the DRAM cell includes: a DRAM array layer and a DRAM peripheral device layer stacked. When the first semiconductor structure includes the DRAM cell, the second end of the first conductive column penetrates to the interface between the DRAM array layer and the DRAM peripheral device layer of the first semiconductor structure. When the second semiconductor structure includes the DRAM cell, the second end of the second conductive column penetrates to the interface between the DRAM array layer and the DRAM peripheral device layer of the second semiconductor structure.

[0012] In some embodiments, the NAND cell includes: a NAND array layer and a NAND peripheral device layer stacked in layers. When the first semiconductor structure includes the NAND cell, the NAND peripheral device layer is closer to the substrate than the NAND array layer; the second end of the first conductive pillar penetrates the NAND array layer of the first semiconductor structure. When the second semiconductor structure includes the NAND cell, the NAND peripheral device layer is closer to the adapter board than the NAND array layer; the second end of the second conductive pillar penetrates the NAND array layer of the second semiconductor structure.

[0013] In some embodiments, orthographic projections of the plurality of first semiconductor structures and the plurality of second semiconductor structures on the substrate coincide with each other.

[0014] In some embodiments, the connection between the substrate and the first semiconductor component, and between the transfer plate and the second semiconductor component includes hybrid bonding or welding.

[0015] In some embodiments, the connection between adjacent first semiconductor structures in the first semiconductor component includes hybrid bonding or welding, and / or the connection between adjacent second semiconductor structures in the second semiconductor component includes hybrid bonding or welding.

[0016] In some embodiments, the connecting line includes gold fingers, and the substrate and the adapter board are connected via a plurality of gold fingers.

[0017] In some embodiments, the chip packaging structure further includes a filling portion, which is formed between the substrate and the adapter plate and filled between the plurality of connection lines.

[0018] In some embodiments, the chip packaging structure further includes: a ball grid array located on a side of the substrate away from the adapter board. The substrate is connected to the circuit board through the ball grid array.

[0019] In another aspect, a storage system is provided, which includes the chip packaging structure and a controller as described in some of the above embodiments, wherein the controller is coupled to the chip packaging structure to control the chip packaging structure to store data.

[0020] In another aspect, an electronic device is provided, wherein the electronic device comprises the storage system according to some of the above embodiments.

[0021] In another aspect, a method for preparing a chip packaging structure is provided. The method for preparing a chip packaging structure includes: forming a first semiconductor component and a second semiconductor component; placing the first semiconductor component and the second semiconductor component on an adapter board, and connecting the second semiconductor component to the adapter board; forming a connecting wire, and connecting the connecting wire to the adapter board; placing a substrate on a side of the first semiconductor component away from the adapter board, and connecting the first semiconductor component and the connecting wire to the substrate.

[0022] In some embodiments, forming a first semiconductor component and a second semiconductor component includes: forming a first semiconductor structure and a second semiconductor structure. At least one first sub-conductive column is formed in the first semiconductor structure, and at least one second sub-conductive column is formed in the second semiconductor structure, and a dielectric layer is provided on the sidewalls of the first sub-conductive column and the second sub-conductive column. A plurality of first semiconductor structures are stacked to form a first semiconductor component, and at least one first sub-conductive column is stacked in the thickness direction of the first semiconductor component to form a first conductive column, and the first end of the first conductive column is exposed to the surface of the first semiconductor component, and the second end of the first conductive column penetrates into a first semiconductor structure. A plurality of second semiconductor structures are stacked to form a second semiconductor component; at least one second sub-conductive column is stacked in the thickness direction of the second semiconductor component to form a second conductive column, and the first end of the second conductive column is exposed to the surface of the second semiconductor component, and the second end of the second conductive column penetrates into a second semiconductor structure.

[0023] In some embodiments, forming a first semiconductor component and a second semiconductor component includes: forming an initial first semiconductor component and an initial second semiconductor component. The initial first semiconductor component includes a plurality of first semiconductor structures arranged in a stacked manner, and the initial second semiconductor component includes a plurality of second semiconductor structures arranged in a stacked manner. A plurality of first conductive pillars are formed in the initial first semiconductor component to form a first semiconductor component; the first end of the first conductive pillar is exposed to the surface of the first semiconductor component, the second end of the first conductive pillar penetrates into a first semiconductor structure, and a dielectric layer is provided on the sidewall of the first conductive pillar. A plurality of second conductive pillars are formed in the initial second semiconductor component to form a second semiconductor component; the first end of the second conductive pillar is exposed to the surface of the second semiconductor component, the second end of the second conductive pillar penetrates into a second semiconductor structure, and a dielectric layer is provided on the sidewall of the second conductive pillar.

[0024] In some embodiments, the first semiconductor component includes a plurality of first semiconductor structures, and the second semiconductor component includes a plurality of second semiconductor structures.

[0025] In the case where the first semiconductor structure includes a DRAM unit, a first semiconductor component is formed, including: forming a plurality of first semiconductor structures, including: forming a DRAM array layer and a DRAM peripheral device layer; forming a first semi-conductive column in the DRAM array layer, and forming a second semi-conductive column in the DRAM peripheral device layer; stacking the DRAM array layer and the DRAM peripheral device layer to form a first semiconductor structure. A plurality of first semiconductor structures are stacked to form a first semiconductor component, at least one semi-conductive column is stacked in the thickness direction of the first semiconductor component to form a first conductive column, and the second end of the first conductive column penetrates to the interface between the DRAM array layer and the DRAM peripheral device layer of a first semiconductor structure. The semi-conductive column includes a first semi-conductive column and a second semi-conductive column.

[0026] In the case where the second semiconductor structure includes a DRAM unit, forming a second semiconductor component includes: forming a plurality of second semiconductor structures, including: forming a DRAM array layer and a DRAM peripheral device layer; forming a third semiconductive column in the DRAM array layer, forming a fourth semiconductive column in the DRAM peripheral device layer; stacking the DRAM array layer and the DRAM peripheral device layer to form a second semiconductor structure. Stacking a plurality of second semiconductor structures to form a second semiconductor component; at least one semiconductive column is stacked in the thickness direction of the second semiconductor component to form a second conductive column; the second end of the second conductive column penetrates to the interface between the DRAM array layer and the DRAM peripheral device layer of a second semiconductor structure; the semiconductive column includes a third semiconductive column and a fourth semiconductive column.

[0027] In some embodiments, the first semiconductor component includes a plurality of first semiconductor structures, and the second semiconductor component includes a plurality of second semiconductor structures.

[0028] In the case where the first semiconductor structure includes a NAND unit, forming a first semiconductor component includes: forming a plurality of first semiconductor structures, including: forming a NAND array layer and a NAND peripheral device layer; forming a fifth semiconductive column in the NAND array layer, forming a sixth semiconductive column in the NAND peripheral device layer; stacking the NAND array layer and the NAND peripheral device layer to form a first semiconductor structure. Stacking a plurality of first semiconductor structures to form a first semiconductor component; at least one semiconductive column is stacked in the thickness direction of the first semiconductor component to form a first conductive column; the second end of the first conductive column penetrates a NAND array layer of the first semiconductor structure; the semiconductive column includes a fifth semiconductive column and a sixth semiconductive column.

[0029] In the case where the second semiconductor structure includes a NAND unit, forming a second semiconductor component includes: forming a plurality of second semiconductor structures, including: forming a NAND array layer and a NAND peripheral device layer; forming a seventh semiconductive column in the NAND array layer, forming an eighth semiconductive column in the NAND peripheral device layer; stacking the NAND array layer and the NAND peripheral device layer to form a second semiconductor structure. Stacking a plurality of second semiconductor structures to form a second semiconductor component, at least one semiconductive column is stacked in the thickness direction of the second semiconductor component to form a second conductive column, the second end of the second conductive column penetrates into a NAND array layer of a second semiconductor structure, and the semiconductive column includes a seventh semiconductive column and an eighth semiconductive column.

[0030] In some embodiments, after forming the connecting wires, the method for preparing the chip packaging structure further includes: forming a filling portion, wherein the filling portion fills between the connecting wires.

[0031] It can be understood that the beneficial effects that can be achieved by the chip packaging structure preparation method, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the chip packaging structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0033] Figure 1 is a block diagram of a storage system according to some embodiments;

[0034] Figure 2 is a structural diagram of a storage system according to some embodiments;

[0035] Figure 3 Structural diagram of chip packaging structure provided for related technology;

[0036] Figure 4 is a structural diagram of a chip packaging structure according to some embodiments;

[0037] Figure 5 for Figure 4 Enlarged view of point A in the middle;

[0038] Figure 6 is a top view of an adapter plate according to some embodiments;

[0039] Figure 7 is a structural diagram of a first semiconductor component according to some embodiments;

[0040] Figure 8 for Figure 7 Enlarged view of point B in the middle;

[0041] Fig. 9 is a structural diagram of a second semiconductor component according to some embodiments;

[0042] Fig.10 A flow chart of a method for preparing a chip packaging structure provided for some embodiments of the present disclosure;

[0043] Figures 11A to 18 It is a structural diagram corresponding to each step in the method for preparing a chip packaging structure according to some embodiments;

[0044] Figures 19A to 19C A structural diagram corresponding to each step of forming a first semiconductor component in a method for preparing a chip packaging structure according to some embodiments;

[0045] Figure 20A to Figure 20C A structural diagram corresponding to each step of forming a second semiconductor component in a method for preparing a chip packaging structure according to some embodiments;

[0046] Figures 21A to 21D A structural diagram corresponding to each step of forming a first semiconductor component in a method for preparing a chip packaging structure according to some embodiments;

[0047] Figures 22A to 22D It is a structural diagram corresponding to each step of forming a second semiconductor component in a method for preparing a chip packaging structure according to some embodiments. DETAILED DESCRIPTION

[0048] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0049] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0052] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0053] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0054] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0055] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0056] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0057] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0058] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0059] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0060] Some embodiments of the present disclosure provide an electronic device. The electronic device may be any one of a mobile phone (e.g., a mobile phone), a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, a printer, a positioning device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, etc.

[0061] The electronic device may include a storage system, and may also include at least one of a central processing unit (CPU) and a cache.

[0062] Figure 1 is a block diagram of a storage system according to some embodiments. Figure 2 is a structural diagram of a storage system according to some embodiments.

[0063] See also Figure 1 and Figure 2 Some embodiments of the present disclosure provide a storage system 1000. The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic devices, such as the electronic devices described above.

[0064] In some embodiments, the storage system 1000 may be integrated into a memory card, which may include a PC (i.e., PCMCIA, Personal Computer Memory Card International Association) card, a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), or a Universal Flash Storage (UFS) card.

[0065] In other embodiments, the storage system 1000 is integrated into solid state drives (SSDs).

[0066] The storage system 1000 includes a chip packaging structure 100 and a controller 200, and may also include a circuit board. The circuit board is connected to the chip packaging structure 100, and the circuit board may be a flexible printed circuit (FPC) or a rigid printed circuit board (PCB).

[0067] The controller 200 is coupled to the chip package structure 100. In some embodiments, the controller 200 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0068] In other embodiments, the controller 200 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0069] In some embodiments, the controller 200 may be configured to control operations of the chip package structure 100, such as read, erase, and program operations. In some embodiments, the controller 200 may also be configured to manage various functions regarding data stored or to be stored in the chip package structure 100, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 200 is also configured to process error correction codes regarding data read from or written to the chip package structure 100. Of course, the controller 200 may also perform any other suitable functions, such as formatting the chip package structure 100.

[0070] In some embodiments, the controller 200 may also be configured to communicate with an external device (e.g., a host), for example, the controller 200 may communicate with the external device via at least one of various interface protocols. It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a Firewire protocol.

[0071] The chip packaging structure 100 provided by some embodiments of the present disclosure is schematically described below in conjunction with the accompanying drawings.

[0072] Figure 3 A structural diagram of a chip packaging structure provided for related technology.

[0073] In the related art, see Figure 3 The chip packaging structure 100' includes a substrate 30' and a chipset 10' disposed on the substrate 30'. The chipset 10' includes a plurality of chips. In order to realize interconnection communication between chips, each chip of the chipset 10' is connected to the substrate 30'. As the number of chips increases, the number of wirings in the substrate 30' increases, and the wiring complexity increases. However, the size of the substrate 30' is limited after all, and the number of wirings in the substrate 30' is limited. Therefore, the number of chips that can be connected to the substrate 30' is limited, which cannot meet the requirements of high-density interconnection of chips, and is not conducive to improving the integration of memory devices.

[0074] In order to solve the above technical problems, some embodiments of the present disclosure provide a chip packaging structure 100, which connects a plurality of semiconductor structures originally connected only to a substrate to the substrate and an adapter plate respectively, so as to improve the integration of a memory device.

[0075] Figure 4 is a structural diagram of a chip packaging structure according to some embodiments.

[0076] See also Figure 4 The chip packaging structure 100 includes a plurality of (e.g., two, or more) semiconductor structures, a substrate 30, and an adapter plate 40. The substrate 30 and the adapter plate 40 are arranged opposite to each other. Exemplarily, the plane where the substrate 30 is located is substantially parallel to the plane where the adapter plate 40 is located. For example, the angle between the plane where the substrate 30 is located and the plane where the adapter plate 40 is located may be less than or equal to 5 degrees; for example, less than or equal to 3 degrees.

[0077] The semiconductor structure includes an array layer and a peripheral device layer which are stacked, and the peripheral device layer is electrically connected to the array layer. The array layer includes a core area and a connection area, and the core area is provided with a plurality of channel structures for signal transmission; the core area and the connection area may be adjacent. The peripheral device layer is configured to receive signals from the outside of the semiconductor structure, such as an address signal ADDR, a command signal CMD, a control signal CTRL, and a data signal DA, and in response to the signals, input signals to the array layer and / or receive signals from the array layer, so that the semiconductor structure can perform storage operations, such as read operations, program operations, and erase operations.

[0078] The semiconductor structure may be a NAND Flash Memory cell, a Dynamic Random Access Memory (DRAM) cell, and a Static Random-Access Memory (SRAM) cell, or may be other suitable memory cells. When the semiconductor structure is a NAND cell, the NAND cell includes a stacked NAND array layer and a NAND peripheral device layer. When the semiconductor structure is a DRAM cell, the DRAM cell includes a stacked DRAM array layer and a DRAM peripheral device layer.

[0079] The plurality of semiconductor structures are divided into a first semiconductor component 10 and a second semiconductor component 20 . The first semiconductor component 10 includes a plurality of (eg, two or more) first semiconductor structures D1 , and the second semiconductor component 20 includes a plurality of (eg, two or more) second semiconductor structures D2 .

[0080] The first semiconductor structure D1 and the second semiconductor structure D2 may be the same. Exemplarily, the first semiconductor structure D1 and the second semiconductor structure D2 are both NAND cells; and further exemplary, the first semiconductor structure D1 and the second semiconductor structure D2 are both DRAM cells.

[0081] The first semiconductor structure D1 and the second semiconductor structure D2 may be different. For example, the first semiconductor structure D1 is one of a DRAM cell and a NAND cell, and the second semiconductor structure D2 is the other of the DRAM cell and the NAND cell.

[0082] In some implementations, the first semiconductor structure D1 or the second semiconductor structure D2 may also be a SRAM cell.

[0083] The substrate 30 is used to provide electrical support for the semiconductor structure. The substrate 30 includes an insulating layer and a plurality of wiring layers. The wiring layer is configured to provide electrical signals to the connected semiconductor structure. The wiring layer is formed with fine wiring. The material of the wiring is a conductive material. The conductive material may include at least one of gold (Au), silver (Ag), aluminum (Al), copper (Cu), zinc (Zn), tin (Sn), lead (Pb), antimony (Sb), bismuth (Bi), lithium (Li), gallium (Ga) and cadmium (Cd), or an alloy containing two or more metal elements. The insulating material is located between the wiring of the wiring layer. The wiring of different wiring layers can be connected by through holes. The insulating layer is provided between the plurality of wiring layers. The material of the insulating layer is an insulating material, and the insulating material may include at least one of polysilicon (Si), silicon oxide, glass, polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyethylene naphthalatetwo formic acid glycol ester (PEN), ultra-thin glass or polyimide (PI), etc.

[0084] The substrate 30 is connected to the first semiconductor component 10 . Specifically, each first semiconductor structure D1 is connected to a wiring of the substrate 30 .

[0085] The adapter plate 40 is used to provide electrical support for the semiconductor structure. The structure and material of the adapter plate 40 can refer to the structure and material of the substrate 30 mentioned above. The second semiconductor assembly 20 is connected to the adapter plate 40. Specifically, each second semiconductor structure D2 is connected to the wiring of the adapter plate 40 respectively.

[0086] In some examples, the adapter board 40 can be a silicon interposer (Si Interposer), and wiring on the silicon interposer can achieve micron and submicron line width and line spacing, meeting the needs of high-density interconnection between multiple semiconductor structures. The silicon interposer includes a silicon substrate and a redistributed layer (RDL). The RDL layer is arranged on the side of the silicon substrate away from the substrate. A plurality of through silicon vias (TSV) are provided on the silicon substrate, and a conductive material is deposited in the through silicon via to form a conductive portion, which is connected to the RDL layer. The conductive material can be selected from the conductive materials introduced above, which will not be repeated here.

[0087] In some other examples, the adapter plate can also be an oxide-metal-oxide-metal (OMOM) layer. The metal can be a metal element, such as Ti, or a conductive metal salt, in particular a conductive metal nitride, such as TiN. The oxide can be silicon oxide, such as silicon dioxide (SiO2). A through hole is provided on the OMOM layer, and a conductive material is deposited in the through hole to form a conductive portion, so that each second semiconductor structure D2 is connected to the metal layer through the conductive portion.

[0088] In some implementations, the substrate 30 may also be a silicon interposer or an OMOM layer.

[0089] A plurality of semiconductor structures are arranged between the substrate 30 and the adapter plate 40. Exemplarily, the first semiconductor component 10 and the second semiconductor component 20 are stacked between the substrate 30 and the connecting plate 40. It can be understood that the stacking arrangement here refers to the stacking of the first semiconductor component 10 and the second semiconductor component 20 along the thickness direction (hereinafter referred to as the first direction) of the substrate 30. For example, the first semiconductor component 10 is arranged between the second semiconductor component 20 and the substrate 30, and the second semiconductor component 20 is arranged between the first semiconductor component 10 and the adapter plate 40. For another example, the first semiconductor component 10 is arranged between the second semiconductor component 20 and the adapter plate 40, and the second semiconductor component 20 is arranged between the first semiconductor component 10 and the substrate 30.

[0090] As another example, the first semiconductor component 10 and the second semiconductor component 20 are arranged flat between the substrate 30 and the adapter plate 40. It can be understood that the flat arrangement here refers to the first semiconductor component 10 and the second semiconductor component 20 being arranged along the extension direction of the substrate 30 (hereinafter referred to as the second direction). The first semiconductor component 10 is located on the left side of the second semiconductor component 20, or the second semiconductor component 20 is located on the left side of the first semiconductor component 10. For example, the upper and lower sides of the first semiconductor component 10 are the substrate 30 and the adapter plate 40, respectively, and the second semiconductor component 20 is not arranged between the first semiconductor component 10 and the substrate 30, and the second semiconductor component 20 is not arranged between the first semiconductor component 10 and the adapter plate 40; the upper and lower sides of the second semiconductor component 20 are the substrate 30 and the adapter plate 40, respectively, and the first semiconductor component 10 is not arranged between the second semiconductor component 20 and the substrate 30, and the first semiconductor component 10 is not arranged between the second semiconductor component 20 and the adapter plate 40.

[0091] Figure 5 for Figure 4 Enlarged view of point A in the middle.

[0092] The substrate 30 and the adapter board 40 are connected by a plurality of connecting wires 50. The connecting wires 50 are conductive structures for transmitting signals between the substrate 30 and the adapter board 40. Figure 4 and Figure 5 , one end of the connecting wire 50 is connected to the side of the substrate 30 close to the adapter board 40, and the other end of the connecting wire 50 is connected to the side of the adapter board 40 close to the substrate 30. Exemplarily, the connecting wire 50 includes contact pads 51 provided at both ends, the substrate 30 is connected to the connecting wire 50 through the contact pads 51, and the adapter board 40 is connected to the connecting wire 50 through the contact pads 51. The material of the connecting wire 50 includes a conductive material, and the conductive material can be selected from the conductive materials described above, which will not be repeated here.

[0093] In some embodiments, the connection line 50 includes a gold finger. The gold finger is composed of a plurality of golden conductive contacts arranged like fingers, one end of the conductive contact is connected to the substrate 30, and the other end is connected to the adapter board 40. The signal between the substrate 30 and the adapter board 40 is transmitted through the gold finger. The conductive contact increases the contact area between the substrate 30 and the adapter board 40 and the connection line 50, thereby reducing the contact resistance and improving the signal transmission efficiency.

[0094] Continue to see Figure 4 The signal of the first semiconductor component 10 is transmitted to the substrate 30, the signal of the second semiconductor component 20 is transmitted to the adapter board 40, the signal of the adapter board 40 is transmitted to the substrate 30 via the connecting line 50, and the substrate 30 transmits the signals of the first semiconductor component 10 and the second semiconductor component 20 to the circuit board.

[0095] In the embodiment of the present disclosure, a part of the semiconductor structures (first semiconductor structures D1) among the plurality of semiconductor structures is connected to the substrate 30, and another part of the semiconductor structures (second semiconductor structures D2) among the plurality of semiconductor structures is connected to the adapter board 40. The wiring density in the substrate 30 is reduced, the number of wirings that can be set in the substrate 30 is increased, and the number of semiconductor structures of the first semiconductor assembly 10 connected to the substrate 30 is increased; in addition, wirings can also be set on the adapter board 40, so that the adapter board 40 can also be connected to a part of the semiconductor structure, the number of semiconductor structures accommodated between the substrate 30 and the adapter board 40 is increased, the integration of the chip packaging structure 100 is improved, and then the integration of the storage device is improved, so as to meet the requirements of microelectronic products for multi-function and miniaturization, and achieve high-density integration.

[0096] Figure 6 is a top view of an adapter plate according to some embodiments.

[0097] In some embodiments, see Figure 2 , the controller of the storage system 1000 is disposed between the substrate 30 and the adapter board 40 of the chip package structure 100. The circuit board is connected to the substrate 30. In order to reduce the wiring density in the substrate 30, the controller 200 can be connected to the adapter board 40. For example, see Figure 6, a first area P1 and a second area P2 are provided on the adapter board 40, the first area P1 is used to connect the controller 200, and the second area P2 is used to connect the second semiconductor component 20. The conductive portion of the adapter board 40 exposed on the surface of the adapter board 40 is a conductive contact. The first area P1 and the second area P2 include a plurality of conductive contacts. The controller 200 includes a plurality of pins, which are connected to the conductive contacts of the first area P1. The pins are directly connected to the conductive contacts, and the pins can also be connected to the conductive contacts through leads, so as to realize the electrical connection between the controller 200 and the chip packaging structure 100. In some implementations, the pins of the controller 200 can also be directly connected to the substrate 30. The controller 200 uses the gap between the substrate 30 and the adapter board 40 to reduce the packaging space occupied by the controller 200, thereby reducing the volume occupied by the storage system 1000, and meeting the requirements of miniaturization of electronic devices.

[0098] In some embodiments, see Figure 4 , the first semiconductor component 10 includes a plurality of first semiconductor structures D1 stacked in layers. Exemplarily, the plurality of first semiconductor structures D1 are stacked in an offset manner. For example, the plurality of first semiconductor structures D1 are stacked in a step-like manner along a first direction, and a bonding space is provided by utilizing the offset height difference, and each first semiconductor structure D1 is provided with a lead in the bonding space without affecting each other. Also exemplarily, the plurality of first semiconductor structures D1 are stacked in sequence along the first direction, and the projection area of ​​the first semiconductor component 10 on the substrate 30 does not exceed the maximum projection area of ​​the first semiconductor structure D1 on the substrate 30.

[0099] When the number of first semiconductor structures D1 is the same, multiple first semiconductor structures D1 are stacked, so that the size of the first semiconductor component 10 along the second direction is smaller than the first semiconductor component 10 with multiple first semiconductor structures D1 laid flat, and the projection area of ​​the first semiconductor component 10 on the substrate 30 is reduced, which can save the bearing size of the substrate 30, and correspondingly reduce the design size of the substrate 30, thereby reducing the package size of the chip packaging structure 100, which is conducive to the miniaturization of the chip packaging structure 100 and improves product performance. In addition, along the second direction, with the same package size, the number of multiple stacked first semiconductor structures D1 is greater than the number of multiple laid first semiconductor structures D1, the number of first semiconductor structures D1 in the chip packaging structure 100 increases, and the integration of the memory device is higher.

[0100] Continue to see Figure 4The second semiconductor component 20 includes a plurality of second semiconductor structures D2 arranged in a stacked manner. Exemplarily, the plurality of second semiconductor structures D2 are stacked in an offset manner. For example, the plurality of second semiconductor structures D2 are stacked in a step-like manner in a first direction, and a bonding space is provided by utilizing the offset height difference. Each second semiconductor structure D2 is provided with a lead in the bonding space and does not affect each other. Also exemplarily, the plurality of second semiconductor structures D2 are stacked in a first direction, and the projection area of ​​the second semiconductor component 20 on the substrate 30 does not exceed the maximum projection area of ​​the second semiconductor structure D2 on the substrate 30.

[0101] In the case where the number of second semiconductor structures D2 is the same, the size of the second semiconductor component 20 in which multiple second semiconductor structures D2 are stacked along the second direction is smaller than the second semiconductor component 20 in which multiple second semiconductor structures D2 are laid flat, and the projection area of ​​the second semiconductor component 20 on the adapter plate 40 is reduced, thereby saving the bearing size of the adapter plate 40, and correspondingly reducing the design size of the adapter plate 40, thereby reducing the packaging size of the chip packaging structure 100, which is conducive to the miniaturization of the chip packaging structure 100 and improving product performance. In addition, in the case of the same packaging size along the second direction, the number of multiple second semiconductor structures D2 in stacked arrangement is greater than the number of multiple second semiconductor structures D2 in laid flat arrangement, the number of second semiconductor structures D2 in the chip packaging structure 100 increases, and the integration of the storage device is higher.

[0102] In some embodiments, see Figure 4 , the orthographic projections of the plurality of first semiconductor structures D1 and the plurality of second semiconductor structures D2 on the substrate overlap. The orthographic projections of the first semiconductor component 10 and the second semiconductor component 20 on the substrate overlap, so that the first semiconductor component 10 and the second semiconductor component 20 are perpendicular to the plane where the substrate 30 is located, and the size of the semiconductor structure as a whole in the extension direction of the substrate 30 is minimized to the greatest extent, thereby reducing the packaging space occupied by the semiconductor structure, and further reducing the volume of the chip packaging structure 100, thereby minimizing the size of the memory device.

[0103] In the related art, continue to see Figure 3 , each chip is connected to the bottom substrate 30' of the chipset 10' by wires. However, this connection method requires that the connection position of the wires be reserved at the edge of the chip, and the wires need to occupy a certain packaging space, so there is a certain limit on the density of the wires, which in turn limits the number of chips; and the wires connecting the chip and the substrate 30' are long, which makes the signal transmission path longer and the transmission speed slower, resulting in high transmission delay and low bandwidth.

[0104] Figure 7 is a structural diagram of a first semiconductor component according to some embodiments. Figure 8 for Figure 7Enlarged view of point B in the middle. Fig. 9 is a structural diagram of a second semiconductor component according to some embodiments.

[0105] In some embodiments, to solve the above problems, see Figure 4 , a plurality of conductive pillars are provided in the first semiconductor component 10 and the second semiconductor component 20, one end of the conductive pillar is connected to the substrate 30 or the adapter plate 40, the other end penetrates into the semiconductor structure, and the end face contacts the semiconductor structure. The conductive pillar can be perpendicular to the substrate 30, in which case the connection distance between the semiconductor structure and the substrate 30 is the shortest. The signal of the semiconductor structure is transmitted to the substrate 30 or the adapter plate 40 via the conductive pillar. The material of the conductive pillar is a conductive material, which can be selected from the conductive materials described above and will not be described in detail here. The side wall of the conductive pillar is provided with a dielectric layer ( Figure 4 The dielectric layer is made of an insulating material, such as silicon oxide, silicon nitride, and a combination of one or more high dielectric constant insulating materials, or other suitable materials. The dielectric layer separates the conductive pillar from the semiconductor structure. It is understandable that in order to protect the channel structure in the semiconductor structure, the conductive pillar is disposed in the core area of ​​the semiconductor structure, and there is a gap between the conductive pillar and the channel structure.

[0106] Specifically, see Figure 4 , Figure 7 and Figure 8 For the first semiconductor component 10, the first semiconductor component 10 includes a plurality of (for example, one, or more) first conductive pillars 11. The sidewall of the first conductive pillar 11 is provided with a dielectric layer 102. The first end 111 of the first conductive pillar is connected to the substrate 30. For example, the end surface of the first end 111 of the first conductive pillar is exposed to the surface of the first semiconductor component 10 close to the substrate 30 (hereinafter referred to as the upper surface of the first semiconductor component 10), and the end surface of the first end 111 is provided with a pad 101, and the substrate 30 is connected to the first end 111 of the first conductive pillar through the pad 101. For another example, the end surface of the first end 111 of the first conductive pillar is directly connected to the substrate 30.

[0107] The second end 112 of the first conductive pillar penetrates into a first semiconductor structure D1, that is, the end surface of the second end 112 of the first conductive pillar is connected to a first semiconductor structure D1 in the first semiconductor component 10. For the convenience of the following description, the first semiconductor structure D1 connected to the end surface of the second end 112 of the first conductive pillar is called the first connection semiconductor of the first conductive pillar. The second end 112 of the first conductive pillar penetrates the first semiconductor structure D1 between the first connection semiconductor and the substrate 30. The closer to the substrate 30, the shorter the length of the first conductive pillar of the first connection semiconductor.

[0108] Exemplarily, the first semiconductor component 10 includes first semiconductor structures D1a, D1b, and D1c stacked in sequence, wherein the first semiconductor structure D1a is farthest from the substrate 30, and the first semiconductor structure D1c is closest to the substrate 30. The first end 111a of the first conductive pillar 11a is exposed to the upper surface of the first semiconductor component 10, and the end surface of the second end 112a of the first conductive pillar 11a is connected to the first semiconductor structure D1a. At this time, the first connection semiconductor of the first conductive pillar 11a is the first semiconductor structure D1a. The first semiconductor structures D1c and D1b stacked are between the first semiconductor structure D1a and the substrate 30. The second end 112a of the first conductive pillar 11a penetrates the first semiconductor structures D1c and D1b and extends into the first connection semiconductor, so that the second end 112a of the first conductive pillar is connected to the first semiconductor structure D1a. In this way, the signal of the first connection semiconductor is transmitted from the end surface of the second end 112a of the first conductive pillar through the first conductive pillar 11a to the substrate 30.

[0109] The first end 111b of the first conductive pillar 11b is exposed on the upper surface of the first semiconductor component 10, and the end surface of the second end 112b of the first conductive pillar 11b is connected to the first semiconductor structure D1b. At this time, the first semiconductor structure D1b is the first connection semiconductor of the first conductive pillar 11b. The first conductive pillar 11b penetrates the first semiconductor structure D1c and extends into the first connection semiconductor, so that the second end 112b of the first conductive pillar is connected to the first semiconductor structure D1b. The first conductive pillar 11b does not extend into the first semiconductor structure D1a, that is, the first semiconductor structure D1a is connected to the substrate 30 only through the first conductive pillar 11a penetrating the first semiconductor structure D1a, and the first semiconductor structure D1b is connected to the substrate 30 only through the first conductive pillar 11b penetrating the first semiconductor structure D1b.

[0110] The first end 111c of the first conductive column 11c is exposed on the upper surface of the first semiconductor component 10, and the end surface of the second end 112c of the first conductive column 11c is connected to the first semiconductor structure D1c. At this time, the first semiconductor structure D1c is the first connection semiconductor of the first conductive column 11c. Since there is no other semiconductor structure between the first semiconductor structure D1c and the substrate 30, the first conductive column 11c only extends into the first semiconductor structure D1c and does not penetrate any first semiconductor structure D1. The embodiment of the present disclosure only takes three first semiconductor structures D1 as an example. The connection of other numbers of first semiconductor structures D1 to the substrate 30 through conductive columns can be referred to the above description, which will not be repeated here.

[0111] The number of the first conductive pillars 11 is at least the same as the number of the first semiconductor structures D1 in the first semiconductor component 10, and each first semiconductor structure D1 is connected to the substrate 30 through at least one (e.g., one, or multiple) first conductive pillars 11. For example, the first semiconductor structure D1 is connected to the substrate 30 through one first conductive pillar 11. For another example, the first semiconductor structure D1 is connected to the substrate 30 through multiple first conductive pillars 11, and the multiple first conductive pillars 11 can be evenly distributed along the second direction, and the multiple first conductive pillars 11 are parallel to each other. The number of the first conductive pillars 11 is related to the signal density of the first semiconductor component 10. The greater the signal density, the more the number of the first conductive pillars 11 can be.

[0112] Continue to see Figure 4 and Fig. 9 For the second semiconductor component 20, the second semiconductor component 20 includes a plurality of (e.g., one, or a plurality of) second conductive pillars 22. The sidewall of the second conductive pillar 22 is provided with a dielectric layer 102 (not shown in the figure). The first end 221 of the second conductive pillar is connected to the adapter plate 40. For example, the end surface of the first end 221 of the second conductive pillar is exposed to the surface of the second semiconductor component 20 on the side close to the adapter plate 40 (hereinafter referred to as the lower surface of the second semiconductor component 20), and the first end 221 is provided with a pad, and the adapter plate 40 is connected to the second end 222 of the second conductive pillar through the pad. The end surface of the first end 221 of the second conductive pillar can also be directly connected to the adapter plate 40.

[0113] The second end 222 of the second conductive column penetrates into a second semiconductor structure D2, that is, the end surface of the second end 222 of the second conductive column is connected to a second semiconductor structure D2 in the second semiconductor component 20. For the convenience of the following description, the second semiconductor structure D2 connected to the end surface of the second end 222 of the second conductive column is called the second connection semiconductor of the second conductive column. The second end 222 of the second conductive column penetrates the second semiconductor structure D2 between the second connection semiconductor and the substrate 30. The closer to the adapter plate 40, the shorter the length of the second conductive column of the second connection semiconductor.

[0114] Exemplarily, the second semiconductor component 20 includes second semiconductor structures D2a, D2b, and D2c stacked in sequence, wherein the second semiconductor structure D2a is farthest from the adapter plate 40, and the second semiconductor structure D2c is closest to the adapter plate 40. The first end 221a of the second conductive column 22a is exposed to the lower surface of the second semiconductor component 20, and the end surface of the second end 222a of the second conductive column 22a is connected to the second semiconductor structure D2a. At this time, the second connection semiconductor of the second conductive column 12a is the second semiconductor structure D2a. The second semiconductor structures D2b and D2c are stacked between the second semiconductor structure D2a and the adapter plate 40. The second end 222a of the second conductive column 22a penetrates the first semiconductor structures D2c and D2b and extends into the second connection semiconductor, so that the second end 222a of the second conductive column is connected to the second semiconductor structure D2a. In this way, the signal of the second connection semiconductor is transmitted from the end surface of the second end 222a of the second conductive column through the second conductive column 22a to the adapter plate 40.

[0115] The first end 221b of the second conductive pillar 22b is exposed to the lower surface of the second semiconductor component 20, and the end surface of the second end 222b of the second conductive pillar 22b is connected to the second semiconductor structure D2b. At this time, the second semiconductor structure D2b is the second connection semiconductor of the second conductive pillar 22b. The second conductive pillar 22b penetrates the second semiconductor structure D2c and extends into the second connection semiconductor, so that the second end 222b of the second conductive pillar is connected to the second semiconductor structure D2b. The second conductive pillar 22b does not extend into the second semiconductor structure D2a, that is, the second semiconductor structure D2a is connected to the adapter plate 40 only through the second conductive pillar 22a penetrating the second semiconductor structure D2a, and the second semiconductor structure D2b is connected to the adapter plate 40 only through the second conductive pillar 22b penetrating the second semiconductor structure D2b.

[0116] The first end 221c of the second conductive column 22c is exposed to the lower surface of the second semiconductor component 20, and the end surface of the second end 222c of the second conductive column 22c is connected to the second semiconductor structure D2c. At this time, the second semiconductor structure D2c is the second connection semiconductor of the second conductive column 22c. Since there is no other semiconductor structure between the second semiconductor structure D2c and the adapter plate 40, the second conductive column 22c only extends into the second semiconductor structure D2c and does not penetrate any second semiconductor structure D2. The embodiment of the present disclosure only takes three second semiconductor structures D2 as an example. The connection of other numbers of second semiconductor structures D2 to the adapter plate 40 through the conductive column can be referred to the above description, which will not be repeated here.

[0117] The first conductive pillar 11 is disposed in the first semiconductor component 10, and the second conductive pillar 22 is disposed in the second semiconductor component 20, and does not occupy additional packaging space, which is conducive to the miniaturization of the chip packaging structure 100. The connection distance between the first conductive pillar 11 and the substrate 30 is reduced, and the connection distance between the second conductive pillar 22 and the adapter board 40 is reduced, so that the signal transmission distance is shortened, thereby improving the signal transmission speed and reducing the delay.

[0118] The number of the second conductive pillars 22 is at least the same as the number of the second semiconductor structures D2 in the second semiconductor component 20, and each second semiconductor structure D2 is connected to the adapter plate 40 through at least one (e.g., one, or more) second conductive pillar 22. For example, the second semiconductor structure D2 is connected to the adapter plate 40 through one second conductive pillar 22. For another example, the second semiconductor structure D2 is connected to the adapter plate 40 through a plurality of second conductive pillars 22, and the plurality of second conductive pillars 22 may be evenly distributed along the second direction, and the plurality of second conductive pillars 22 may be parallel to each other. The number of the second conductive pillars 22 is related to the signal density of the second semiconductor component 20, and the greater the signal density, the greater the number of the second conductive pillars 22 may be.

[0119] In the disclosed embodiment, the conductive pillars are disposed inside the first semiconductor component 10 and the second semiconductor component 20, and do not need to occupy the packaging space outside the semiconductor structure, thereby reducing the volume of the chip packaging structure 100. The conductive pillars are directly connected to the substrate 30 or the adapter plate 40, which can reduce the interconnection length as much as possible, thereby increasing the signal transmission speed, reducing possible signal interference, achieving low power consumption and high-speed communication between semiconductor structures, increasing bandwidth, and realizing miniaturization of device integration, and realizing high-density integration of storage devices.

[0120] In some embodiments, the first semiconductor structure D1 includes one of a DRAM cell and a NAND cell, and the second semiconductor structure D2 includes the other of the DRAM cell and the NAND cell.

[0121] For example, see Figure 7 and Fig. 9 The first semiconductor structure D1 is a DRAM cell, and the second semiconductor structure D2 is a NAND cell.

[0122] Continue to see Figure 4 and Figure 7 The embodiment of the present disclosure is illustrated by taking the DRAM peripheral device layer M2 as being closer to the substrate 30 than the DRAM array layer M1. It is understandable that the embodiment of the present disclosure is also applicable to the DRAM array layer M1 as being closer to the substrate 30 than the DRAM peripheral device layer M2.

[0123] The second end 112 of the first conductive pillar 11 penetrates to the interface between the DRAM array layer M1 and the DRAM peripheral device layer M2 of a first semiconductor structure D1. The first end 111 of the first conductive pillar 11 is connected to the substrate 30. Specifically, the second end 112 of each first conductive pillar 11 respectively penetrates to the interface between the DRAM array layer M1 and the DRAM peripheral device layer M2 of the first connection semiconductor of the first conductive pillar 11. The signal of the DRAM array layer M1 and the DRAM peripheral device layer M2 is transmitted from the second end 112 of the first conductive pillar 11 to the first end 111 of the first conductive pillar 11, and then transmitted to the substrate 30. For example, continue to refer to Figure 7 , the second end 112a of the first conductive pillar 11a penetrates the first semiconductor structure D1c, the DRAM array layer M1 and the DRAM peripheral device layer M2 of the first semiconductor structure D1b, and the DRAM peripheral device layer M2 of the first semiconductor structure D1a, to the interface between the DRAM peripheral device layer M2 and the DRAM array layer M1 of the first semiconductor structure D1a. The second end 112b of the first conductive pillar 11b penetrates the DRAM array layer M1 and the DRAM peripheral device layer M2 of the first semiconductor structure D1c, and the DRAM peripheral device layer M2 of the first semiconductor structure D1b, to the interface between the DRAM peripheral device layer M2 and the DRAM array layer M1 of the first semiconductor structure D1b. The second end 112c of the first conductive pillar 11c penetrates the DRAM peripheral device layer M2 of the first semiconductor structure D1c, to the interface between the DRAM peripheral device layer M2 and the DRAM array layer M1 of the first semiconductor structure D1c.

[0124] Continue to see Figure 4 and Fig. 9 , the NAND peripheral device layer N2 is closer to the adapter board 40 than the NAND array layer N1, that is, the NAND peripheral device layer N2 of the second semiconductor structure D2 closest to the adapter board 40 is connected to the adapter board 40; the NAND array layer N1 of the second semiconductor structure D2 farthest from the adapter board 40 is closer to the substrate 30 than its NAND peripheral device layer N2.

[0125] The second end 222 of the second conductive pillar 22 penetrates the NAND array layer N1 of a second semiconductor structure D2. The first end 221 of the second conductive pillar 22 is connected to the adapter board 40. Specifically, the second end 222 of each second conductive pillar 22 respectively penetrates the NAND array layer N1 of the second semiconductor connection of the second conductive pillar 22. The signal of the NAND cell is transmitted from the NAND array layer N1 to the first end 221 of the second conductive pillar 22 through the second end 222 of the second conductive pillar 22, and then transmitted to the adapter board 40. For example, continue to refer to Fig. 9The second end 222a of the second conductive pillar 22a penetrates the second semiconductor structure D2c, the NAND peripheral device layer N2 and the NAND array layer N1 of the second semiconductor structure D2b, and the NAND peripheral device layer N2 of the first semiconductor structure D2a, and extends into the NAND array layer N1 of the first semiconductor structure D2a. The second end 222b of the second conductive pillar 22b penetrates the NAND peripheral device layer N2 and the NAND array layer N1 of the second semiconductor structure D2c, and the NAND peripheral device layer N2 of the second semiconductor structure D2b, and extends into the NAND array layer N1 of the second semiconductor structure D2b. The second end 222c of the second conductive pillar 22c penetrates the NAND peripheral device layer N2 of the second semiconductor structure D2c, and extends into the NAND array layer N1 of the first semiconductor structure D2c.

[0126] When the first semiconductor component 10 and the second semiconductor component 20 are stacked, the first semiconductor component 10 is closer to the substrate 30 than the second semiconductor component 20. Because the first semiconductor component 10 is connected to the substrate 30 and the second semiconductor component 20 is connected to the adapter 40, in this embodiment, the distance between the DRAM unit and the substrate 30 is closer, so that the distance between the DRAM unit and the circuit board is closer, thereby improving the transmission speed of the DRAM unit and reducing the transmission delay of the DRAM unit.

[0127] Also exemplarily, the first semiconductor structure D1 is a NAND cell, and the second semiconductor structure D2 is a DRAM cell.

[0128] The NAND peripheral device layer N2 is closer to the substrate 30 than the NAND array layer N1, that is, the NAND peripheral device layer N2 of the first semiconductor structure D1 closest to the substrate 30 is connected to the substrate 30; the NAND array layer N1 of the first semiconductor structure D1 farthest from the substrate 30 is closer to the adapter board 40 than its NAND peripheral device layer N2.

[0129] The second end 112 of the first conductive pillar penetrates a NAND array layer N1 of a first semiconductor structure. The first end 111 of the first conductive pillar is connected to the substrate 30. Specifically, the second end of each first conductive pillar penetrates a NAND array layer of the first semiconductor structure. The signal of the NAND cell is transmitted from the NAND array layer N1 to the first end 111 of the first conductive pillar 11 through the second end 112 of the first conductive pillar 11, and then transmitted to the substrate 30.

[0130] The second end 222 of the second conductive pillar penetrates to the interface between the DRAM array layer M1 and the DRAM peripheral device layer M2 of a second semiconductor structure.

[0131] The embodiment of the present disclosure is illustrated by the example that the DRAM peripheral device layer M2 is closer to the adapter board 40 than the DRAM array layer M1. It can be understood that the embodiment of the present disclosure is also applicable to the case that the DRAM array layer M1 is closer to the adapter board 40 than the DRAM peripheral device layer M2.

[0132] The first end 221 of the second conductive pillar 22 is connected to the adapter board 40. Specifically, the second end 222 of each second conductive pillar 22 respectively penetrates the interface between the DRAM array layer M1 and the DRAM peripheral device layer M2 of the second semiconductor connection of the second conductive pillar 22. The signals of the DRAM array layer M1 and the DRAM peripheral device layer M2 are transmitted from the second end 222 of the second conductive pillar 22 to the first end 221 of the second conductive pillar 22, and then transmitted to the adapter board 40.

[0133] In some embodiments, see Figure 4 The chip packaging structure 100 further includes an adhesive layer 60. The adhesive layer 60 is disposed between the first semiconductor component 10 and the second semiconductor component 20, and serves to bond the first semiconductor component 10 to the second semiconductor component 20. The material of the adhesive layer 60 is an insulating material that can serve as an adhesive, for example, it can be one or more combinations of polyurethane, polystyrene, polyacrylate, ethylene-vinyl acetate copolymer, epoxy resin, die attach film (Die Attach Film, DAF), etc., or other suitable materials. The material of the adhesive layer 60 is an insulating material, which can prevent the signal from being transmitted between the first semiconductor component 10 and the second semiconductor component 20, causing signal transmission disorder.

[0134] In some embodiments, the connection method between adjacent first semiconductor structures D1 in the first semiconductor component 10 includes hybrid bonding or welding; and / or, the connection method between adjacent second semiconductor structures D2 in the second semiconductor component 20 includes hybrid bonding or welding. Exemplarily, the connection method between adjacent first semiconductor structures D1 is different from the connection method between adjacent second semiconductor structures D2. Also exemplarily, the connection method between adjacent first semiconductor structures D1 is the same as the connection method between adjacent second semiconductor structures D2.

[0135] In some examples, the connection between adjacent first semiconductor structures D1 in the first semiconductor component 10 includes hybrid bonding or welding.

[0136] When the connection method is hybrid bonding, multiple first semiconductor structures D1 can be formed on different substrates respectively, and adjacent first semiconductor structures D1 are attached together at room temperature, and then the temperature is increased and the adjacent first semiconductor structures D1 are annealed. The bonding contacts provided on the opposite sides of the adjacent first semiconductor structures D1 will expand and bond together firmly, thereby connecting together to form a first semiconductor component 10 with hybrid bonding between the first semiconductor structures D1. A direct, short-distance (for example, micrometer-level) electrical connection is formed between adjacent first semiconductor structures. Compared with connection through wires, this eliminates the interface delay between adjacent first semiconductor structures D1 and achieves high-speed I / O throughput with reduced power consumption.

[0137] When the connection method is welding, multiple first semiconductor structures D1 can be formed on different substrates respectively, and at least one bump is provided on opposite sides of adjacent first semiconductor structures D1. The bump is reflowed, and during the reflow process, the bump melts, and the opposite bumps melt with each other, so that the adjacent first semiconductor structures D1 are connected. Compared with connection through wires, the interface delay between adjacent first semiconductor structures D1 is eliminated.

[0138] In some other examples, the connection between adjacent second semiconductor structures D2 in the second semiconductor component 20 includes hybrid bonding or welding. The connection between adjacent second semiconductor structures D2 can refer to the description between adjacent first semiconductor structures D1 above, which will not be repeated here.

[0139] In some other examples, the connection between adjacent first semiconductor structures D1 in the first semiconductor component 10 and the connection between adjacent second semiconductor structures D2 in the second semiconductor component 20 are both hybrid bonding.

[0140] In some other examples, the connection between adjacent first semiconductor structures D1 in the first semiconductor component 10 and the connection between adjacent second semiconductor structures D2 in the second semiconductor component 20 are both welded.

[0141] In some embodiments, the connection method between the substrate 30 and the first semiconductor component 10, and between the adapter plate 40 and the second semiconductor component 20 includes hybrid bonding or welding, forming a direct, short-distance (for example, micrometer-level) electrical connection between the substrate 30 and the first semiconductor component 10, and between the adapter plate 40 and the second semiconductor component 20, eliminating the interface delay between the semiconductor component and the substrate 30 and the adapter plate 40, and also reducing power consumption to achieve high-speed I / O throughput. The connection method between the substrate 30 and the first semiconductor component 10, and between the adapter plate 40 and the second semiconductor component 20 can be the same or different. For example, continue to refer to Figure 4, a side of the substrate 30 close to the first semiconductor component 10 and the upper surface of the first semiconductor component 10 are provided with a plurality of bumps, the bumps are reflowed, and the bumps are melted, so that the substrate 30 and the first semiconductor component 10 are welded. A side of the adapter plate 40 close to the second semiconductor component 20 and the lower surface of the second semiconductor component 20 are mixedly bonded. In another exemplary embodiment, a side of the substrate 30 close to the first semiconductor component 10 and the upper surface of the first semiconductor component 10 are mixedly bonded, and the adapter plate 40 and the lower surface of the second semiconductor component 20 are mixedly bonded. In another exemplary embodiment, a side of the substrate 30 close to the first semiconductor component 10 and the upper surface of the first semiconductor component 10 are welded, and the adapter plate 40 and the lower surface of the second semiconductor component 20 are welded.

[0142] When the connection methods between the substrate 30 and the first semiconductor component 10, between the adapter plate 40 and the second semiconductor component 20, between adjacent first semiconductor structures D1 and between adjacent second semiconductor structures D2 are the same, the same connection conditions can be set so that these structures can be connected at the same time. For example, the connection methods are all welding, and the bumps between these structures are reflowed at the same time, and the bumps are melted, so that these structures can be connected at the same time. For another example, the connection methods are all mixed bonding, and these structures are stacked in order of connection, and then the temperature is increased and they are annealed. The bonding contacts between the structures to be connected will expand and bond firmly together, thereby forming an electrical connection.

[0143] In some embodiments, see Figure 4 The chip packaging structure 100 further includes a filling portion 70. The filling portion 70 is formed between the substrate 30 and the adapter plate 40, and is disposed outside the first semiconductor component 10 and the second semiconductor component 20 to fill the gap between the substrate 30 and the adapter plate 40. The filling portion 70 may be a filling material with a certain shock absorption capability, such as silicone, resin or other adhesives, which can prevent the first semiconductor component 10 and the second semiconductor component 20 from being damaged on the one hand, and absorb a portion of the deformation and external force when the chip packaging structure 100 is squeezed by an external force on the other hand. Exemplarily, the material of the filling portion 70 is an epoxy molding compound (EMC).

[0144] The filling portion 70 is also filled between the plurality of connection wires 50. The gaps between the connection wires 50 are filled to prevent the connection wires 50 from directly contacting the semiconductor structure and causing a short circuit.

[0145] In some embodiments, see Figure 4, the chip packaging structure 100 also includes a ball grid array 80. The ball grid array 80 is located on the side of the substrate 30 away from the adapter board 40 (hereinafter referred to as the upper surface of the substrate 30), and the substrate 30 is connected to the circuit board through the ball grid array 80. The ball grid array 80 can be a plurality of solder balls. When in use, the circuit board is directly flipped on the plurality of solder balls. The solder pads of the circuit board correspond to the solder balls, and the solder balls and the solder pads are combined after reflow. The ball grid array 80 can also be a plurality of copper pillar bumps (CPB) with a smaller diameter. The copper pillar bumps contact the substrate 30 to form a metal eutectic bond, thereby achieving the purpose of welding, which is suitable for a chip packaging structure 100 with a higher integration density.

[0146] The disclosed embodiment also provides a method for preparing a chip packaging structure.

[0147] Fig.10 A flow chart of a method for preparing a chip packaging structure provided for some embodiments of the present disclosure. Figures 11A to 18 It is a structural diagram corresponding to each step in the method for preparing a chip packaging structure according to some embodiments.

[0148] The following is a schematic illustration of a method for preparing a chip packaging structure provided by some embodiments of the present disclosure in conjunction with the accompanying drawings.

[0149] See also Fig.10 , and combined with Figures 11A to 18 The preparation method of the above chip packaging structure includes: S1 to S7.

[0150] S1. Form a first semiconductor component and a second semiconductor component.

[0151] The structures of the first semiconductor component 10 and the second semiconductor component 20 can refer to the above description and will not be repeated here. The first semiconductor component 10 and the second semiconductor component 20 can be formed at the same time, or the first semiconductor component 10 can be formed first and then the second semiconductor component 20 can be formed, or the second semiconductor component 20 can be formed first and then the first semiconductor component 10 can be formed.

[0152] Forming the first semiconductor component 10 includes the following steps:

[0153] S11A: See Fig.11A , forming a first semiconductor structure D1.

[0154] The array layer and the peripheral device layer of the first semiconductor structure D1 are connected to form the first semiconductor structure D1.

[0155] In some other implementations, the first semiconductor structure D1 can be directly obtained by purchasing or other means.

[0156] S12A: See Fig. 11B , at least one first sub-conductive pillar 91 is formed in the first semiconductor structure D1.

[0157] A connection hole is formed in the first semiconductor structure D1 by an etching process, and an insulating material is deposited in the connection hole to form a first sub-dielectric layer on the sidewall of the connection hole to form a contact hole. A conductive material is deposited in the contact hole to form a first sub-conductive column 91. The conductive material and the insulating material can be selected from the conductive materials described above, and will not be described in detail here.

[0158] The extension depth of the first sub-conductive pillar 91 in the first semiconductor structure D1 can be in two options:

[0159] Solution 1: The first sub-conductive pillar 91 penetrates the array layer and the peripheral device layer of the first semiconductor structure D1 .

[0160] In solution 2, the first sub-conductive pillar 91 penetrates the array layer of the first semiconductor structure D1 and extends to the interface between the array layer of the first semiconductor structure D1 and the peripheral device layer.

[0161] S13A: See Fig. 11C , multiple first semiconductor structures D1 are stacked to form a first semiconductor component 10.

[0162] At least one (e.g., one, or more) first sub-conductive pillars 91 are stacked in the thickness direction of the first semiconductor component 10 to form a first conductive pillar 11, a first end 111 of the first conductive pillar is exposed on the surface of the first semiconductor component 10, and a second end 112 of the first conductive pillar penetrates into a first semiconductor structure D1. At least one (e.g., one, or more) first sub-dielectric layers are stacked in the thickness direction of the first semiconductor component 10 to form a dielectric layer.

[0163] In the first semiconductor component 10 , the two first semiconductor structures D1 closest to the surface of the first semiconductor component 10 may include the first sub-conductive pillars 91 formed by the first solution, or may include the first sub-conductive pillars 91 formed by the second solution.

[0164] Forming the second semiconductor component 20 includes the following steps:

[0165] S11B: See Fig. 12A , forming a second semiconductor structure D2.

[0166] The array layer and the peripheral device layer of the second semiconductor structure D2 are connected to form the second semiconductor structure D2.

[0167] In some other implementations, the second semiconductor structure D2 can be directly obtained by purchasing or other means.

[0168] S12B: See Fig. 12B , at least one second sub-conductive pillar 92 is formed in the second semiconductor structure D2.

[0169] A connection hole is formed in the second semiconductor structure D2 by an etching process, and an insulating material is deposited in the connection hole to form a second sub-dielectric layer on the sidewall of the connection hole to form a contact hole. A conductive material is deposited in the contact hole to form a second sub-conductive column 92. The conductive material and the insulating material can be selected from the conductive materials described above, and will not be described in detail here.

[0170] The extension depth of the second sub-conductive pillar 92 in the second semiconductor structure D2 can be in two options:

[0171] Solution three: the second sub-conductive pillar 92 penetrates the array layer and the peripheral device layer of the second semiconductor structure D2 .

[0172] In solution 4, the second sub-conductive pillar 92 penetrates the array layer of the second semiconductor structure D2 and extends to the interface between the array layer of the second semiconductor structure D2 and the peripheral device layer.

[0173] S13B: See Fig. 12C , multiple second semiconductor structures D2 are stacked to form a second semiconductor component 20.

[0174] At least one (e.g., one, or more) second sub-conductive pillars 92 are stacked in the thickness direction of the second semiconductor component 20 to form a second conductive pillar 22, a first end 221 of the second conductive pillar is exposed to the surface of the second semiconductor component 20, and a second end 222 of the second conductive pillar penetrates into a second semiconductor structure D2. At least one (e.g., one, or more) second sub-dielectric layers are stacked in the thickness direction of the second semiconductor component 20 to form a dielectric layer.

[0175] In the second semiconductor component 20 , the two second semiconductor structures D2 closest to the surface of the second semiconductor component 20 may be the second sub-conductive pillars 92 formed in the third solution or the fourth solution.

[0176] In step S1, sub-conductive pillars are first formed in the semiconductor structure, and then the semiconductor structure is stacked, so that the positions of the conductive pillars are more accurate and the channel structure in the semiconductor structure is prevented from being damaged.

[0177] S2 (optionally), connecting the first semiconductor component and the second semiconductor component.

[0178] Fig.13 The present invention is a structural diagram of connecting a first semiconductor component and a second semiconductor component in a method for preparing a chip packaging structure according to some embodiments.

[0179] See also Fig.13The first semiconductor component 10 and the second semiconductor component 20 are stacked and connected by an adhesive layer 60. The material of the adhesive layer 60 can be found in the above description and will not be described again.

[0180] Illustratively, a bonding layer 60 is formed on one side of the first semiconductor component 10 by coating or inkjet printing, and a side of the second semiconductor component 20 is brought into contact with the bonding layer 60 , and the first semiconductor component 10 , the bonding layer 60 , and the second semiconductor component 20 are stacked in sequence.

[0181] As another example, the adhesive layer 60 is formed on one side of the second semiconductor component 20 by coating or inkjet printing, and the adhesive layer 60 is brought into contact with one side of the first semiconductor component 10. The second semiconductor component 20, the adhesive layer 60 and the first semiconductor component 10 are stacked in sequence.

[0182] In some other embodiments, the first semiconductor component 10 and the second semiconductor component 20 may also be arranged flat, and step S3 may be directly executed after step S1 is executed.

[0183] S3, placing the first semiconductor component and the second semiconductor component on the adapter board, and connecting the second semiconductor component to the adapter board.

[0184] Fig.14 It is a structural diagram of the connection between the second semiconductor component and the adapter board in the method for preparing the chip packaging structure according to some embodiments.

[0185] See also Fig.14 The first semiconductor component 10 and the second semiconductor component 20 are placed on the adapter board 40, and the side of the second semiconductor component 20 away from the first semiconductor component 10 is connected to the adapter board 40. The connection method can be found in the above description and will not be repeated here.

[0186] S4. Form a connecting line.

[0187] Fig.15 FIG. 1 is a structural diagram of forming connecting wires in a method for preparing a chip packaging structure according to some embodiments.

[0188] See also Fig.15 , one end of the connecting wire 50 is connected to the adapter board 40. The connection between the connecting wire 50 and the adapter board 40 is located in the area of ​​the adapter board 40 where the first semiconductor component 10 and the second semiconductor component 20 are not arranged, so as to prevent the connecting wire 50 from being directly connected to the first semiconductor component 10 and the second semiconductor component 20, thereby preventing the signal transmission from being interfered. The structure and material of the connecting wire 50 can be found in the above description, and will not be repeated here.

[0189] S5 (optional): forming a filling portion.

[0190] Fig.16 FIG. 1 is a structural diagram of forming a filling portion in a method for preparing a chip packaging structure according to some embodiments.

[0191] See also Fig.16 , a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) can be used to deposit filling materials on the adapter plate 40, and a chemical-mechanical planarization (CMP) or etching process can be used to remove the filling material on the side of the first semiconductor component 10 away from the second semiconductor component 20, and expose the other end of the connecting wire 50 to form a filling part 70. The filling material can be found in the above description and will not be repeated here. The filling part 70 fills between the connecting wires 50, and can also fill between the connecting wire 50 and the first semiconductor component 10, and between the connecting wire 50 and the second semiconductor component 20 to prevent short circuits.

[0192] In the related art, a filling part is first formed, a connection hole is formed in the filling part by an etching process, and a conductive material is deposited in the connection hole to form a connection line. However, since the connection line is thin and long, and the etched connection hole has a high aspect ratio, etching multiple connection holes with high aspect ratios at one time requires a precise etching process, which has a low yield, and the etching speed cannot be increased, resulting in low preparation efficiency.

[0193] In the embodiment of the present disclosure, the connecting line 50 is formed first, and then the filling portion 70 is formed, so as to avoid etching a connecting hole with a high aspect ratio in the filling portion 70 . The manufacturing process is relatively simple, and the manufacturing efficiency is improved.

[0194] S6, placing a substrate on a side of the first semiconductor component away from the adapter plate, and connecting the first semiconductor component and the connecting wires to the substrate.

[0195] Fig.17 A structural diagram of setting a substrate in a method for preparing a chip packaging structure according to some embodiments.

[0196] See also Fig.17 A substrate 30 is disposed on one side of the first semiconductor component 10 away from the adapter board 40 , and the other end of the connecting wire 50 is connected to the substrate 30 . The connection method between the substrate 30 and the first semiconductor component 10 can be referred to the above description and will not be repeated here.

[0197] S7 (optional), forming a ball grid array.

[0198] Fig.18A structural diagram of forming a ball grid array in a method for preparing a chip packaging structure according to some embodiments.

[0199] See also Fig.18 A ball grid array 80 is provided on the side of the substrate 30 away from the adapter board 40 for connecting the circuit board. The material and structure of the ball grid array 80 can be found in the above description and will not be described again.

[0200] The disclosed embodiment also provides a method for preparing a semiconductor structure, which may include S1A to S7A.

[0201] Among them, S2A~S7A specifically refer to S2~S7 above.

[0202] S1A, forming a first semiconductor component 10 and a second semiconductor component 20.

[0203] The structures of the first semiconductor component 10 and the second semiconductor component 20 can refer to the above description and will not be repeated here. The first semiconductor component 10 and the second semiconductor component 20 can be formed at the same time, or the first semiconductor component 10 can be formed first and then the second semiconductor component 20 can be formed, or the second semiconductor component 20 can be formed first and then the first semiconductor component 10 can be formed.

[0204] Figures 19A to 19C The structure diagram corresponds to each step of forming a first semiconductor component in a method for preparing a chip packaging structure according to some embodiments.

[0205] Forming the first semiconductor component 10 includes the following steps:

[0206] S11C: See Fig.19A , forming a first semiconductor structure D1.

[0207] See S11A above for details.

[0208] S12C: See Fig.19B , forming an initial first semiconductor component 201.

[0209] A plurality of first semiconductor structures D1 are stacked to form an initial first semiconductor component 201 .

[0210] S13C: See Fig.19C , a plurality of first conductive pillars 11 are formed in the initial first semiconductor component 201 to form the first semiconductor component 10 .

[0211] A connection hole is formed in the initial first semiconductor component 201 by etching, and an insulating material is deposited in the connection hole to form a dielectric layer on the sidewall of the connection hole. The connection hole is provided with a dielectric layer to form a contact hole. A conductive material is deposited in the contact hole to form a first conductive column 11. The conductive material and the insulating material can be selected from the conductive materials described above, and will not be described in detail here.

[0212] The first end 111 of the first conductive pillar 11 is exposed on the surface of the first semiconductor component 10 , the second end 112 of the first conductive pillar 11 penetrates into a first semiconductor structure D1 , and a dielectric layer is disposed on the sidewall of the first conductive pillar 11 .

[0213] Figure 20A to Figure 20C The diagram is a structural diagram corresponding to each step of forming a second semiconductor component in a method for preparing a chip packaging structure according to some embodiments.

[0214] Forming the second semiconductor component 20 includes the following steps:

[0215] S11D: See Fig. 20A , forming a second semiconductor structure D2.

[0216] Please refer to S11B above for details.

[0217] S12D: See Fig. 20B , forming an initial second semiconductor component 202.

[0218] A plurality of second semiconductor structures D2 are stacked to form an initial second semiconductor component 202 .

[0219] S13D: See Fig. 20C , a plurality of second conductive pillars 22 are formed in the initial second semiconductor component 202 to form the second semiconductor component 20 .

[0220] A connection hole is formed in the initial second semiconductor component 202 by etching, and an insulating material is deposited in the connection hole to form a dielectric layer on the sidewall of the connection hole. The connection hole is provided with a dielectric layer to form a contact hole. A conductive material is deposited in the contact hole to form a second conductive column 22. The conductive material and the insulating material can be selected from the conductive materials described above, and will not be described in detail here.

[0221] The first end 221 of the second conductive pillar 22 is exposed on the surface of the second semiconductor component 20 , and the second end 222 of the second conductive pillar 22 penetrates into a second semiconductor structure D2 . A dielectric layer is disposed on the sidewall of the second conductive pillar 22 .

[0222] In step S1A, a stacked initial semiconductor assembly is first formed, and a conductive column is formed in the initial semiconductor assembly at one time, which reduces the number of etchings and improves the manufacturing efficiency. Furthermore, the conductive column is formed at one time to avoid misalignment between the sub-conductive columns, which results in the semiconductor structure being unable to be directly connected to the substrate or the adapter plate.

[0223] The disclosed embodiment also provides a method for preparing a semiconductor structure, which may include S1B to S7B.

[0224] Among them, S2B~S7B specifically refer to the above S2~S7.

[0225] S1B, forming a first semiconductor component 10 and a second semiconductor component 20.

[0226] The first semiconductor component 10 includes a plurality of first semiconductor structures D1, and the second semiconductor component 20 includes a plurality of second semiconductor structures D2. The first semiconductor structures D1 and the second semiconductor structures D2 may be DRAM cells or NAND cells.

[0227] The structures of the first semiconductor component 10 and the second semiconductor component 20 can refer to the above description and will not be repeated here. The first semiconductor component 10 and the second semiconductor component 20 can be formed at the same time, or the first semiconductor component 10 can be formed first and then the second semiconductor component 20 can be formed, or the second semiconductor component 20 can be formed first and then the first semiconductor component 10 can be formed.

[0228] Figures 21A to 21D It is a structural diagram corresponding to each step of forming a first semiconductor component in another method for preparing a chip packaging structure according to some embodiments.

[0229] In some embodiments, the first semiconductor structure D1 is a DRAM cell, and the second semiconductor structure D2 is a DRAM cell.

[0230] Forming the first semiconductor component 10 includes the following steps:

[0231] S11E: See Fig.21A , forming a DRAM array layer M1 and a DRAM peripheral device layer M2.

[0232] The structures of the DRAM array layer M1 and the DRAM peripheral device layer M2 can be found in the above description and will not be described in detail here.

[0233] S12E: See Fig.21B , a first semi-conductive pillar 301 is formed in the DRAM array layer M1, and a second semi-conductive pillar 302 is formed in the DRAM peripheral device layer M2.

[0234] A connection hole is formed in the DRAM array layer M1 by etching, and an insulating material is deposited in the connection hole to form a first semi-dielectric layer on the sidewall of the connection hole to form a contact hole. A conductive material is deposited in the contact hole to form a first semi-conductive column 301 .

[0235] In some examples, the number of first semiconductive pillars 301 in the DRAM array layer M1 may be zero.

[0236] A connection hole is formed in the DRAM peripheral device layer M2 by an etching process, and an insulating material is deposited in the connection hole to form a second semi-dielectric layer on the sidewall of the connection hole to form a contact hole. A conductive material is deposited in the contact hole to form a second semi-conductive column 302. The conductive material and the insulating material can be selected from the conductive materials described above, and will not be described in detail here.

[0237] In some examples, the number of first semiconductive pillars 301 in the DRAM peripheral device layer M2 may be zero.

[0238] S13E: See Fig. 21C The DRAM array layer M1 and the DRAM peripheral device layer M2 are stacked to form a first semiconductor structure D1.

[0239] The first semi-conductive pillar 301 and the second semi-conductive pillar 302 are stacked in the thickness direction of the first semiconductor structure D1 to form a semi-conductive pillar 303. The first semi-dielectric layer and the second semi-dielectric layer are stacked in the thickness direction of the first semiconductor structure D1 to form a semi-dielectric layer. When the number of the first semi-conductive pillars 301 is zero, the semi-conductive pillar 303 is formed by the second semi-conductive pillar 302. When the number of the second semi-conductive pillars 302 is zero, the semi-conductive pillar 303 is formed by the first semi-conductive pillar 301.

[0240] S14E: See Fig.21D , multiple first semiconductor structures D1 are stacked to form a first semiconductor component 10.

[0241] At least one semi-conductive pillar 303 is stacked in the thickness direction of the first semiconductor component 10 to form a first conductive pillar 11. The second end 112 of the first conductive pillar penetrates to the interface between the DRAM array layer M1 and the DRAM peripheral device layer M2 of a first semiconductor structure D1. The number of the first semi-conductive pillars 301 in the DRAM array layer M1 of the first semiconductor structure D1 close to the side surface of the first semiconductor component 10 can be zero.

[0242] Forming the second semiconductor component 20 includes the following steps:

[0243] S11F: forming a DRAM array layer M1 and a DRAM peripheral device layer M2.

[0244] The structures of the DRAM array layer M1 and the DRAM peripheral device layer M2 can be found in the above description and will not be described in detail here.

[0245] S12F: forming a third semi-conductive pillar in the DRAM array layer M1, and forming a fourth semi-conductive pillar in the DRAM peripheral device layer M2.

[0246] A connection hole is formed in the DRAM array layer M1 by etching, and an insulating material is deposited in the connection hole to form a third semi-dielectric layer on the sidewall of the connection hole to form a contact hole. A conductive material is deposited in the contact hole to form a third semi-conductive column.

[0247] In some examples, the number of third semiconductive pillars in the DRAM array layer M1 may be zero.

[0248] A connection hole is formed in the DRAM peripheral device layer M2 by an etching process, and an insulating material is deposited in the connection hole to form a fourth semi-dielectric layer on the sidewall of the connection hole to form a contact hole. A conductive material is deposited in the contact hole to form a fourth semi-conductive column. The conductive material and the insulating material can be selected from the conductive materials introduced above, and will not be described in detail here.

[0249] In some examples, the number of fourth semiconductive pillars in the DRAM peripheral device layer M2 may be zero.

[0250] S13F: stacking the DRAM array layer M1 and the DRAM peripheral device layer M2 to form a second semiconductor structure D2.

[0251] The third semiconductive pillar and the fourth semiconductive pillar are stacked in the thickness direction of the second semiconductor structure D2 to form a semiconductive pillar 303. The third semi-dielectric layer and the fourth semi-dielectric layer are stacked in the thickness direction of the second semiconductor structure D2 to form a semi-dielectric layer. When the number of the third semiconductive pillars is zero, the semiconductive pillar 303 is formed by the fourth semiconductive pillar. When the number of the fourth semiconductive pillars is zero, the semiconductive pillar 303 is formed by the third semiconductive pillar.

[0252] S14F: stacking a plurality of second semiconductor structures D2 to form a second semiconductor component 20 .

[0253] At least one semi-conductive pillar 303 is stacked in the thickness direction of the second semiconductor component 20 to form a second conductive pillar 22. The second end 222 of the second conductive pillar penetrates to the interface between the DRAM array layer M1 and the DRAM peripheral device layer M2 of a second semiconductor structure D2. The number of third semi-conductive pillars in the DRAM array layer M1 of the second semiconductor structure D2 close to the side surface of the second semiconductor component 20 can be zero.

[0254] In some further embodiments, the first semiconductor structure is a NAND cell, and the second semiconductor structure is a NAND cell.

[0255] Forming the first semiconductor component 10 includes the following steps:

[0256] S11P: forming a NAND array layer N1 and a NAND peripheral device layer N2.

[0257] See step S11F above.

[0258] S12P: forming a fifth semiconductive pillar in the NAND array layer N1, and forming a sixth semiconductive pillar in the NAND peripheral device layer N2.

[0259] A connection hole is formed in the NAND array layer N1 by etching, and an insulating material is deposited in the connection hole to form a fifth semi-dielectric layer on the sidewall of the connection hole to form a contact hole. A conductive material is deposited in the contact hole to form a fifth semi-conductive column.

[0260] A connection hole is formed in the NAND peripheral device layer N2 by etching, and an insulating material is deposited in the connection hole to form a sixth semi-dielectric layer on the sidewall of the connection hole to form a contact hole. A conductive material is deposited in the contact hole to form a sixth semi-conductive column.

[0261] S13P: stacking the NAND array layer N1 and the NAND peripheral device layer N2 to form a first semiconductor structure D1.

[0262] The fifth and sixth semiconductive pillars are stacked in the thickness direction of the first semiconductor structure D1 to form a semiconductive pillar 303. The fifth and sixth semi-dielectric layers are stacked in the thickness direction of the first semiconductor structure D1 to form a semi-dielectric layer.

[0263] S14P: stacking a plurality of first semiconductor structures D1 to form a first semiconductor component 10 .

[0264] At least one semi-conductive pillar 303 is stacked in the thickness direction of the first semiconductor device 10 to form a first conductive pillar 11. The second end 112 of the first conductive pillar penetrates into a NAND array layer N1 of a first semiconductor structure D1.

[0265] Figures 22A to 22D It is a structural diagram corresponding to each step of forming a second semiconductor component in a method for preparing a chip packaging structure according to some embodiments.

[0266] Forming the second semiconductor component 20 includes the following steps:

[0267] S11Q: See Fig.22A , forming a NAND array layer N1 and a NAND peripheral device layer N2.

[0268] The structures of the NAND array layer N1 and the NAND peripheral device layer N2 can be found in the above description and will not be described in detail here.

[0269] S12Q: See Fig. 22B , a seventh semiconductive pillar 307 is formed in the NAND array layer N1, and an eighth semiconductive pillar 308 is formed in the NAND peripheral device layer N2.

[0270] A connection hole is formed in the NAND array layer N1 by etching, and an insulating material is deposited in the connection hole to form a seventh semi-dielectric layer on the sidewall of the connection hole to form a contact hole. A conductive material is deposited in the contact hole to form a seventh semi-conductive pillar 307 .

[0271] A connection hole is formed in the NAND peripheral device layer N2 by etching, and an insulating material is deposited in the connection hole to form an eighth semi-dielectric layer on the sidewall of the connection hole to form a contact hole. A conductive material is deposited in the contact hole to form an eighth semi-conductive pillar 308 .

[0272] S13Q: See Fig. 22C , the NAND array layer N1 and the NAND peripheral device layer N2 are stacked to form a second semiconductor structure D2.

[0273] The seventh semiconductive pillar 307 and the eighth semiconductive pillar 308 are stacked in the thickness direction of the second semiconductor structure D2 to form a semiconductive pillar 303. The seventh semi-dielectric layer and the eighth semi-dielectric layer are stacked in the thickness direction of the second semiconductor structure D2 to form a semi-dielectric layer.

[0274] S14Q: See Fig.22D , multiple second semiconductor structures D2 are stacked to form a second semiconductor component 20.

[0275] At least one semi-conductive pillar 303 is stacked in the thickness direction of the second semiconductor device 20 to form a second conductive pillar 22. The second end 222 of the second conductive pillar penetrates into a NAND array layer N1 of a second semiconductor structure D2.

[0276] In some other embodiments, the first semiconductor structure D1 is a DRAM cell, and the second semiconductor structure D2 is a NAND cell.

[0277] The steps of forming the first semiconductor element 10 may refer to the above steps S11E to S14E.

[0278] The steps of forming the second semiconductor element 20 may refer to the above steps S11Q to S14Q.

[0279] In some other embodiments, the first semiconductor structure D1 is a NAND cell, and the second semiconductor structure D2 is a DRAM cell.

[0280] The steps of forming the first semiconductor element 10 may refer to the above steps S11P to S14P.

[0281] The steps of forming the second semiconductor element 20 may refer to the above steps S11F to S14F.

[0282] In the embodiment of the present disclosure, sub-conductive pillars are first formed in the array layer and the peripheral device layer respectively, and then the array layer and the peripheral device layer are stacked to form a semiconductor structure, thereby further improving the accuracy of the stacking of the sub-conductive pillars, so that the sub-conductive pillars are interconnected after being stacked, which is convenient for signal transmission.

[0283] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: substrate; An adapter plate, arranged opposite to the base plate; The first semiconductor component and the second semiconductor component are arranged between the substrate and the adapter board; the first semiconductor component is connected to the substrate, and the second semiconductor component is connected to the adapter board; the substrate and the adapter board are connected through a plurality of connecting wires.

2. The chip packaging structure according to claim 1, characterized in that: The first semiconductor component includes a plurality of first semiconductor structures arranged in a stacked manner, and the second semiconductor component includes a plurality of second semiconductor structures arranged in a stacked manner.

3. The chip packaging structure according to claim 1, characterized in that: The first semiconductor component comprises a plurality of first conductive pillars, wherein the first ends of the first conductive pillars are connected to the substrate, and the second ends of the first conductive pillars penetrate into the first semiconductor structure; and a dielectric layer is provided on the sidewalls of the first conductive pillars; The second semiconductor component includes a plurality of second conductive pillars, wherein the first ends of the second conductive pillars are connected to the adapter plate, and the second ends of the second conductive pillars penetrate into a second semiconductor structure; and a dielectric layer is disposed on the sidewalls of the second conductive pillars.

4. The chip packaging structure according to claim 3, characterized in that: The first semiconductor structure includes one of a DRAM cell and a NAND cell, and the second semiconductor structure includes the other of the DRAM cell and the NAND cell; The chip packaging structure further includes an adhesive layer disposed between the first semiconductor component and the second semiconductor component.

5. The chip packaging structure according to claim 4, characterized in that: The first semiconductor structure includes a DRAM cell, and the second semiconductor structure includes a NAND cell.

6. The chip packaging structure according to claim 4, characterized in that: The DRAM unit comprises: a DRAM array layer and a DRAM peripheral device layer which are stacked; In the case where the first semiconductor structure includes a DRAM cell, the second end of the first conductive pillar penetrates to an interface between the DRAM array layer and the DRAM peripheral device layer of the first semiconductor structure; In the case where the second semiconductor structure includes a DRAM cell, the second end of the second conductive pillar penetrates to an interface between the DRAM array layer and the DRAM peripheral device layer of the second semiconductor structure.

7. The chip packaging structure according to claim 4, characterized in that: The NAND cell comprises: a NAND array layer and a NAND peripheral device layer which are stacked; In the case where the first semiconductor structure includes a NAND cell, the NAND peripheral device layer is closer to the substrate than the NAND array layer; the second end of the first conductive pillar penetrates the NAND array layer of the first semiconductor structure; In the case where the second semiconductor structure includes a NAND unit, the NAND peripheral device layer is closer to the adapter board than the NAND array layer; and the second end of the second conductive pillar penetrates into the NAND array layer of the second semiconductor structure.

8. The chip packaging structure according to claim 2, characterized in that: Orthographic projections of the first semiconductor structures and the second semiconductor structures on the substrate overlap.

9. The chip packaging structure according to claim 1, characterized in that: The connection between the substrate and the first semiconductor component and between the adapter plate and the second semiconductor component includes hybrid bonding or welding.

10. The chip packaging structure according to claim 2, characterized in that: The connection between adjacent first semiconductor structures in the first semiconductor component includes hybrid bonding or welding; and / or, The connection between adjacent second semiconductor structures in the second semiconductor component includes hybrid bonding or welding.

11. The chip packaging structure according to claim 1, characterized in that: The connecting line includes gold fingers, and the substrate and the adapter board are connected via a plurality of the gold fingers.

12. The chip packaging structure according to claim 1, characterized in that: Also includes: A filling portion is formed between the substrate and the adapter plate; the filling portion is filled between the plurality of connection lines.

13. The chip packaging structure according to claim 1, characterized in that: Also includes: A ball grid array is located on a side of the substrate away from the adapter plate; The substrate is connected to the circuit board through the ball grid array.

14. A storage system, characterized in that: include: The chip packaging structure according to any one of claims 1 to 13; A controller is coupled to the chip packaging structure.

15. An electronic device, characterized in that: Comprising the storage system as claimed in claim 14.

16. A method for preparing a chip packaging structure, characterized in that: include: forming a first semiconductor component and a second semiconductor component; Placing the first semiconductor component and the second semiconductor component on an adapter board, and connecting the second semiconductor component to the adapter board; forming a connecting line, wherein the connecting line is connected to the adapter board; A substrate is arranged on a side of the first semiconductor component away from the transfer board, and the first semiconductor component and the connecting wire are connected to the substrate.

17. The method for preparing a chip packaging structure according to claim 16, characterized in that: The forming of the first semiconductor component and the second semiconductor component comprises: forming a first semiconductor structure and a second semiconductor structure; At least one first sub-conductive column is formed in the first semiconductor structure, and at least one second sub-conductive column is formed in the second semiconductor structure, wherein the sidewalls of the first sub-conductive column and the second sub-conductive column are provided with a dielectric layer; A plurality of first semiconductor structures are stacked to form a first semiconductor component; the at least one first sub-conductive column is stacked in the thickness direction of the first semiconductor component to form a first conductive column, the first end of the first conductive column is exposed to the surface of the first semiconductor component, and the second end of the first conductive column penetrates into the first semiconductor structure; A plurality of second semiconductor structures are stacked to form a second semiconductor component; the at least one second sub-conductive column is stacked in the thickness direction of the second semiconductor component to form a second conductive column, the first end of the second conductive column is exposed to the surface of the second semiconductor component, and the second end of the second conductive column penetrates into a second semiconductor structure.

18. The method for preparing a chip packaging structure according to claim 16, characterized in that: The forming of the first semiconductor component and the second semiconductor component comprises: Forming an initial first semiconductor component and an initial second semiconductor component; the initial first semiconductor component includes a plurality of first semiconductor structures arranged in a stacked manner, and the initial second semiconductor component includes a plurality of second semiconductor structures arranged in a stacked manner; A plurality of first conductive pillars are formed in the initial first semiconductor component to form the first semiconductor component; a first end of the first conductive pillar is exposed on a surface of the first semiconductor component, a second end of the first conductive pillar penetrates into a first semiconductor structure, and a dielectric layer is provided on a sidewall of the first conductive pillar; A plurality of second conductive pillars are formed in the initial second semiconductor component to form the second semiconductor component; a first end of the second conductive pillar is exposed on a surface of the second semiconductor component, a second end of the second conductive pillar penetrates into a second semiconductor structure, and a dielectric layer is provided on a sidewall of the second conductive pillar.

19. The method for preparing a chip packaging structure according to claim 16, characterized in that: The first semiconductor component includes a plurality of first semiconductor structures, and the second semiconductor component includes a plurality of second semiconductor structures; In the case where the first semiconductor structure includes a DRAM cell, the forming of the first semiconductor component includes: forming a plurality of first semiconductor structures; Forming the first semiconductor structure includes: forming a DRAM array layer and a DRAM peripheral device layer; forming a first semi-conductive pillar in the DRAM array layer and forming a second semi-conductive pillar in the DRAM peripheral device layer; The DRAM array layer and the DRAM peripheral device layer are stacked to form a first semiconductor structure; A plurality of first semiconductor structures are stacked to form a first semiconductor component; the at least one semi-conductive column is stacked in the thickness direction of the first semiconductor component to form a first conductive column; the second end of the first conductive column penetrates to the interface between the DRAM array layer and the DRAM peripheral device layer of the first semiconductor structure; the semi-conductive column includes the first semi-conductive column and the second semi-conductive column; In the case where the second semiconductor structure includes a DRAM cell, the forming of the second semiconductor component includes: forming a plurality of second semiconductor structures; Forming the second semiconductor structure includes: forming a DRAM array layer and a DRAM peripheral device layer; forming a third semi-conductive pillar in the DRAM array layer and forming a fourth semi-conductive pillar in the DRAM peripheral device layer; The DRAM array layer and the DRAM peripheral device layer are stacked to form a second semiconductor structure; A plurality of second semiconductor structures are stacked to form a second semiconductor component; the at least one semiconductive column is stacked in the thickness direction of the second semiconductor component to form a second conductive column; the second end of the second conductive column penetrates to an interface between the DRAM array layer and the DRAM peripheral device layer of the second semiconductor structure; the semiconductive column includes the third semiconductive column and the fourth semiconductive column.

20. The method for preparing a chip packaging structure according to claim 16, characterized in that: The first semiconductor component includes a plurality of first semiconductor structures, and the second semiconductor component includes a plurality of second semiconductor structures; In the case where the first semiconductor structure includes a NAND cell, the forming of the first semiconductor component includes: forming a plurality of first semiconductor structures; Forming the first semiconductor structure includes: forming a NAND array layer and a NAND peripheral device layer; forming a fifth semiconductive pillar in the NAND array layer and forming a sixth semiconductive pillar in the NAND peripheral device layer; The NAND array layer and the NAND peripheral device layer are stacked to form a first semiconductor structure; A plurality of first semiconductor structures are stacked to form a first semiconductor component; the at least one semiconductive column is stacked in the thickness direction of the first semiconductor component to form a first conductive column; the second end of the first conductive column penetrates the NAND array layer of the first semiconductor structure; the semiconductive column includes the fifth semiconductive column and the sixth semiconductive column; In the case where the second semiconductor structure includes a NAND cell, the forming of the second semiconductor component includes: forming a plurality of second semiconductor structures; Forming the second semiconductor structure includes: forming a NAND array layer and a NAND peripheral device layer; forming a seventh semiconductive pillar in the NAND array layer and forming an eighth semiconductive pillar in the NAND peripheral device layer; The NAND array layer and the NAND peripheral device layer are stacked to form a second semiconductor structure; A plurality of second semiconductor structures are stacked to form a second semiconductor component; the at least one semiconductive column is stacked in the thickness direction of the second semiconductor component to form a second conductive column; the second end of the second conductive column penetrates into the NAND array layer of the second semiconductor structure; the semiconductive column includes the seventh semiconductive column and the eighth semiconductive column.

21. The method for preparing a chip packaging structure according to any one of claims 16 to 20, characterized in that: After forming the connecting wires, the method for preparing the chip packaging structure further includes: A filling portion is formed, wherein the filling portion fills between the connection lines.

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