Bipolar transistor

Abstract

The invention relates to a semiconductor structure, and more particularly relates to a bipolar transistor and a manufacturing method. The structure comprises a collector electrode; a base region over the collector; an emitter laterally connected to the base region; and an external base connected to the base region.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to bipolar transistors and methods of fabrication. Background Art

[0002] A heterojunction bipolar transistor (HBT) is a bipolar junction transistor (BJT) that uses different semiconductor materials for the emitter and base regions to form a heterojunction. HBTs can handle extremely high frequency signals up to hundreds of GHz. HBTs are commonly used in ultrafast circuits (mainly radio frequency (RF) systems) and applications that require high power efficiency, such as RF power amplifiers in cellular phones. Summary of the invention

[0003] In one aspect of the present disclosure, a structure includes: a collector; a base region located above the collector; an emitter laterally connected to the base region; and an extrinsic base connected to the base region.

[0004] In one aspect of the present disclosure, a structure includes: a semiconductor region of a first conductivity type; a subcollector located above the semiconductor region and including a second conductivity type; a base region located above the subcollector and also including the first conductivity type; a gate structure located above the base region; an emitter located on a first side of the gate structure; and an external base located on a second side of the gate structure.

[0005] In one aspect of the disclosure, a method includes forming a collector; forming a base region over the collector; forming an emitter laterally connected to the base region; and forming an extrinsic base connected to the base region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0007] Figure 1 A transistor and corresponding manufacturing process according to some aspects of the present disclosure are shown.

[0008] Figure 2 Transistors according to additional aspects of the present disclosure are shown.

[0009] Figures 3A-3C A transistor according to further aspects of the disclosure is shown.

[0010] Figures 4A-4E A fabrication process for fabricating a transistor according to some aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0011] The present disclosure relates to semiconductor structures, and more particularly to bipolar transistors and methods of manufacturing. More particularly, the bipolar transistor may be a lateral vertical bipolar transistor formed below a gate structure. Advantageously, the lateral vertical bipolar transistor disclosed herein exhibits high performance characteristics, such as improved fT / Fmax.

[0012] In a specific embodiment, the lateral vertical bipolar transistor can be a lateral vertical SiGe heterojunction bipolar transistor (HBT). The HBT includes an emitter, and an external base is laterally connected to the SiGe base, and a collector can be vertically located below the SiGe base. The gate structure can separate the emitter from the external base. In operation, the HBT can be modulated by a biased gate structure. The emitter and the external base can be, for example, single crystal semiconductor materials.

[0013] The bipolar transistors of the present disclosure can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer-scale dimensions. Methods (i.e., techniques) for manufacturing the bipolar transistors of the present disclosure have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a material film patterned on top of the wafer by means of a photolithography process. Specifically, the manufacture of bipolar transistors uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithography imaging; and (iii) selectively etching the film to the mask. In addition, as is known in the art, a pre-cleaning process can be used to clean any contaminants on the etched surface. In addition, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0014] Figure 1 A transistor and a corresponding manufacturing process according to some aspects of the present disclosure are shown. In an embodiment, the transistor 10 may be a four-terminal bipolar transistor. In another embodiment, the transistor 10 may be a lateral-vertical HBT, which includes a base 18 vertically located above the subcollector 14 and an emitter 26 laterally connected to the base 18. The external base 24 may also be laterally connected to the base 18 at the end of the gate structure 20 opposite to the emitter 26. The gate structure 20 separates the emitter 26 from the external base 24 and may be biased to modulate the HBT. The emitter 26 and the external base 24 may be at the same level of the device and may be separated by the gate structure 20.

[0015] More specifically, transistor 10 includes substrate 12, which includes, for example, semiconductor-on-insulator (SOI) technology. Semiconductor substrate 12 includes, from bottom to top, a handle substrate 12a, a buried insulator layer 12b, and a top semiconductor layer 12c. The handle substrate 12a provides mechanical support for the buried insulator layer 12b and the top semiconductor layer 12c. The handle substrate 12a may also include a collector / sub-collector region 14.

[0016] In an embodiment, the sub-collector region 14 may include an N-well. The N-well may be formed by a conventional ion implantation process as described herein. The n-type dopants used in the ion implantation process may be, for example, arsenic (As), phosphorus (P), and antimony (Sb), as well as other suitable examples. It will be appreciated by those skilled in the art that an annealing process may be performed to drive any dopants into the handling substrate 12a and / or the top semiconductor layer 12c. In a PNP device, the sub-collector region 14 may be a P-well, and the handling substrate 12a may be an n-type substrate or have an n-type isolation region around the p-well.

[0017] The processing substrate 12a and the top semiconductor layer 12c may include semiconductor materials, such as Si, SiGe, SiC, SiGeC, III-V compound semiconductors, II-VI compound semiconductors, or any combination thereof. In a specific embodiment, the processing substrate 12a may preferably be a P-type Si substrate. The buried insulator layer 12b may include a dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, boron nitride, or a combination thereof. In one embodiment, the buried insulator layer 12b may be a buried oxide layer (BOX) formed by a deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition CVD (PECVD), or physical vapor deposition (PVD). In another embodiment, the buried insulator layer 12b may be formed using a thermal growth process (e.g., thermal oxidation) or by implanting oxygen atoms into the bulk semiconductor substrate and then annealing the structure.

[0018] Typically, each of the handle substrate 12a and the top semiconductor layer 12c includes a single crystal semiconductor material, such as single crystal silicon (Si). The handle substrate 12a and the top semiconductor layer 12c may include any suitable crystal orientation (e.g., (100), (110), (111) or (001) crystal orientation). The top semiconductor layer 12c may be formed by a deposition process (e.g., CVD or PECVD) or a smart cut process known in the art, and therefore, no further explanation is required to fully understand the present invention.

[0019] Still refer to Figure 1, a base region 18 may be formed within the buried insulator layer 12b and the top semiconductor layer 12c. The base region 18 may contact the handling substrate 12a, and more specifically, be electrically connected to the sub-collector region 14. The base region 18 may be an epitaxially grown semiconductor material vertically located above the sub-collector region 14. The base region 18 may be a p-type SiGe material epitaxially grown from the handling substrate 12a by in-situ p-type doping (e.g., boron). The combination of the base region 18, the sub-collector region 14, and the handling substrate 12a will form a parasitic PNP device.

[0020] In an alternative embodiment for forming a PNP device, the base region 18 may be an n-type SiGe material epitaxially grown from the handle substrate 12a by in-situ n-type doping (e.g., arsenic). In this embodiment, the combination of the base region 18, the sub-collector region 14, and the handle substrate 12a will form a parasitic NPN device.

[0021] The gate structure 20 may be formed vertically above the base region 18. In a more specific embodiment, the gate structure 20 may be formed on a surface of the base region 18 (e.g., a p-type SiGe material). The gate structure 20 may be, for example, a dielectric material contacting the base region 18 and a polysilicon material located above the dielectric layer, and its width may be the same, smaller, or larger than the width of the base region 18. Sidewall spacers 22 may be formed on the sidewalls of the gate structure 20. In an embodiment, the sidewall spacers 22 may be an insulator material, such as an oxide and / or nitride material.

[0022] The gate structure 20 may be disposed between the extrinsic base 24 and the emitter 26. In this manner, the extrinsic base 24 and the emitter 26 are laterally separated and isolated from each other by the gate structure 20.

[0023] In an embodiment, the external base 24 may be a p-type semiconductor material formed on one side of the gate structure 20 (e.g., adjacent to the sidewall spacer 22 and directly above the buried insulator layer 12b) by an epitaxial growth process. The external base 24 may also be laterally connected to the base region 18 (e.g., a p-type SiGe material). The p-type semiconductor material may be p-doped Si.

[0024] The top semiconductor layer 12a may also be used to form a portion of the extrinsic base 24 that contacts the base region 18. For example, in an embodiment, the extrinsic base 24 may be epitaxially grown from the top semiconductor layer 12a. In this manner, the semiconductor layer 12a may become p-doped by an in-situ doping process during the epitaxial growth process of the extrinsic base 24.

[0025] In addition, the emitter 26 can be an n-type emitter formed by an epitaxial growth process on the other side of the gate structure 20 (e.g., adjacent to the sidewall spacer 22 and directly above the buried insulator layer 12b). The emitter 26 can also be laterally connected to the base region 18 (e.g., p-type SiGe material) below the gate structure 20. The top semiconductor layer 12a can form a portion of the emitter 26. In an embodiment, the emitter 26 can be epitaxially grown from the top semiconductor layer 12a. In this way, the semiconductor layer 12a can become n-doped by an in-situ doping process during the epitaxial growth process of the emitter 26. Therefore, the top semiconductor layer 12a can be used to form both the external base 24 and the emitter 26.

[0026] The collector contact 28 may be formed on the side of the base region 18 by an epitaxial growth process. The collector contact 28 may be electrically connected to the collector region 16. The collector contact 28 may be separated from the base region 18 by both the buried insulator layer 12b and the shallow trench isolation structure 30. In an embodiment, the shallow trench isolation structure 30 may be formed by conventional photolithography, etching, and deposition methods known to those skilled in the art, such as those described in detail in relation to FIG. Figure 4A as described.

[0027] Figure 1 Also shown are contacts 32 formed to the collector contact 28, the extrinsic base 24, the emitter 26, and the gate structure 20. Prior to forming the contacts 32, silicide contacts may be formed on the collector contact 28, the extrinsic base 24, the emitter 26, and optionally on the gate structure 20. As will be appreciated by those skilled in the art, the silicide process begins by depositing a thin transition metal layer, such as nickel, cobalt, or titanium, over a fully formed and patterned semiconductor device (e.g., the collector contact 28, the extrinsic base 24, the emitter 26, and the gate structure 20). After the material is deposited, the structure is heated, allowing the transition metal to react with the exposed silicon (or other semiconductor materials described herein) in the active region of the semiconductor device (e.g., the collector contact 28, the extrinsic base 24, the emitter 26, and the gate structure 20) to form a low-resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active region of the device.

[0028] Figure 2 1 shows a transistor according to additional aspects of the present disclosure. In an embodiment, transistor 10a may be Figure 1 For example, in this embodiment, two gate structures 20 may be disposed over two base regions 18 (e.g., p-type SiGe material) with a single emitter region 26 between the gate structures 20 and two base regions 24 on opposite sides of the gate structures 20. The remaining features of transistor 10a are similar to those of Figure 1The transistor 10, therefore, requires no further explanation to fully understand the present disclosure.

[0029] Figures 3A-3C A transistor according to further aspects of the disclosure is shown. Figure 3A A top view of transistor 10b is shown; and Figure 3B Shown along Figure 3A A cross-sectional view of the transistor taken along line XX, Figure 3C Shown along Figure 3A 2 is a cross-sectional view of the transistor taken along line YY. In this embodiment, the gate structure 20 is an "I"-shaped structure with sidewall spacers 22 around it. Figure 3B As shown in the cross-sectional view taken along line XX, the emitter 26 is disposed on both sides of the gate structure 20. Figure 3A In the cross-sectional view taken along the line YY, the external base 24 is disposed at both ends of the gate structure 20. The remaining features are similar to Figure 1 The transistor 10, therefore, requires no further explanation to fully understand the present disclosure.

[0030] Figures 4A-4E A manufacturing process for manufacturing a transistor according to some aspects of the present disclosure is shown. FIG. 4 shows a substrate 12, which includes, for example, a handle substrate 12a, a buried insulator layer 12b, and a top semiconductor layer 12c from bottom to top. The handle substrate 12a includes a sub-collector region 14, which may include an N-well. The N-well may be formed by a conventional ion implantation process. For example, the N-well may be formed by introducing a certain concentration of n-type dopants. In an embodiment, a patterned implantation mask may be used to define a selected area exposed for implantation. The implantation mask may include a layer of photosensitive material, such as an organic photoresist layer, which is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. The implantation mask has a thickness and stopping capability sufficient to block the masked area from receiving a certain dose of implanted ions. The N-well is doped with n-type dopants, such as arsenic (As), phosphorus (P), and Sb, as well as other suitable examples.

[0031] In an embodiment, the shallow trench isolation structure 30 can be formed by conventional photolithography, etching and deposition methods known to those skilled in the art. For example, the resist formed above the buried insulator layer 12b is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). An etching process with selective chemical action, such as reactive ion etching (RIE), is used to transfer the pattern from the photoresist layer to the buried insulator layer 12b to form one or more grooves that reach the underlying (underlying) processing substrate 12a. After removing the resist by a conventional oxygen ashing process or other known strippers, the insulator material (e.g., SiO2) can be deposited by any conventional deposition process, such as a chemical vapor deposition (CVD) process. Any residual material on the surface of the structure can be removed by a conventional chemical mechanical polishing (CMP) process.

[0032] 4, the top semiconductor layer 12c and the buried insulator layer 12b may also be patterned to expose the underlying handle substrate 12a, and more specifically, the sub-collector region 14. The patterning may be a conventional photolithography and etching process as already described herein.

[0033] exist Figure 4B In the embodiment, a nitride hard mask 50 can be formed over the top semiconductor layer 12c and patterned. In this embodiment, the pattern includes an opening that conforms to the size and shape of the base region. The pattern formed by the hard mask 50 is transferred to the buried insulator layer 12b and the top semiconductor layer 12c by a conventional etching process with selective chemistry, such as RIE. In this way, a trench 52 is formed in the buried insulator layer 12b and the top semiconductor layer 12c, exposing the underlying handle substrate 12a, such as the sub-collector region 14.

[0034] exist Figure 4C In the embodiment, the base region 18 can be formed in the trench 52. In an embodiment, the base region 18 can be formed by an epitaxial growth process using in-situ doping. For example, the epitaxial growth process can be a SiGe material grown from the handle substrate 12a using in-situ p-type doping. In an embodiment, a boron spike can be set at the surface of the p-type SiGe material.

[0035] exist Figure 4DIn the embodiment, the hard mask can be stripped and a gate structure 20 with sidewall spacers 22 can be formed above the base region 18. In an embodiment, the gate structure 20 can be formed by a conventional deposition process and then a patterning process is performed. For example, the gate structure 20 can be formed by a CVD process, and the CVD process includes, for example, depositing a gate dielectric material and a gate electrode material. In an embodiment, the gate dielectric material can be a low-k dielectric material or a high-k dielectric material known in the art, and therefore, no further explanation is required to fully understand the present disclosure. The gate electrode material can be a polysilicon material. The conventional patterning process described herein can be used to pattern the gate electrode material and the gate dielectric material. The gate 20 can have a width that is larger, smaller, or the same size as the base region 18.

[0036] Still refer to Figure 4D , sidewall spacers 22 may be formed on the sidewalls of the gate structure 20. The sidewall spacers 22 may be oxide and / or nitride materials formed by a conventional deposition method (eg, CVD) followed by an anisotropic etching process.

[0037] like Figure 4E As further shown, the extrinsic base 24, emitter 26, and collector contact 31 may be formed by conventional epitaxial growth processes as described herein. In an embodiment, the emitter 26 and collector contact 28 may be formed simultaneously using an in-situ n-type doping process; while the extrinsic base 24 may be formed by an in-situ p-type doping process. In an alternative embodiment, the extrinsic base 24, emitter 26, and collector contact 28 may be epitaxially grown simultaneously, followed by an ion implantation process for the emitter 26 and collector contact 28, and a separate ion implantation process for the extrinsic base 24.

[0038] Return to reference Figure 1 For example, the contact 32 can be formed by conventional photolithography, etching and deposition processes. For example, after depositing the interlayer dielectric material, a trench can be formed in the interlayer dielectric material to expose the external base 24, the emitter 26, the collector contact 28 and the gate structure 20. After the above-mentioned silicide process, a conductive material can be formed (e.g., deposited) in the trench on the silicide contact. Any excess conductive material can be removed by a conventional chemical mechanical planarization (CMP) process. The conductive material can be aluminum, tungsten, etc., with an optional liner, such as TiN or TaN.

[0039] Bipolar transistors can be utilized in system-on-chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies a much smaller area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0040] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die or in a packaged form. In the latter case, the chip is installed in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having surface interconnects or buried interconnects, or both surface interconnects and buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product including an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units.

[0041] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: collector; a base region located above the collector; an emitter laterally connected to the base region; as well as An external base connected to the base region.

2. The structure according to claim 1, wherein: The extrinsic base is laterally connected to the base region.

3. The structure of claim 1 further comprising a gate structure located above the base region, the gate structure separating the extrinsic base from the emitter, and wherein both the extrinsic base and the emitter are partially located below the gate structure.

4. The structure according to claim 3, wherein: The gate structure has the same width as the base region.

5. The structure according to claim 3, wherein: The gate structure has a different width than the base region.

6. The structure according to claim 1, wherein: The emitter and the extrinsic base are epitaxial semiconductor materials on the top semiconductor layer of semiconductor-on-insulator technology.

7. The structure according to claim 1, wherein: From a top view perspective, the gate structure is in an "I" shape.

8. The structure according to claim 7, wherein: The emitter is located at a side of the gate structure, and the external base is located at an end of the gate structure.

9. The structure according to claim 1, further comprising: a second base region located above the collector; a first gate structure located on the base region; as well as a second gate structure, which is located on the second base region, The emitter is located between the first gate structure and the second gate structure, and is laterally connected to the base region and the second base region.

10. The structure according to claim 9, wherein: The extrinsic base region is located on a side of the first gate structure and the second gate structure opposite to the emitter.

11. A structure comprising: a semiconductor region of a first conductivity type; a subcollector electrode located above the semiconductor region and comprising a second conductivity type; a base region located above the subcollector and also comprising the first conductivity type; a gate structure located above the base region; an emitter located on a first side of the gate structure; and An external base is located at the second side of the gate structure.

12. The structure according to claim 11, wherein: The emitter and the extrinsic base are separated from each other by the gate structure and are laterally connected to the base region.

13. The structure according to claim 11, wherein: The base region includes p-SiGe material.

14. The structure according to claim 11, wherein: The base region is partially located between the buried oxide layers.

15. The structure according to claim 14, wherein: The emitter and the extrinsic base include a semiconductor-on-insulator (SOI) substrate.

16. The structure of claim 11, wherein: The gate structure includes an "I" shape, the emitter is located at both sides of the gate structure, and the external base is located at an end of the gate structure.

17. The structure of claim 11, wherein: The gate structure has the same width as the base region.

18. The structure of claim 11, wherein: The gate structure is a gate contact structure forming a four-terminal bipolar transistor.

19. The structure of claim 11, further comprising: a second base region located above the collector; as well as a second gate structure located on the second base region; The emitter is located between the gate structure and the second gate structure, and is laterally connected to the base region and the second base region.

20. A method comprising: forming a collector; forming a base region above the collector; forming an emitter laterally connected to the base region; as well as An extrinsic base is formed connected to the base region.

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