Heterojunction bipolar transistor and forming method thereof
By adopting a first conductive structure including an electrical contact structure, a barrier structure and a conductive layer in the heterojunction bipolar transistor, the complex formation process, high cost and leakage problems in the prior art are solved, and process simplification and cost reduction are achieved.
Patent Information
- Application Number
- CN202411545880.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-03-18
AI Technical Summary
The existing heterojunction bipolar transistors have complex and high cost, and have leakage problems.
A heterojunction bipolar transistor is adopted, which includes a first conductive structure located on the surface of the first emission layer. The first conductive structure consists of an electrical contact structure, a barrier structure and a conductive layer. The electrical contact structure forms an ohmic contact with the first emission layer. The conductive layer is used for conduction, and the barrier structure prevents the ions of the conductive layer from diffusing to the first emission layer.
The process flow is simplified, the emitter electrode layer is omitted, the device leakage is avoided, and the cost is reduced.
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Figure CN119653792A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a heterojunction bipolar transistor and a method for forming the same. Background Art
[0002] Heterojunction Bipolar Transistor (HBT) is a transistor composed of an emitter, a base and a collector. The emitter uses a lightly doped wide bandgap, and the base uses a heavily doped narrow bandgap. The emission efficiency is determined by the bandgap energy difference. The main function is current gain, such as gain collector current or gain base current. Heterojunction bipolar transistor devices have the characteristics of stable performance, high speed and high frequency. Heterojunction bipolar transistor technology has become one of the mainstream technologies in the RF integrated circuit market and has a profound impact on the development of modern communication technology.
[0003] However, the existing process of forming heterojunction bipolar transistors needs to be improved. Summary of the invention
[0004] The technical problem solved by the present invention is to provide a heterojunction bipolar transistor and a forming method thereof, so as to improve the forming process of the heterojunction bipolar transistor.
[0005] To solve the above technical problems, the technical solution of the present invention provides a heterojunction bipolar transistor, comprising: a substrate, the substrate comprising a first region, a second region and a third region in sequence in a first direction, the second region being located between the first region and the third region, and the first direction being parallel to the substrate surface; a collector layer located on the substrate; a base layer located on the collector layer in the first region and the second region; a first emitter layer located on the base layer in the first region; a base electrode layer located on the base layer in the second region; a collector layer located on the collector layer in the third region; a first conductive structure located on the surface of the first emitter layer, the first conductive structure comprising an electrical contact structure, a blocking structure located on the electrical contact structure and a conductive layer located on the blocking structure, the electrical contact structure comprising at least one electrical contact layer, ions of a material of the electrical contact layer diffuse into the first emitter layer to form an ohmic contact, the blocking structure is used to block the ions of the conductive layer from diffusing into the first emitter layer, and the thickness of the blocking structure is greater than the thickness of the electrical contact layer; a second conductive structure located on the base electrode layer and a third conductive structure located on the collector layer, the second conductive structure and the third conductive structure being the same as the first conductive structure.
[0006] Optionally, the resistance of the conductive layer is smaller than the resistance of the electrical contact layer.
[0007] Optionally, the material of the conductive layer includes gold; and the material of the electrical contact layer includes platinum.
[0008] Optionally, the electrical contact structure further includes: a plurality of adhesive layers, and the plurality of adhesive layers include: a first adhesive layer located between the electrical contact layer and the first emission layer.
[0009] Optionally, the electrical contact structure further includes: a second adhesive layer located between two adjacent electrical contact layers.
[0010] Optionally, the material of the first adhesive layer includes titanium.
[0011] Optionally, the blocking structure includes a first blocking layer and a second blocking layer, the first blocking layer is located between the second blocking layer and the conductive layer, the second blocking layer is located between the electrical contact structure and the first blocking layer, and the thickness of the first blocking layer is greater than the thickness of the electrical contact layer.
[0012] Optionally, the thickness of the electrical contact layer is in a range of 50 angstroms to 100 angstroms; and the thickness of the first barrier layer is in a range of 300 angstroms to 400 angstroms.
[0013] Optionally, the material of the first barrier layer includes platinum.
[0014] Optionally, the material of the second barrier layer includes titanium.
[0015] Optionally, the thickness of the second barrier layer is greater than the thickness of the first adhesive layer.
[0016] Optionally, the thickness of the first adhesive layer ranges from 50 angstroms to 100 angstroms; and the thickness of the second barrier layer ranges from 300 angstroms to 400 angstroms.
[0017] Optionally, the thickness of the first barrier layer is greater than the thickness of the second barrier layer.
[0018] Optionally, the thickness of the conductive layer ranges from 9000 angstroms to 10000 angstroms.
[0019] Optionally, the first conductive structure further includes: an anti-reflection layer located on the top surface of the conductive layer.
[0020] Correspondingly, the technical solution of the present invention also provides a method for forming a heterogeneous bipolar transistor, comprising: providing a substrate, the substrate including a first region, a second region and a third region in sequence in a first direction, the second region being located between the first region and the third region, and the first direction being parallel to the substrate surface; forming a collector layer located on the substrate; forming a base layer on the collector layer located in the first region and the second region; forming a first emitter layer on the base layer located in the first region; forming a base electrode layer on the base layer located in the second region; forming a collector layer on the collector layer located in the third region; forming a first conductive structure located on the surface of the first emitter layer, the first conductive structure including an electrical contact structure, a blocking structure located on the electrical contact structure and a conductive layer located on the blocking structure, the electrical contact structure including at least one electrical contact layer, ions of a material of the electrical contact layer diffuse into the first emitter layer to form an ohmic contact, the blocking structure is used to block the ions of the conductive layer from diffusing into the first emitter layer, and the thickness of the blocking structure is greater than the thickness of the electrical contact layer; forming a second conductive structure located on the base electrode layer, forming a third conductive structure located on the collector layer, the second conductive structure and the third conductive structure are formed simultaneously with the first conductive structure.
[0021] Optionally, the method for forming the base electrode layer and the collector layer includes: forming a collector layer, a base material layer located on the collector layer, and a first emission material layer located on the base material layer on a substrate; patterning the first emission material layer to form a first emission layer on the base material layer on the first region; forming a base electrode layer on the base material layer in the second region; etching the base material layer to form a base layer on the collector layers on the first region and the second region; and forming a collector layer on the collector layer in the third region.
[0022] Optionally, the method for forming the first conductive structure, the second conductive structure and the third conductive structure includes: forming an electrical contact structure on a base electrode layer, a collector layer and a first emission layer, the electrical contact structure including at least one electrical contact layer; forming a blocking structure on the electrical contact structure; and forming a conductive layer on the blocking structure.
[0023] Optionally, forming the electrical contact structure further includes: forming a first adhesive layer between the electrical contact layer and the first emission layer.
[0024] Optionally, when the electrical contact structure includes multiple electrical contact layers, forming the electrical contact structure further includes: forming a second adhesive layer between two adjacent electrical contact layers.
[0025] Optionally, the process of forming the electrical contact layer includes a metal evaporation process; and the process of forming the conductive layer includes a metal evaporation process.
[0026] Optionally, forming the blocking structure includes: forming a first blocking layer and a second blocking layer, the first blocking layer is located between the second blocking layer and the conductive layer, the second blocking layer is located between the electrical contact structure and the first blocking layer, and the thickness of the first blocking layer is greater than the thickness of the electrical contact layer.
[0027] Optionally, after forming the base electrode layer, the method further includes: performing a first annealing treatment on the base electrode layer to form an ohmic contact between the base electrode layer and the base layer.
[0028] Optionally, after forming the first conductive structure, the second conductive structure and the third conductive structure, the method further includes: performing a second annealing treatment to make the collector layer form an ohmic contact with the collector layer, and to make the first conductive structure form an ohmic contact with the first emitter layer.
[0029] Optionally, the process parameters of the second annealing treatment include: a temperature range of 350 degrees Celsius to 360 degrees Celsius; a time range of 2 minutes to 5 minutes.
[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0031] The heterojunction bipolar transistor of the present invention comprises a first conductive structure located on the surface of the first emission layer, the first conductive structure comprises an electrical contact structure, a blocking structure located on the electrical contact structure, and a conductive layer located on the blocking structure, the electrical contact structure is used to form an ohmic contact with the first emission layer, the conductive layer is used to conduct electricity, and the blocking structure is used to block the ions of the conductive layer from diffusing into the first emission layer, so as to avoid excessive ions diffusing into the first emission layer and causing device leakage. The first conductive structure combines the functions of ohmic contact, diffusion blocking, and conduction, omits the emission electrode layer, and can simplify the process flow.
[0032] The heterojunction bipolar transistor formed by the formation method of the present invention forms a first conductive structure on the surface of the first emission layer, the first conductive structure includes an electrical contact structure, a blocking structure located on the electrical contact structure, and a conductive layer located on the blocking structure, the electrical contact structure is used to form an ohmic contact with the first emission layer, the conductive layer is used for conducting electricity, and the blocking structure is used to block the ions of the conductive layer from diffusing into the first emission layer, so as to avoid excessive ions diffusing into the first emission layer and causing device leakage. The first conductive structure combines the functions of ohmic contact, diffusion blocking, and conduction, and can simplify the process flow; in addition, the process of forming a separate emission electrode layer on the first emission layer is omitted, saving the mask cost.
[0033] Furthermore, an annealing process can be used to make the collector layer and the first conductive structure form ohmic contacts with the collector layer and the first emitter layer respectively, thereby simplifying the annealing process and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 is a schematic structural diagram of a heterojunction bipolar transistor in one embodiment;
[0035] Figures 2 to 8 It is a structural schematic diagram of the process of forming a heterojunction bipolar transistor in an embodiment of the present invention. DETAILED DESCRIPTION
[0036] As described in the background art, the existing process of forming heterojunction bipolar transistors needs to be improved.
[0037] Figure 1 1 is a schematic diagram of the structure of a heterojunction bipolar transistor in one embodiment.
[0038] Please refer to Figure 1 The heterojunction bipolar transistor comprises: a substrate 100, wherein the substrate comprises a first region I, a second region II and a third region III in sequence in a first direction X, wherein the second region II is located between the first region I and the third region III, and the first direction X is parallel to the surface of the substrate 100; a collector layer 101 located on the substrate 100, wherein the thickness of the collector layer 101 on the first region I and the second region II is greater than the thickness of the collector layer 101 on the third region III; a base layer 102 located on the collector layer 101 of the first region I and the second region II; a first emission layer 103 located on the base layer 102 of the first region I; an emission electrode layer 104 located on the first emission layer 103; and a base electrode layer 106 located on the base layer 102 of the second region II; A collector layer 108 located on the collector layer 101 of the third region III; a protective layer 110 located on the surface of the collector layer 101, the side wall surface and the top surface of the collector layer 108, the surface of the base layer 102, the side wall surface and the top surface of the base electrode layer 106, the side wall surface of the first emitter layer 103, and the top surface and the side wall surface of the emitter electrode layer 104, the protective layer 110 exposing part of the top surface of the collector layer 108, part of the top surface of the base electrode layer 106, and part of the top surface of the emitter electrode layer 104; a conductive structure 105 located on the top surface of the collector layer 108, the top surface of the base electrode layer 106, and the top surface of the emitter electrode layer 104 exposed by the protective layer 110.
[0039] In the heterojunction bipolar transistor, an emitter electrode layer 104 needs to be formed on the first emitter layer 103 and an ohmic contact is formed by annealing, and then the emitter electrode layer 104 is connected to the conductive structure 105; a base electrode layer 106 needs to be formed on the base layer 102 and an ohmic contact is formed by annealing, and then the base electrode layer 106 is connected to the conductive structure 105; a collector layer 108 needs to be formed on the collector layer 101 and an ohmic contact is formed by annealing, and then the collector layer 108 is connected to the conductive structure 105. The emitter electrode layer 104, the base electrode layer 106 and the collector layer 108 require different formation processes and annealing processes, which makes the formation process of the heterojunction bipolar transistor more complicated and costly.
[0040] In order to solve the above problems, the present invention provides a heterojunction bipolar transistor and a method for forming the same, comprising a first conductive structure located on the surface of the first emission layer, the first conductive structure comprising an electrical contact structure, a blocking structure located on the electrical contact structure, and a conductive layer located on the blocking structure, the electrical contact structure is used to form an ohmic contact with the first emission layer, the conductive layer is used for conducting electricity, and the blocking structure is used to block the ions of the conductive layer from diffusing into the first emission layer, so as to avoid excessive ions diffusing into the first emission layer and causing device leakage. The first conductive structure combines the functions of ohmic contact, diffusion blocking, and conduction, omits the emission electrode layer, and can simplify the process flow.
[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0042] Figures 2 to 8 It is a structural schematic diagram of the process of forming a heterojunction bipolar transistor in an embodiment of the present invention.
[0043] Please refer to Figure 2 , provide a substrate 200, wherein the substrate 200 includes a first region I, a second region II and a third region III in sequence in a first direction X, wherein the second region II is located between the first region I and the third region III, and the first direction X is parallel to the surface of the substrate 200; form a collector layer 201, a base material layer 202 located on the collector layer 201, and a first emission material layer 204 located on the base material layer 202 on the substrate 200.
[0044] In this embodiment, the material of the substrate 200 is silicon.
[0045] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
[0046] In this embodiment, the collector layer 201 is doped with first ions; the base material layer 202 is doped with second ions, the electrical type of the first ions is different from the electrical type of the second ions, and the doping concentration of the second ions is greater than the doping concentration of the first ions.
[0047] The first emission material layer 204 is doped with third ions, the electrical type of the third ions is different from the electrical type of the second ions, the electrical type of the third ions is the same as the electrical type of the first ions, the doping concentration of the third ions is greater than the doping concentration of the first ions, and the doping concentration of the third ions is less than the doping concentration of the second ions.
[0048] In this embodiment, the collector layer 201 has a doping concentration of 1E16 atoms / cm 3 N-type gallium arsenide (GaAs); the base material layer 202 has a doping concentration of 1E19atoms / cm 3 The first emission material layer 204 has a doping concentration of 1E17atoms / cm 3 N-type gallium arsenide.
[0049] In this embodiment, a second emission material layer 203 is further formed between the first emission material layer 204 and the base material layer 202 .
[0050] The material of the second emission material layer 203 includes N-type indium gallium phosphide (InGaP).
[0051] In this embodiment, the doping ion concentration in the second emission material layer 203 is less than the doping ion concentration in the first emission material layer 204 .
[0052] The second emission material layer 203 is used to subsequently form a second emission layer, and the first emission material layer 204 is used to subsequently form a first emission layer. The first emission layer and the second emission layer together constitute an emission structure. The ion doping type of the second emission layer is opposite to the ion doping type of the base material layer 202, and can form a PN junction with the base material layer 202; the first emission layer is used to form an ohmic contact with the first conductive structure.
[0053] In this embodiment, the doping ion concentration in the second emission material layer 203 is less than the doping ion concentration in the base material layer 202 .
[0054] In other embodiments, the second emission material layer may not be formed.
[0055] In this embodiment, the process of forming the collector layer 201 includes an epitaxial growth process; the process of forming the base material layer 202 includes an epitaxial growth process; the process of forming the first emission material layer 204 includes an epitaxial growth process; and the process of forming the second emission material layer 203 includes an epitaxial growth process.
[0056] In this embodiment, the substrate 200 includes a device region and an isolation region, and the device region includes a first region I, a second region II, and a third region III.
[0057] Please refer to Figure 3 , patterning the first emission material layer 204, and forming a first emission layer 205 on the second emission material layer 203 on the first region I.
[0058] The method for patterning the first emission material layer 204 includes: forming a mask layer (not shown) on the first emission material layer 204; etching the first emission material layer 204 using the mask layer as a mask until the surface of the second emission material layer 203 is exposed, and forming a first emission layer 205 on the second emission material layer 203 on the first area I.
[0059] The process of etching the first emission material layer 204 includes a dry etching process.
[0060] Please refer to Figure 4 , a base electrode layer 206 is formed on the second emission material layer 203 in the second region II.
[0061] The method for forming the base electrode layer 206 includes: forming a patterned layer (not shown) on the substrate 200, wherein the patterned layer exposes a portion of the surface of the second emission material layer 203 on the second region II; forming a base electrode material layer (not shown) on the patterned layer and the exposed second emission material layer 203 using a metal evaporation process; removing the patterned layer and the base electrode material layer on the patterned layer, and forming a base electrode layer 206 on the second emission material layer 203 in the second region II.
[0062] The base electrode material layer includes a multi-layer metal film, and the material of the metal film includes platinum, titanium or gold.
[0063] In this embodiment, the base electrode layer 206 includes a platinum (Pt) film, a titanium (Ti) film, a platinum (Pt) film, and a gold (Au) film stacked in sequence.
[0064] Please continue to refer to Figure 4 , performing a first annealing treatment on the base electrode layer 206 so that the base electrode layer 206 forms an ohmic contact with the base material layer 202 .
[0065] After annealing, ions of the base electrode layer 206 material diffuse into the base material layer 202 , so that the base electrode layer 206 forms an ohmic contact with the base material layer 202 , and the base electrode layer 206 penetrates the second emission material layer 203 .
[0066] The process parameters of the first annealing treatment include: a temperature range of 390 degrees Celsius to 410 degrees Celsius; and a time range of 2 minutes to 5 minutes.
[0067] Please refer to Figure 5 , the base material layer 202 and the second emission material layer 203 are etched to form a base layer 207 and a second emission layer 208 on the collector layer 201 on the first region I and the second region II.
[0068] In this embodiment, the process of etching the base material layer 202 also includes: removing part of the collector layer 201, so that the thickness of the collector layer 201 on the first region I and the second region II is greater than the thickness of the collector layer 201 on the third region III.
[0069] Please continue to refer to Figure 5 , ion implantation is performed on the isolation region to electrically isolate the isolation region from the device region.
[0070] In this embodiment, the implanted ions for ion implantation into the isolation region include helium ions.
[0071] Please refer to Figure 6 , a collector layer 220 is formed on the collector layer 201 on the third region III.
[0072] The method for forming the collector layer 220 includes: forming a patterned layer (not shown) on the substrate 200, wherein the patterned layer exposes a portion of the surface of the collector layer 201 on the third region III; forming a collector material layer (not shown) on the patterned layer and the exposed collector layer 201 using a metal evaporation process; removing the patterned layer and the collector material layer on the patterned layer, and forming a collector layer 220 on the collector layer 201 in the third region III.
[0073] The collector material layer includes a multi-layer metal film, and the material of the metal film includes gold germanium, nickel or gold.
[0074] In this embodiment, the collector layer 220 includes a gold-germanium (AuGe) alloy film, a nickel (Ni) film, and a gold (Au) film stacked in sequence.
[0075] Please continue to refer to Figure 6 A protective layer 209 is formed on the surface of the collector layer 201, the side wall surface and top surface of the collector layer 220, the surface of the second emission layer 208, the side wall surface and top surface of the base electrode layer 206, and the side wall surface and top surface of the first emission layer 205, and the protective layer 209 exposes part of the top surface of the first emission layer 205, part of the top surface of the base electrode layer 206, and part of the top surface of the collector layer 220.
[0076] In this embodiment, the material of the protection layer 209 includes silicon nitride.
[0077] Please refer to Figure 7 and Figure 8 , Figure 8 yes Figure 7 An enlarged schematic diagram of the first conductive structure 210 is shown in FIG. 2 , in which the first conductive structure 210 is formed on the top surface of the first emitter layer 205 exposed by the protective layer 209; the second conductive structure 221 is formed on the top surface of the base electrode layer 206 exposed by the protective layer 209; and the second conductive structure 222 is formed on the top surface of the collector layer 220 exposed by the protective layer 209.
[0078] In this embodiment, the first conductive structure 210 , the second conductive structure 221 , and the second conductive structure 222 are formed simultaneously, and the first conductive structure 210 , the second conductive structure 221 , and the second conductive structure 222 are the same.
[0079] The first conductive structure 210 , the second conductive structure 221 and the second conductive structure 222 are the same, that is, the first conductive structure 210 , the second conductive structure 221 and the second conductive structure 222 have the same structural composition, film thickness and material.
[0080] The method for forming the first conductive structure 210, the second conductive structure 221 and the second conductive structure 222 includes: forming an electric contact structure on the first emission layer 205, the base electrode layer 206 and the collector layer 220, forming a blocking structure on the electric contact structure, and forming a conductive layer 215 on the blocking structure, wherein the electric contact structure includes at least one electric contact layer, and the electric contact layer is used to form an ohmic contact with the first emission layer 205.
[0081] In this embodiment, the electrical contact structure includes an electrical contact layer 212 .
[0082] In this embodiment, the thickness of the electrical contact layer 212 is in a range of 50 angstroms to 100 angstroms.
[0083] The electrical contact layer 212 within the above-mentioned thickness range can provide a good ohmic contact effect, but will not cause device leakage due to too much ions diffusing into the first emission layer 205 due to being too thick.
[0084] In other embodiments, the number of the electrical contact layer is 2 or more.
[0085] When the number of the electrical contact layers is 2 or more, the thickness range of the electrical contact layers is the same, which is 50 angstroms to 100 angstroms. The total thickness range of the electrical contact layers is less than 1000 angstroms.
[0086] In this embodiment, forming the electrical contact structure further includes: forming a first adhesive layer 211 on the first emission layer 205 , and forming an electrical contact layer 212 on the first adhesive layer 211 , wherein the first adhesive layer 211 is located between the electrical contact layer 212 and the first emission layer 205 .
[0087] The first adhesive layer 211 provides good adhesion and can increase the adhesion between the electrical contact layer and the first emission layer 205 .
[0088] In this embodiment, the material of the first adhesive layer 211 is different from the material of the electrical contact layer 212 ; the material of the first adhesive layer 211 is different from the material of the conductive layer 215 .
[0089] In this embodiment, the material of the first adhesive layer 211 includes titanium.
[0090] In this embodiment, the thickness of the first adhesive layer 211 is in a range of 50 angstroms to 100 angstroms.
[0091] The first adhesive layer 211 within the thickness range can achieve good adhesion effect without causing material waste and increasing resistance.
[0092] In other embodiments, when the number of the electrical contact layers is 2 or more, the method for forming the electrical contact structure further includes: forming a second adhesive layer between two adjacent electrical contact layers.
[0093] In this embodiment, only the first adhesive layer 211 is illustrated.
[0094] The second adhesive layer provides good adhesion and can increase the adhesion between two adjacent electrical contact layers.
[0095] The thickness range of the plurality of layers of the second adhesive layer is the same as the thickness range of the first adhesive layer, so that the conductive structure can be formed using fewer types of metals, and the process and thickness can be better controlled.
[0096] The material of the second adhesive layer is the same as that of the first adhesive layer.
[0097] The thickness of the second adhesive layer ranges from 50 angstroms to 100 angstroms; the material of the second adhesive layer includes titanium. The total thickness of the second adhesive layer and the first adhesive layer is less than 1000 angstroms.
[0098] In this embodiment, the method for forming the first conductive structure 210, the second conductive structure 221 and the second conductive structure 222 further includes: forming an anti-reflection layer 216 on the top surface of the conductive layer 215. The anti-reflection layer 216 is used for anti-reflection during exposure.
[0099] In this embodiment, the material of the anti-reflection layer 216 is the same as that of the first adhesive layer 211. This allows the conductive structure to be formed using fewer types of metals, and the process and thickness can be better controlled.
[0100] In this embodiment, the material of the anti-reflection layer 216 includes titanium.
[0101] In this embodiment, the thickness of the anti-reflection layer 216 is in a range of 30 angstroms to 50 angstroms.
[0102] In other embodiments, the material of the anti-reflection layer and the material of the first adhesive layer may be different.
[0103] In other embodiments, the anti-reflection layer may not be formed.
[0104] In other embodiments, the first adhesive layer may not be formed.
[0105] In this embodiment, the material of the electrical contact layer is different from that of the conductive layer 215. The electrical contact layer has good catalytic performance and corrosion resistance, and the ions of the material of the electrical contact layer can easily diffuse to the first emission layer to form an ohmic contact under annealing.
[0106] In this embodiment, the resistance of the conductive layer 215 is less than the resistance of the electrical contact layer, so that the conductive layer 215 has good conductivity and stability, which can ensure smooth transmission of current in the device, and the chemical properties of gold are stable and not easy to react with other materials, thereby ensuring the long-term reliability of the device.
[0107] In this embodiment, the material of the conductive layer 215 includes gold; the material of the electrical contact layer 212 includes platinum.
[0108] In this embodiment, the blocking structure includes a first blocking layer 214 and a second blocking layer 213, the first blocking layer 214 is located between the second blocking layer 213 and the conductive layer 215, the second blocking layer 213 is located between the electrical contact structure and the first blocking layer 214, the first blocking layer 214 is used to block the ions of the conductive layer 215 from diffusing into the first emission layer 205, and the second blocking layer 213 is used to block the ions of the first blocking layer 214 from diffusing into the first emission layer 205.
[0109] In this embodiment, the material of the first barrier layer 214 is the same as that of the electrical contact layer 212, and the material of the first barrier layer 214 includes platinum, so that the conductive structure can be formed using fewer types of metals, and the process and thickness can be better controlled.
[0110] In other embodiments, the material of the first barrier layer and the material of the electrical contact layer may be different.
[0111] In this embodiment, the thickness of the first barrier layer 214 is greater than the thickness of the electrical contact layer 212 ; the thickness of the conductive layer 215 is greater than the thickness of the first barrier layer 214 .
[0112] In this embodiment, the thickness of the first barrier layer 214 is in a range of 300 angstroms to 400 angstroms.
[0113] The first barrier layer 214 within the thickness range can play a good barrier role without causing material waste and increasing resistance.
[0114] In other embodiments, the first barrier layer may not be formed.
[0115] In this embodiment, the material of the second barrier layer 213 is the same as that of the first adhesive layer 211, and the material of the second barrier layer 213 includes titanium, so that the conductive structure can be formed using fewer types of metals, and the process and thickness can be better controlled.
[0116] In other embodiments, the material of the second barrier layer and the material of the first adhesive layer may be different.
[0117] In this embodiment, the thickness of the second barrier layer 213 is greater than that of the electrical contact layer 212 ; the thickness of the second barrier layer 213 is greater than that of the first adhesive layer 211 ; and the thickness of the conductive layer 215 is greater than that of the second barrier layer 213 .
[0118] The thickness of the second barrier layer 213 is in a range of 300 angstroms to 400 angstroms.
[0119] The second barrier layer 213 within the thickness range can play a good barrier role without causing material waste and increasing resistance.
[0120] In this embodiment, the thickness of the first barrier layer 214 is greater than the thickness of the second barrier layer 213 .
[0121] In other embodiments, the thickness of the first barrier layer can be less than the thickness of the second barrier layer.
[0122] In this embodiment, the thickness of the conductive layer 215 is greater than the total thickness of the barrier structure, thereby ensuring that the first conductive structure 210 has sufficiently good conductive properties.
[0123] In this embodiment, the thickness of the conductive layer 215 ranges from 9000 angstroms to 10000 angstroms.
[0124] In this embodiment, the process of forming the electrical contact layer includes a metal evaporation process; the process of forming the conductive layer 215 includes a metal evaporation process; the process of forming the first adhesive layer 211 includes a metal evaporation process; and the process of forming the second adhesive layer includes a metal evaporation process.
[0125] Please continue to refer to Figure 7 , performing a second annealing treatment on the collector layer 220 and the first conductive structure 210 , so that the collector layer 220 forms an ohmic contact with the collector layer 201 , and so that the first conductive structure 210 forms an ohmic contact with the first emitter layer 205 .
[0126] In this embodiment, the process parameters of the second annealing treatment include: a temperature range of 350 degrees Celsius to 360 degrees Celsius; and a time range of 2 minutes to 5 minutes.
[0127] The first conductive structure 210 is in ohmic contact with the first emitter layer 205 ; the first conductive structure 210 is in electrical contact with the base electrode layer 206 and the collector layer 220 .
[0128] The blocking structure is located between the electrical contact structure and the conductive layer 215. During the annealing process, the ions in the electrical contact layer 212 diffuse into the first emission layer 205 to form an ohmic contact. The blocking structure can block the ions in the conductive layer 215 from diffusing into the first emission layer 205 during the annealing process, thereby preventing excessive ions from diffusing into the first emission layer 205 and causing device leakage.
[0129] The first conductive structure 210 includes an electrical contact structure, a blocking structure located on the electrical contact structure, and a conductive layer 215 located on the blocking structure. The electrical contact structure is used to form an ohmic contact with the first emission layer 205. The conductive layer 215 is used for conducting electricity. The blocking structure is used to block the ions of the conductive layer from diffusing into the first emission layer 205, so as to prevent excessive ions from diffusing into the first emission layer 205 and causing device leakage. The first conductive structure 210 combines the functions of ohmic contact, diffusion blocking, and conduction, which can simplify the process flow; in addition, the process of forming a separate emission electrode layer on the first emission layer 205 is omitted, saving the mask cost.
[0130] In addition, an annealing process can be used to make the collector layer 220 and the first conductive structure 210 form ohmic contacts with the collector layer 201 and the first emitter layer 205 respectively, thereby simplifying the annealing process and saving costs.
[0131] Accordingly, the embodiment of the present invention further provides a heterojunction bipolar transistor, please continue to refer to Figure 7 and Figure 8 ,include:
[0132] A substrate 200, wherein the substrate 200 includes a first region I, a second region II and a third region III in sequence in a first direction X, wherein the second region II is located between the first region I and the third region III, and the first direction X is parallel to a surface of the substrate 200;
[0133] A current collecting layer 201 located on the substrate 200;
[0134] A base layer 207 located on the collector layer 201 of the first region I and the second region II;
[0135] A first emission layer 205 located on the base layer 207 of the first region I;
[0136] A base electrode layer 206 located on the base layer 207 of the second region II;
[0137] A collector layer 220 located on the collector layer 201 in the third region III;
[0138] a first conductive structure 210 located on the surface of the first emission layer 205, the first conductive structure 210 comprising an electrical contact structure, a blocking structure located on the electrical contact structure, and a conductive layer 215 located on the blocking structure, the electrical contact structure comprising at least one electrical contact layer, ions of a material of the electrical contact layer diffuse into the first emission layer 205 to form an ohmic contact, the blocking structure is used to block ions of the conductive layer 215 from diffusing into the first emission layer 205, and the thickness of the blocking structure is greater than the thickness of the electrical contact layer;
[0139] The second conductive structure 221 located on the base electrode layer 206 and the second conductive structure 222 located on the collector layer 220 , wherein the second conductive structure 221 and the second conductive structure 222 are the same as the first conductive structure 210 .
[0140] The heterojunction bipolar transistor includes a first conductive structure 210 located on the surface of the first emission layer 205, the first conductive structure 210 includes an electrical contact structure, a blocking structure located on the electrical contact structure, and a conductive layer 215 located on the blocking structure, the electrical contact structure is used to form an ohmic contact with the first emission layer 205, the conductive layer 215 is used for conduction, and the blocking structure is used to block the ions of the conductive layer 215 from diffusing into the first emission layer 205, so as to avoid excessive ions diffusing into the first emission layer 205 and causing device leakage. The first conductive structure 210 combines the functions of ohmic contact, diffusion blocking, and conduction, omits the emission electrode layer, and can simplify the process flow.
[0141] In this embodiment, the electrical contact structure further includes: a first adhesive layer 211 located between the electrical contact layer 212 and the first emission layer 205 .
[0142] In other embodiments, the electrical contact structure further includes: a second adhesive layer located between two adjacent electrical contact layers.
[0143] In this embodiment, the first conductive structure 210 further includes an anti-reflection layer 216 located on the top surface of the conductive layer 215 .
[0144] In this embodiment, the material of the electrical contact layer 212 is different from the material of the conductive layer 215 .
[0145] In this embodiment, the resistance of the conductive layer 215 is smaller than the resistance of the electrical contact layer 212 .
[0146] In this embodiment, the material of the conductive layer 215 includes gold; the material of the electrical contact layer 212 includes platinum.
[0147] In this embodiment, the material of the first adhesive layer 211 is different from the material of the electrical contact layer 212 ; the material of the first adhesive layer 211 is different from the material of the conductive layer 215 .
[0148] In this embodiment, the material of the first adhesive layer includes titanium.
[0149] In this embodiment, the blocking structure includes a first blocking layer 214 and a second blocking layer 213, the first blocking layer 214 is located between the second blocking layer 213 and the conductive layer 215, the second blocking layer 213 is located between the electrical contact structure and the first blocking layer 214, and the thickness of the first blocking layer 214 is greater than the thickness of the electrical contact layer 212.
[0150] In this embodiment, the material of the first barrier layer 214 is the same as that of the electrical contact layer 212 , and the material of the first barrier layer 214 includes platinum.
[0151] In this embodiment, the thickness of the electrical contact layer 212 is in a range of 50 angstroms to 100 angstroms; the thickness of the first barrier layer 214 is in a range of 300 angstroms to 400 angstroms.
[0152] In this embodiment, the material of the second barrier layer 213 includes titanium.
[0153] In this embodiment, the thickness of the second barrier layer 213 is greater than the thickness of the first adhesive layer 211 .
[0154] In this embodiment, the thickness of the first adhesive layer 211 is in a range of 50 angstroms to 100 angstroms; the thickness of the second barrier layer 213 is in a range of 300 angstroms to 400 angstroms.
[0155] In this embodiment, the thickness of the conductive layer 215 ranges from 9000 angstroms to 10000 angstroms.
[0156] In this embodiment, the thickness of the first barrier layer 214 is greater than the thickness of the second barrier layer 213 .
[0157] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A heterojunction bipolar transistor, characterized in that: include: A substrate, wherein the substrate includes a first region, a second region and a third region in sequence in a first direction, the second region is located between the first region and the third region, and the first direction is parallel to a surface of the substrate; a current collecting layer located on the substrate; A base layer located on the collector layer in the first and second regions; a first emitting layer located on the base layer in the first region; a base electrode layer located on the base layer of the second region; a collector layer located on the collector layer in the third region; a first conductive structure located on the surface of the first emission layer, the first conductive structure comprising an electrical contact structure, a blocking structure located on the electrical contact structure, and a conductive layer located on the blocking structure, the electrical contact structure comprising at least one electrical contact layer, ions of a material of the electrical contact layer diffuse into the first emission layer to form an ohmic contact, the blocking structure is used to block ions of the conductive layer from diffusing into the first emission layer, and the thickness of the blocking structure is greater than the thickness of the electrical contact layer; A second conductive structure located on the base electrode layer and a third conductive structure located on the collector layer, wherein the second conductive structure and the third conductive structure are the same as the first conductive structure.
2. The heterojunction bipolar transistor according to claim 1, characterized in that: The electrical resistance of the conductive layer is lower than the electrical resistance of the electrical contact layer.
3. The heterojunction bipolar transistor according to claim 2, characterized in that: The material of the conductive layer includes gold; the material of the electrical contact layer includes platinum.
4. The heterojunction bipolar transistor according to claim 1, wherein: The electrical contact structure further includes a first adhesive layer located between the electrical contact layer and the first emission layer.
5. The heterojunction bipolar transistor according to claim 4, characterized in that: The electrical contact structure further includes: a second adhesive layer located between two adjacent electrical contact layers.
6. The heterojunction bipolar transistor according to claim 4, characterized in that: The material of the first adhesive layer includes titanium.
7. The heterojunction bipolar transistor according to claim 4, characterized in that: The blocking structure includes a first blocking layer and a second blocking layer, the first blocking layer is located between the second blocking layer and the conductive layer, the second blocking layer is located between the electrical contact structure and the first blocking layer, and the thickness of the first blocking layer is greater than that of the electrical contact layer.
8. The heterojunction bipolar transistor according to claim 7, characterized in that: The thickness of the electrical contact layer is in a range of 50 angstroms to 100 angstroms; the thickness of the first barrier layer is in a range of 300 angstroms to 400 angstroms.
9. The heterojunction bipolar transistor according to claim 7, characterized in that: The material of the first barrier layer includes platinum.
10. The heterojunction bipolar transistor according to claim 7, characterized in that: The material of the second barrier layer includes titanium.
11. The heterojunction bipolar transistor according to claim 7, characterized in that: The second barrier layer has a thickness greater than that of the first adhesive layer.
12. The heterojunction bipolar transistor according to claim 11, characterized in that: The thickness of the first adhesive layer ranges from 50 angstroms to 100 angstroms; the thickness of the second barrier layer ranges from 300 angstroms to 400 angstroms.
13. The heterojunction bipolar transistor according to claim 7, characterized in that: The thickness of the first barrier layer is greater than the thickness of the second barrier layer.
14. The heterojunction bipolar transistor according to claim 1, wherein: The thickness of the conductive layer ranges from 9000 angstroms to 10000 angstroms.
15. The heterojunction bipolar transistor according to claim 1, wherein: The first conductive structure further includes an anti-reflection layer located on the top surface of the conductive layer.
16. A method for forming a heterogeneous bipolar transistor, characterized in that: include: Providing a substrate, wherein the substrate sequentially comprises a first region, a second region and a third region in a first direction, wherein the second region is located between the first region and the third region, and the first direction is parallel to a surface of the substrate; forming a current collecting layer on the substrate; forming a base layer on the collector layer in the first region and the second region; forming a first emission layer on the base layer in the first region; forming a base electrode layer on the base layer in the second region; forming a collector layer on the collector layer in the third region; forming a first conductive structure located on the surface of the first emission layer, the first conductive structure comprising an electrical contact structure, a blocking structure located on the electrical contact structure, and a conductive layer located on the blocking structure, the electrical contact structure comprising at least one electrical contact layer, ions of a material of the electrical contact layer diffuse into the first emission layer to form an ohmic contact, the blocking structure is used to block ions of the conductive layer from diffusing into the emission layer, and the thickness of the blocking structure is greater than the thickness of the electrical contact layer; A second conductive structure is formed on the base electrode layer, and a third conductive structure is formed on the collector layer. The second conductive structure and the third conductive structure are formed simultaneously with the first conductive structure.
17. The method for forming a heterobipolar transistor according to claim 16, wherein: The method for forming the base electrode layer and the collector layer includes: forming a collector layer, a base material layer located on the collector layer, and a first emission material layer located on the base material layer on a substrate; patterning the first emission material layer to form a first emission layer on the base material layer on the first region; forming a base electrode layer on the base material layer in the second region; etching the base material layer to form a base layer on the collector layer on the first region and the second region; and forming a collector layer on the collector layer in the third region.
18. The method for forming a heterobipolar transistor according to claim 17, wherein: The method for forming the first conductive structure, the second conductive structure and the third conductive structure includes: forming an electrical contact structure on a base electrode layer, a collector layer and a first emission layer, the electrical contact structure including at least one electrical contact layer; forming a blocking structure on the electrical contact structure; and forming a conductive layer on the blocking structure.
19. The method for forming a heterobipolar transistor according to claim 18, wherein: Forming the electrical contact structure further includes forming a first adhesive layer between the electrical contact layer and the first emission layer.
20. The method for forming a heterobipolar transistor according to claim 19, wherein: When the electrical contact structure includes multiple electrical contact layers, forming the electrical contact structure further includes: forming a second adhesive layer between two adjacent electrical contact layers.
21. The method for forming a heterobipolar transistor according to claim 18, wherein: The process of forming the electrical contact layer includes a metal evaporation process; the process of forming the conductive layer includes a metal evaporation process.
22. The method for forming a heterobipolar transistor according to claim 18, wherein: Forming the blocking structure includes: forming a first blocking layer and a second blocking layer, wherein the first blocking layer is located between the second blocking layer and the conductive layer, the second blocking layer is located between the electrical contact structure and the first blocking layer, and the thickness of the first blocking layer is greater than the thickness of the electrical contact layer.
23. The method for forming a heterobipolar transistor according to claim 17, wherein: After forming the base electrode layer, the method further includes: performing a first annealing treatment on the base electrode layer to form an ohmic contact between the base electrode layer and the base layer.
24. The method for forming a heterobipolar transistor according to claim 17, wherein: After forming the first conductive structure, the second conductive structure and the third conductive structure, the method further includes: A second annealing process is performed to make the collector layer form an ohmic contact with the collector layer, and to make the first conductive structure form an ohmic contact with the first emission layer.
25. The method for forming a heterobipolar transistor according to claim 24, wherein: The process parameters of the second annealing treatment include: a temperature range of 350 degrees Celsius to 360 degrees Celsius; and a time range of 2 minutes to 5 minutes.