Transistor and preparation method thereof

Abstract

The invention provides a transistor and a preparation method thereof. The transistor comprises a channel layer, a barrier layer, an etching barrier layer and a p-GaN layer, the barrier layer, the etching barrier layer and the p-GaN layer are sequentially stacked on the channel layer, and selective etching is performed through a mask, so that the p-GaN layer is provided with a step structure extending to the etching barrier layer. An etching barrier layer is added between a barrier layer and a p-GaN layer of an epitaxial structure, the etching speed of the etching barrier layer is low in the etching process, and the selection ratio of the p-GaN layer to the etching barrier layer is increased; meanwhile, the barrier layer can prevent the barrier layer from being etched, and the stability of the transistor is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronic devices, and in particular to a transistor and a method for preparing the same. Background Art

[0002] High Electron Mobility Transistor (HEMT) is a heterojunction field effect transistor that is widely used in wireless communications, automotive electronics and other fields.

[0003] The related art provides a transistor, the transistor structure includes: a channel layer, a barrier layer and a p-GaN layer.

[0004] During the transistor manufacturing process, the etching of the p-GaN layer will cause serious damage to the barrier layer, affecting the quality of the transistor. Summary of the invention

[0005] The disclosed embodiment provides a transistor and a method for manufacturing the same, which can significantly improve the p-GaN layer etching selectivity, prevent the barrier layer from being etched, and improve the stability of the transistor. The technical solution is as follows:

[0006] In one aspect, a transistor is provided, the transistor comprising: a channel layer, a barrier layer, an etch stop layer and a p-GaN layer;

[0007] The barrier layer, the etch stop layer and the p-GaN layer are sequentially stacked on the channel layer, and the p-GaN layer is provided with a step structure extending to the etch stop layer.

[0008] Optionally, the etching stop layer is In x Al y Ga z N layers, where x, y, and z are all greater than 0.

[0009] Optionally, the x is 0.1, the y is 0.2, and the z is 0.7.

[0010] Optionally, the etch stop layer has a thickness of 1-10 nm.

[0011] In another aspect, a method for manufacturing a transistor includes:

[0012] manufacturing a channel layer;

[0013] forming a barrier layer on the channel layer;

[0014] forming an etching stop layer on the barrier layer;

[0015] Fabricating a p-GaN layer on the etch stop layer;

[0016] The p-GaN layer is patterned so that the p-GaN layer has a step structure extending to the etching stop layer.

[0017] Optionally, the patterning of the p-GaN layer includes:

[0018] Growing a SiO2 dielectric layer on the p-GaN layer;

[0019] forming a photoresist mask layer on the SiO2 dielectric layer;

[0020] Under the protection of the photoresist mask layer, etching the SiO2 dielectric layer;

[0021] The p-GaN layer is etched under the shielding of the etched SiO2 dielectric layer.

[0022] Optionally, etching the p-GaN layer under the shielding of the etched SiO2 dielectric layer comprises:

[0023] Setting etching conditions for the main etching process and the over-etching process;

[0024] Under the etching conditions of the main etching procedure and the over-etching procedure, the p-GaN layer is etched while being shielded by the etched SiO2 dielectric layer.

[0025] Optionally, the etching conditions of the main etching procedure are as follows: etching pressure is 2-4 Mt, etching power is 140-160 W, bias power is 70-90 W, Cl2 gas flow rate is 40-60 sccm, and Ar gas flow rate is 1-10 sccm;

[0026] The etching conditions of the over-etching procedure are as follows: etching pressure is 4-6Mt, etching power is 140-160W, bias power is 20-40W, BCl3 gas flow rate is 20-40sccm, N2 gas flow rate is 10-20sccm, and SF6 gas flow rate is 10-20sccm.

[0027] Optionally, the etching stop layer is In x Al y Ga z N layers, where x, y, and z are all greater than 0.

[0028] Optionally, the x is 0.1, the y is 0.2, and the z is 0.7.

[0029] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0030] In the embodiment of the present disclosure, an etch barrier layer is added between the barrier layer and the p-GaN layer of the epitaxial structure, so that the etching rate of the etch barrier layer is slow during the etching process, thereby improving the selectivity of the p-GaN layer to the etch barrier layer; at the same time, the barrier layer is prevented from being etched during the etching process of the p-GaN layer, thereby improving the stability of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;

[0033] Figure 2 is a schematic diagram of the structure of another transistor provided by an embodiment of the present disclosure;

[0034] Figure 3 is a schematic diagram of the structure of another transistor provided by an embodiment of the present disclosure;

[0035] Figure 4 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure;

[0036] Figure 5 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure;

[0037] Figure 6 is a schematic diagram of a structure in a transistor manufacturing process provided by an embodiment of the present disclosure;

[0038] Figure 7 is a schematic diagram of a structure in a transistor manufacturing process provided by an embodiment of the present disclosure;

[0039] Figure 8 is a schematic diagram of a structure in a transistor manufacturing process provided by an embodiment of the present disclosure;

[0040] Fig. 9 is a schematic diagram of a structure in a transistor manufacturing process provided by an embodiment of the present disclosure;

[0041] Fig.10 is a schematic diagram of a structure in a transistor manufacturing process provided by an embodiment of the present disclosure;

[0042] Fig.11 It is a structural schematic diagram of a transistor manufacturing process provided by an embodiment of the present disclosure.

[0043] The reference numerals are as follows:

[0044] 101: channel layer; 102: barrier layer; 103: etching stop layer; 104: p-GaN layer; 105: buffer layer; 106: dielectric layer; 107: first electrode; 108: second electrode; 109: control electrode;

[0045] 201: Step structure. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0047] Figure 1 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure. Figure 1 , the transistor comprises: a channel layer 101, a barrier layer 102, an etching stop layer 103 and a p-GaN layer 104;

[0048] The barrier layer 102 , the etch stop layer 103 and the p-GaN layer 104 are sequentially stacked on the channel layer 101 , and the p-GaN layer 104 has a step structure extending to the etch stop layer 103 .

[0049] In the embodiment of the present disclosure, an etch barrier layer is added between the barrier layer and the p-GaN layer of the epitaxial structure, so that the etching rate of the etch barrier layer is slow during the etching process, thereby improving the selectivity of the p-GaN layer to the etch barrier layer; at the same time, the barrier layer is prevented from being etched during the etching process of the p-GaN layer, thereby improving the stability of the transistor.

[0050] In the embodiment of the present disclosure, the etching stop layer 103 is In x Al y Ga z N layers, where x, y, and z are all greater than 0, In x Al y Ga z N acts as an etch barrier.

[0051] In the related art, the AlGaN barrier layer is directly used as an etching barrier layer, the main etching rate (Main Etch, ME) of the p-GaN layer is 125.7 angstroms / min; the over etching rate (Over Etch, OE) of the p-GaN layer is 14.9 angstroms / min, and the etching rate of the AlGaN barrier layer is 0.98 angstroms / min; the selectivity of p-GaN / AlGaN is 15.2.

[0052] In the embodiment of the present disclosure, InAlGaN is used as an etching barrier layer, the main etching rate of the p-GaN layer is 125.7 angstroms / min; the over-etching rate of the p-GaN layer is 14.9 angstroms / min, and the etching rate of the InAlGaN barrier layer is 0.62 angstroms / min; the selectivity of p-GaN / InAlGaN is greater than 20.

[0053] The over-etching process is performed after the main etching process is completed.

[0054] That is, using InAlGaN as an etching barrier layer has a high selectivity ratio and can better avoid etching other film layers, thereby protecting the transistor structure.

[0055] In the embodiment of the present disclosure, x is 0.1, y is 0.2, and z is 0.7, which can provide good lattice matching and high chemical stability. Under the same etching conditions, the etching rate is slower, has a high selectivity, and can effectively protect the barrier layer.

[0056] In the disclosed embodiment, the thickness of the etch stop layer 103 may be 1-10 nm, which will not be too thin to cause etching to the barrier layer during etching, nor too thick to cause the overall thickness of the transistor to be too thick.

[0057] Exemplarily, the thickness of the etch stop layer 103 is 5 nm.

[0058] In the embodiment of the present disclosure, the channel layer 101 may be a GaN channel layer.

[0059] In the embodiment of the present disclosure, the barrier layer 102 may be an AlGaN barrier layer, and the thickness may be 20-50 nm.

[0060] Exemplarily, the barrier layer 102 has a thickness of 35 nm.

[0061] In the embodiment of the present disclosure, the thickness of the p-GaN layer 104 may be 75-150 nm.

[0062] Exemplarily, the p-GaN layer has a thickness of 100 nm.

[0063] In the embodiment of the present disclosure, the transistor may further include: a substrate 100 , a buffer layer 105 and a dielectric layer 106 .

[0064] The buffer layer 105, the channel layer 101, the barrier layer 102, the etch stop layer 103, the p-GaN layer 104 and the dielectric layer 106 are sequentially stacked on the substrate 101. The barrier layer 102, the etch stop layer 103, the p-GaN layer 104 and the dielectric layer 106 are provided with a step structure 201 extending to the etch stop layer 103, the step structure 201 has a step bottom surface and a step top surface, and the step bottom surface of the step structure 201 is located at the etch stop layer 103.

[0065] In the embodiment of the present disclosure, the transistor may further include: a first electrode, a second electrode and a control electrode.

[0066] Exemplarily, the first electrode, the second electrode and the control electrode may be a source electrode, a drain electrode and a gate electrode, respectively, wherein the source electrode and the drain electrode are located on the etching stop layer 103 , and the gate electrode is located on the dielectric layer 106 .

[0067] Figure 2 is a schematic diagram of the structure of another transistor provided by an embodiment of the present disclosure. Figure 2 The transistor may further include: a first electrode 107 , a second electrode 108 and a control electrode 109 , wherein the first electrode 107 and the second electrode 108 are connected to the channel layer 101 through the etching stop layer 103 and the barrier layer 102 .

[0068] Figure 3 is a schematic diagram of the structure of another transistor provided by an embodiment of the present disclosure. Figure 3 The transistor may further include: a first electrode 107 , a second electrode 108 and a control electrode 109 , wherein the first electrode 107 and the second electrode 108 are connected to the barrier layer 102 through the etching stop layer 103 .

[0069] In the embodiment of the present disclosure, the substrate 100 may be any one of substrates such as a sapphire substrate, a Si substrate, a SiC substrate, and a GaN substrate. The embodiment of the present disclosure does not limit the material of the substrate 100.

[0070] Exemplarily, the substrate 100 is a Si substrate.

[0071] Of course, in other embodiments, the transistor may not have a substrate, and the present disclosure is not limited to this.

[0072] In the embodiment of the present disclosure, the buffer layer 105 may be a GaN buffer layer.

[0073] In the embodiment of the present disclosure, the dielectric layer 106 may be a SiO 2 dielectric layer, and the thickness may be 190-210 nm.

[0074] Exemplarily, the dielectric layer 106 has a thickness of 200 nm.

[0075] In the embodiment of the present disclosure, the first electrode 107 and the second electrode 108 may include a first Ti sublayer, an Al sublayer, a second Ti sublayer, and a TiN sublayer (anti-oxidation sublayer) stacked in sequence.

[0076] In the embodiment of the present disclosure, the gate metal layer 109 may include a first Ti sub-layer, an Al sub-layer, and a second Ti sub-layer stacked in sequence.

[0077] Figure 4 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure. Figure 4 The method steps include:

[0078] S11 . Manufacturing a channel layer.

[0079] In the embodiment of the present disclosure, the channel layer may be a GaN channel layer.

[0080] S12, forming a barrier layer on the channel layer.

[0081] In the embodiment of the present disclosure, the barrier layer may be an AlGaN barrier layer, and the thickness may be 20-50 nm.

[0082] Exemplarily, the barrier layer thickness is 35 nm.

[0083] S13, forming an etching stop layer on the barrier layer.

[0084] In the embodiment of the present disclosure, the etching stop layer is In x Al y Ga z N layers, where x, y, and z are all greater than 0, In x Al y Ga z N acts as an etch barrier.

[0085] In the related art, the AlGaN barrier layer is directly used as an etching stop layer, the main etching rate of the p-GaN layer is 125.7 angstroms / min; the over-etching rate of the p-GaN layer is 14.9 angstroms / min, and the etching rate of the AlGaN barrier layer is 0.98 angstroms / min; the selectivity of p-GaN / AlGaN is 15.2.

[0086] In the embodiment of the present disclosure, InAlGaN is used as an etching barrier layer, the main etching rate of the p-GaN layer is 125.7 angstroms / min; the over-etching rate of the p-GaN layer is 14.9 angstroms / min, and the etching rate of the InAlGaN barrier layer is 0.62 angstroms / min; the selectivity of p-GaN / InAlGaN is greater than 20.

[0087] The over-etching process is performed after the main etching process is completed.

[0088] In the embodiment of the present disclosure, x is 0.1, y is 0.2, and z is 0.7, which can provide good lattice matching and high chemical stability. Under the same etching conditions, the etching rate is slower, has a high selectivity, and can effectively protect the barrier layer.

[0089] In the disclosed embodiment, the thickness of the etch stop layer may be 1 to 10 nm, which is not too thin to cause etching to the barrier layer during the etching process, nor too thick to cause the overall thickness of the transistor to be too thick.

[0090] Exemplarily, the thickness of the etch stop layer is 5 nm.

[0091] S14, forming a p-GaN layer on the etching stop layer.

[0092] In the embodiment of the present disclosure, the thickness of the p-GaN layer may be 75-150 nm.

[0093] Exemplarily, the p-GaN layer has a thickness of 100 nm.

[0094] S15, performing patterning on the p-GaN layer so that the p-GaN layer has a step structure extending to the etching stop layer.

[0095] In the embodiment of the present disclosure, an etch barrier layer is added between the barrier layer and the p-GaN layer of the epitaxial structure, so that the etching rate of the etch barrier layer is slow during the etching process, thereby improving the selectivity of the p-GaN layer to the etch barrier layer; at the same time, the barrier layer is prevented from being etched during the etching process of the p-GaN layer, thereby improving the stability of the transistor.

[0096] Figure 5 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure. Figure 5 The method steps include:

[0097] S21, forming a buffer layer, a channel layer, a barrier layer and an etching stop layer in sequence on the substrate.

[0098] Figure 6 is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure. Figure 6 , a buffer layer 105 , a channel layer 101 , a barrier layer 102 and an etch stop layer 103 are sequentially stacked on the substrate 100 .

[0099] In the embodiment of the present disclosure, the substrate may be any one of a sapphire substrate, a Si substrate, a SiC substrate, a GaN substrate, and the like. The embodiment of the present disclosure does not limit the material of the substrate 100 .

[0100] Exemplarily, the substrate is a Si substrate. In one example, step S21 includes:

[0101] The first step is to make a buffer layer.

[0102] In the embodiment of the present disclosure, the buffer layer may be a GaN buffer layer.

[0103] The second step is to make the channel layer.

[0104] In the embodiment of the present disclosure, the channel layer may be a GaN channel layer.

[0105] The third step is to make the barrier layer.

[0106] In the embodiment of the present disclosure, the barrier layer may be an AlGaN barrier layer, and the thickness may be 20-50 nm.

[0107] Exemplarily, the barrier layer thickness is 35 nm.

[0108] The fourth step is to make an etching stop layer.

[0109] In the embodiment of the present disclosure, the etching stop layer is In x Al y Ga z N layers, where x, y, and z are all greater than 0, In x Al y Ga z N acts as an etch barrier.

[0110] In the related art, the AlGaN barrier layer is directly used as an etching stop layer, the main etching rate of the p-GaN layer is 125.7 angstroms / min; the over-etching rate of the p-GaN layer is 14.9 angstroms / min, and the etching rate of the AlGaN barrier layer is 0.98 angstroms / min; the selectivity of p-GaN / AlGaN is 15.2.

[0111] In the embodiment of the present disclosure, InAlGaN is used as an etching barrier layer, the main etching rate of the p-GaN layer is 125.7 angstroms / min; the over-etching rate of the p-GaN layer is 14.9 angstroms / min, and the etching rate of the InAlGaN barrier layer is 0.62 angstroms / min; the selectivity of p-GaN / InAlGaN is greater than 20.

[0112] In the embodiment of the present disclosure, x is 0.1, y is 0.2, and z is 0.7, which can provide good lattice matching and high chemical stability. Under the same etching conditions, the etching rate is slower, has a high selectivity, and can effectively protect the barrier layer.

[0113] In the disclosed embodiment, the thickness of the etch stop layer may be 1 to 10 nm, which is not too thin to cause etching to the barrier layer during the etching process, nor too thick to cause the overall thickness of the transistor to be too thick.

[0114] Exemplarily, the thickness of the etch stop layer is 5 nm.

[0115] S22 . Manufacturing a p-GaN layer.

[0116] Figure 7 is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure. Figure 7 , the p-GaN layer 104 is on the etch stopper 103 layer.

[0117] In the embodiment of the present disclosure, the thickness of the p-GaN layer may be 75-150 nm.

[0118] Exemplarily, the p-GaN layer has a thickness of 100 nm.

[0119] S23. Growing a SiO2 dielectric layer on the p-GaN layer.

[0120] Figure 8 is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure. Figure 8 , the p-GaN layer 104 is on the etch stop layer 103 , and the dielectric layer 106 is on the p-GaN layer 104 .

[0121] In the embodiment of the present disclosure, the thickness of the SiO2 dielectric layer may be 190-210 nm.

[0122] Exemplarily, the SiO2 dielectric layer has a thickness of 200 nm.

[0123] S24, etching the SiO2 dielectric layer.

[0124] Fig. 9 is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure. Fig. 9 The dielectric layer 106 has a patterned covering portion of the p-GaN layer 104 .

[0125] The first step is to form a photoresist mask layer on the SiO2 dielectric layer.

[0126] The second step is to etch the SiO2 dielectric layer under the protection of the photoresist mask layer.

[0127] S25, etching the p-GaN layer under the protection of the etched SiO2 dielectric layer.

[0128] Fig.10is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure. Fig.10 The p-GaN layer 104 is provided with a step structure 201 extending to the etching stop layer 103 .

[0129] In the embodiment of the present disclosure, through step S25, the p-GaN layer is provided with a step structure extending to the etching stop layer.

[0130] In the embodiment of the present disclosure, the p-GaN layer is etched according to the following etching conditions:

[0131] Main etching procedure: etching pressure is 2-4Mt, etching power is 140-160W, bias power is 70-90W, Cl2 gas flow rate is 40-60sccm, Ar gas flow rate is 1-10sccm;

[0132] Over-etching procedure: etching pressure is 4~6Mt, etching power is 140~160W, bias power is 20~40W, BCl3 gas flow rate is 20~40sccm, N2 gas flow rate is 10-20sccm, and SF6 gas flow rate is 10~20sccm.

[0133] Exemplarily, the p-GaN layer is etched according to the following etching conditions:

[0134] Main etching program: etching pressure is 3Mt, etching power is 150W, bias power is 80W, Cl2 gas flow rate is 50sccm, Ar gas flow rate is 5sccm;

[0135] Over-etching procedure: etching pressure is 5Mt, etching power is 150W, bias power is 28W, BCl3 gas flow rate is 30sccm, N2 gas flow rate is 15sccm, and SF6 gas flow rate is 15sccm.

[0136] In the disclosed embodiments, Cl2 gas is often used to etch metals (Al, TiN, etc.) and GaN-based compounds (p-GaN, AlGaN, etc.); due to its high chemical activity, it can react with the material during the etching process to generate volatile chlorides, thereby achieving high-quality etching effects. The introduction of Ar gas can optimize the physical properties of the plasma and improve the etching process. As an inert gas, Ar gas can be used as a dilution gas to adjust the uniformity of etching; at the same time, it can also increase physical bombardment, open the chemical bonds of the reactants, accelerate chemical etching to a certain extent, and increase the etching rate. BCl3 gas can improve the selectivity and anisotropy of etching. BCl3 gas can provide ion bombardment during the etching process, which helps to remove the oxide layer on the surface of the material and promote the etching reaction. In addition, the introduction of BCl3 can consume Cl atoms (BCl x +Cl → BClx+1 ), reducing the etching of the sidewalls, thereby improving the etching profile and maintaining better pattern fidelity. The fluorine ions and free radicals produced by the decomposition of SF6 gas in a plasma state etch the dielectric faster; but SF6 etches Al-containing compounds more slowly, because F-based gases will produce AlF3 when etching Al-containing compounds, which has a high melting point and is extremely difficult to volatilize. Therefore, the introduction of SF6 can improve the selectivity of p-GaN to InAlGaN. N2 is an inert gas that can be used as a diluent gas and, in some cases, as a sidewall protection and passivation layer to improve the etching morphology.

[0137] S26, forming a first electrode and a second electrode on the etching stop layer and connecting them to the epitaxial structure through a step structure.

[0138] Fig.11 is a schematic diagram of a structure of a transistor manufacturing process provided by an embodiment of the present disclosure. Fig.11 The first electrode 107 and the second electrode 108 are connected to the channel layer 101 through the etching stop layer 103 and the barrier layer 102 respectively.

[0139] In one example, step S26 includes:

[0140] In the first step, a through hole is made, which penetrates the etching stop layer and the barrier layer.

[0141] The second step is to make the first electrode and the second electrode.

[0142] In other embodiments, the first electrode and the second electrode may also be connected to the barrier layer through the etching stop layer respectively.

[0143] In the embodiment of the present disclosure, the first electrode and the second electrode may include a first Ti sublayer, an Al sublayer, a second Ti sublayer, and a TiN sublayer (anti-oxidation sublayer) stacked in sequence.

[0144] In the embodiment of the present disclosure, the first Ti sub-layer, the Al sub-layer, the second Ti sub-layer and the TiN sub-layer may be formed by evaporation or sputtering process.

[0145] In the second step, the first electrode and the second electrode are annealed.

[0146] In the embodiment of the present disclosure, the annealing conditions may include: in a pure N2 atmosphere, the N2 flow rate may be 5 to 50 sccm, the temperature may be 450 to 600° C., and the time may be 30 to 180 s.

[0147] Exemplarily, the N2 flow rate is 25 sccm, the temperature is 500° C., and the time is 100 s.

[0148] S27. Make a control electrode on the dielectric layer.

[0149] In the embodiment of the present disclosure, the control electrode may include a first Ti sub-layer, an Al sub-layer, and a second Ti sub-layer stacked in sequence.

[0150] In the embodiment of the present disclosure, the first Ti sub-layer, the Al sub-layer and the second Ti sub-layer may be formed by an evaporation process or a sputtering process.

[0151] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A transistor, characterized in that: The transistor comprises: a channel layer (101), a barrier layer (102), an etching stop layer (103) and a p-GaN layer (104); The barrier layer (102), the etch stop layer (103) and the p-GaN layer (104) are sequentially stacked on the channel layer (101), and the p-GaN layer (104) is provided with a step structure extending to the etch stop layer (103).

2. The transistor according to claim 1, characterized in that The etching stop layer (103) is In x Al y Ga z N layers, where x, y, and z are all greater than 0.

3. The transistor according to claim 2, characterized in that The x is 0.1, the y is 0.2, and the z is 0.

7.

4. The transistor according to claim 1, characterized in that The thickness of the etching stop layer (103) is 1-10 nm.

5. A method for preparing a transistor, characterized in that: The transistor preparation method comprises: manufacturing a channel layer; forming a barrier layer on the channel layer; forming an etching stop layer on the barrier layer; Fabricating a p-GaN layer on the etch stop layer; The p-GaN layer is patterned so that the p-GaN layer has a step structure extending to the etching stop layer.

6. The transistor manufacturing method according to claim 5, characterized in that: The patterning of the p-GaN layer comprises: Growing a SiO2 dielectric layer on the p-GaN layer; forming a photoresist mask layer on the SiO2 dielectric layer; Under the protection of the photoresist mask layer, etching the SiO2 dielectric layer; The p-GaN layer is etched under the shielding of the etched SiO2 dielectric layer.

7. The transistor manufacturing method according to claim 6, characterized in that: The step of etching the p-GaN layer under the shielding of the etched SiO2 dielectric layer comprises: Setting etching conditions for the main etching process and the over-etching process; Under the etching conditions of the main etching procedure and the over-etching procedure, the p-GaN layer is etched while being shielded by the etched SiO2 dielectric layer.

8. The transistor manufacturing method according to claim 7, characterized in that: The etching conditions of the main etching procedure are as follows: etching pressure is 2-4 Mt, etching power is 140-160 W, bias power is 70-90 W, Cl2 gas flow rate is 40-60 sccm, and Ar gas flow rate is 1-10 sccm; The etching conditions of the over-etching procedure are as follows: etching pressure is 4-6Mt, etching power is 140-160W, bias power is 20-40W, BCl3 gas flow rate is 20-40sccm, N2 gas flow rate is 10-20sccm, and SF6 gas flow rate is 10-20sccm.

9. The transistor manufacturing method according to any one of claims 6 to 8, characterized in that: The etching stop layer is In x Al y Ga z N layers, where x, y, and z are all greater than 0.

10. The transistor manufacturing method according to claim 9, characterized in that: The x is 0.1, the y is 0.2, and the z is 0.7.

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