Semiconductor power device with wide safe working area and preparation method thereof

Abstract

The invention provides a semiconductor power device with a wide safe operation area and a preparation method thereof, and the device comprises a first groove and a second groove which are respectively formed in different areas of an epitaxial layer; a source polysilicon layer is formed at the bottom of the trench, a third isolation layer, a second isolation layer and a first isolation layer are sequentially formed on the outer side of the source polysilicon layer, an isolation oxide layer and a gate polysilicon layer are sequentially formed on the source polysilicon layer, and a gate oxide layer is formed on the outer side of the gate polysilicon layer; the thickness of the first isolation oxide layer is greater than that of the second isolation oxide layer, and the thickness of the first gate oxide layer is greater than that of the second gate oxide layer. The method has the beneficial effects that the isolation oxide layers with different thicknesses are formed in the device active region division regions, so that the gate-drain capacitance is reduced, and the device switching frequency is improved; meanwhile, the gate oxide layer adopts a single layer to realize different thicknesses in different areas, so that the threshold voltages of the cells in different areas are different, and the safe working area of the power device is widened; and a good compromise between the forward conduction capability and the reverse recovery capability is realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor power device with a wide safe operating area and a preparation method thereof. Background Art

[0002] Power Metal-Oxide-Semiconductor or Field-effect Transistor (MOSFET) is one of the commonly used power devices for switching devices. Power MOSFET devices have advantages such as high switching frequency. Under normal working conditions, due to the impedance inside the device, the power MOSFET device itself will generate a lot of power consumption during the switching process. With the increase of operating frequency, the proportion of switching loss of power MOSFET devices in the overall loss is also increasing. Moreover, with the continuous miniaturization of semiconductor process technology, the cell density continues to increase, and the increase of switching frequency can easily cause overcurrent or overvoltage in the device circuit, resulting in a sharp increase in the junction temperature of the chip, and ultimately causing device failure.

[0003] Safe Operating Area (SOA) refers to a voltage-current range that enables power devices to operate safely. Within this voltage-current range, the device can operate stably within the maximum junction temperature limit, thereby avoiding the risk of thermal failure.

[0004] At present, the industry has proposed some solutions to enhance the heat dissipation capacity of the device and improve the thermal stability of the device. For example, Chinese patent CN118315425A discloses a semiconductor power device with a wide safe operating area and a manufacturing method thereof. The first gate oxide layer in the first trench of the device includes a first nitride layer and a first oxide layer, and the second gate oxide layer in the second trench includes a first oxide layer. Therefore, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer. After P+ and N+ injection, the regional threshold voltage of the thicker first gate oxide layer is higher, and the regional threshold voltage of the thinner second gate oxide layer is lower. This achieves different gate oxide layer thicknesses in different regions of the same device, resulting in different cell threshold voltages in different regions, successfully reducing the zero temperature coefficient point of the device, improving the thermal failure of MOS, and enabling the MOS device to have a wider safe operating area (SOA).

[0005] However, the device has a large gate-drain capacitance, which results in prolonged charge accumulation and discharge time during the switching process, thereby limiting the switching frequency of the device; moreover, the gate oxide layer adopts a multi-layer combination structure to achieve different thicknesses in different regions, which limits the threshold voltage regulation; in addition, existing devices often find it difficult to achieve an ideal balance between forward conduction capability and reverse recovery capability, affecting the overall performance of the device. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a semiconductor power device with a wide safe operating area; on the other hand, it also provides a method for preparing a semiconductor power device with a wide safe operating area.

[0007] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0008] A first aspect of the present invention is to provide a semiconductor power device with a wide safe operating area, comprising:

[0009] An epitaxial layer is formed on a substrate, wherein the epitaxial layer includes a first region and second regions located on both sides of the first region;

[0010] a first trench formed in the first region;

[0011] a second trench formed in the second region;

[0012] A source polysilicon layer is formed at the bottom of the first trench and the second trench respectively, and a third isolation layer, a second isolation layer and a first isolation layer are sequentially formed on the outer side of the source polysilicon layer;

[0013] A first isolation oxide layer is formed on the upper end of the source polysilicon layer at the bottom of the first trench, a first gate polysilicon layer is formed on the upper end of the first isolation oxide layer, and a first gate oxide layer is formed on the outer side of the first gate polysilicon layer;

[0014] A second isolation oxide layer is formed on the upper end of the source polysilicon layer at the bottom of the second trench, a second gate polysilicon layer is formed on the upper end of the second isolation oxide layer, and a second gate oxide layer is formed on the outer side of the second gate polysilicon layer;

[0015] The thickness of the first isolation oxide layer is greater than the thickness of the second isolation oxide layer, and the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0016] Preferably, it also includes:

[0017] A first body region formed in a region of the first region excluding the first trench;

[0018] A second body region formed in the second region except for the second trench;

[0019] A source region is formed in the first body region and the second body region.

[0020] Preferably, the doping concentration of the first body region is greater than the doping concentration of the second body region.

[0021] Preferably, the first isolation layer is a silicon oxide layer, the second isolation layer is a silicon nitride layer, and the third isolation layer is a silicon oxide layer.

[0022] Preferably, the thickness of the first isolation layer is greater than the thickness of the second isolation layer;

[0023] The thickness of the first isolation layer is greater than the thickness of the third isolation layer.

[0024] A second aspect of the present invention is to provide a method for preparing a semiconductor power device with a wide safe operating area, comprising:

[0025] Step S1, growing an epitaxial layer on a substrate, wherein the epitaxial layer includes a first region and second regions located on both sides of the first region;

[0026] Step S2, growing a barrier layer on the epitaxial layer, and etching the barrier layer and the epitaxial layer to form a first trench located in the first region and a second trench located in the second region;

[0027] Step S3, forming a first isolation layer, a second isolation layer and a third isolation layer in sequence on the surface of the epitaxial layer and the inner walls of the first trench and the second trench;

[0028] Step S4, forming a source polysilicon layer in the first trench and the second trench;

[0029] Step S5, forming a first isolation oxide layer on the upper end of the source polysilicon layer of the first trench, and forming a second isolation oxide layer on the upper end of the source polysilicon layer of the second trench;

[0030] Step S6, etching the third isolation layer and the second isolation layer until they are flush with the first isolation oxide layer and the second isolation oxide layer;

[0031] Step S7, forming a first mask layer in the first region;

[0032] Step S8, etching part of the first isolation layer and the first isolation oxide layer in the second region, the first isolation layer retained at the upper end of the second trench is used as the second gate oxide layer, and the first isolation layer at the upper end of the first trench is used as the first gate oxide layer, and after etching, the thickness of the first isolation oxide layer is less than the thickness of the second isolation oxide layer, and the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer;

[0033] Step S9, removing the first mask layer, and forming a first gate polysilicon layer in the first trench, and forming a second gate polysilicon layer in the second trench.

[0034] Preferably, after step S9, the step further includes:

[0035] Step S10, forming a second mask layer in the second region;

[0036] Step S11, performing a first ion implantation in the first region except the first trench to form a body region;

[0037] Step S12, removing the second mask layer, and performing a second ion implantation in the epitaxial layer to form a first body region and a second body region;

[0038] Step S13, forming a source region in the first body region and the second body region.

[0039] Preferably, the doping concentration of the first body region is greater than the doping concentration of the second body region.

[0040] Preferably, the first isolation layer is a silicon oxide layer, the second isolation layer is a silicon nitride layer, and the third isolation layer is a silicon oxide layer.

[0041] Preferably, the thickness of the first isolation layer is greater than the thickness of the second isolation layer;

[0042] The thickness of the first isolation layer is greater than the thickness of the third isolation layer.

[0043] The advantages or beneficial effects of the technical solution of the present invention are:

[0044] The present invention forms isolation oxide layers of different thicknesses in the device active area to reduce gate-drain capacitance and improve the switching frequency of the device; at the same time, the gate oxide layer adopts a single layer to achieve different thicknesses in different areas, so that the threshold voltage of the cell in different areas is different, the device threshold voltage temperature coefficient is reduced, thereby reducing the current zero temperature coefficient point, improving the device heating uniformity, and widening the safe operating area SOA of the power device; in addition, a good compromise between the forward conduction capability and the reverse recovery capability of the device can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A cross-sectional schematic diagram of a semiconductor power device with a wide safe operating area in a preferred embodiment of the present invention;

[0046] Figure 2 A schematic diagram of a preparation method in a preferred embodiment of the present invention;

[0047] Figure 3-15 It is a cross-sectional schematic diagram of each step of the preparation method in a preferred embodiment of the present invention.

[0048] Description of reference numerals:

[0049] 1. Substrate; 2. Epitaxial layer; 3. Barrier layer; 41. First trench; 42. Second trench; 51. First isolation layer; 52. Second isolation layer; 53. Third isolation layer; 6. Source polysilicon layer; 71. First isolation oxide layer; 72. Second isolation oxide layer; 81. First mask layer; 82. Second mask layer; 91. First gate polysilicon layer; 92. Second gate polysilicon layer; 101. First gate oxide layer; 102. Second gate oxide layer; 11. Body region; 12. First body region; 13. Second body region; 14. Source region. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0052] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0053] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a semiconductor power device with a wide safe operating area is provided. Figure 1 As shown, including:

[0054] An epitaxial layer 2 is formed on the substrate 1, and the epitaxial layer 2 includes a first region and second regions located on both sides of the first region;

[0055] A first trench 41 formed in the first region;

[0056] A second groove 42 is formed in the second region; wherein the second groove 42 is located on both sides of the first groove 41;

[0057] A source polysilicon layer 6 is formed at the bottom of the first trench 41 and the second trench 42, respectively. A third isolation layer 53, a second isolation layer 52 and a first isolation layer 51 are sequentially formed on the outer side of the source polysilicon layer 6;

[0058] A first isolation oxide layer 71 is formed on the upper end of the source polysilicon layer 6 at the bottom of the first trench 41, a first gate polysilicon layer 91 is formed on the upper end of the first isolation oxide layer 71, and a first gate oxide layer 101 is formed on the outer side of the first gate polysilicon layer 91 and on the surface of the epitaxial layer 2 in the first region;

[0059] A second isolation oxide layer 72 is formed on the upper end of the source polysilicon layer 6 at the bottom of the second trench 42, a second gate polysilicon layer 92 is formed on the upper end of the second isolation oxide layer 72, and a second gate oxide layer 102 is formed on the outer side of the second gate polysilicon layer 92 and on the surface of the epitaxial layer 2 in the second region;

[0060] The thickness of the first isolation oxide layer 71 is greater than the thickness of the second isolation oxide layer 72 , and the thickness of the first gate oxide layer 101 is greater than the thickness of the second gate oxide layer 102 .

[0061] Specifically, in this embodiment, different regions are divided in the active region of the device, such as the middle region a is set as the first region, and the regions b on both sides are set as the second region.

[0062] The thickness of the isolation oxide layer formed in different regions (i.e., the length in the lateral direction parallel to the device) is different. For example, the thickness of the first isolation oxide layer 71 in the first region is x, and the thickness of the second isolation oxide layer 72 in the second region is y, i.e., y>x. The thickness of the first isolation oxide layer 71 in the first region is relatively thick, and the thickness of the second isolation oxide layer 72 in the second region is relatively thin, which reduces the gate-drain capacitance of the device and improves the switching frequency of the device.

[0063] At the same time, the thickness of the gate oxide layer formed in different regions (i.e., the length in the longitudinal direction perpendicular to the device) is also different. For example, the thickness of the first gate oxide layer 101 in the first region is m, and the thickness of the second gate oxide layer 102 in the second region is n, that is, m>n. The thickness of the first gate oxide layer 101 in the first region is thicker, and the thickness of the second gate oxide layer 102 in the second region is thinner. Moreover, the first gate oxide layer 101 in the first groove 41 includes a first isolation layer 51, and the second gate oxide layer 102 in the second groove 42 includes a first isolation layer 51, and the first isolation layer 51 is a silicon oxide layer, that is, the gate oxide layer adopts a single-layer isolation layer (the first isolation layer of the second region is etched) to achieve different thicknesses in different regions, so that the threshold voltage of the cell in different regions is different, and the device threshold voltage temperature coefficient is reduced, thereby reducing the current zero temperature coefficient point (Zero Temperature Coefficient Point, ZTCP), so that when the device is turned on, some regions are turned on first, while other regions are turned on with delay or even not turned on. When one region is turned on, the work can be completed, and the other non-turned-on region can be used as a heat dissipation field plate, thereby improving the uniformity of device heating and widening the safe operating area SOA of the power device.

[0064] In addition, a good compromise between the forward conduction capability and the reverse recovery capability of the device is achieved.

[0065] As a preferred embodiment, the invention further comprises:

[0066] A first body region 12 is formed in the first region except the first trench 41;

[0067] A second body region 13 formed in the second region except the second trench 42;

[0068] The source region 14 is formed in the first body region 12 and the second body region 13 .

[0069] In this embodiment, the first body region is a BODY-high open region, and the second body region is a BODY-low open region.

[0070] As a preferred embodiment, the doping concentration of the first body region 12 is greater than the doping concentration of the second body region 13 .

[0071] Specifically, in the present embodiment, by forming gate oxide layers of different thicknesses and P-body regions of different concentrations, wherein the thickness of the first gate oxide layer 101 in the first region is relatively thick, and the concentration of the first body region 12 is relatively high, and the thickness of the second gate oxide layer 102 in the second region is relatively thin, and the concentration of the second body region 13 is relatively low, the threshold voltage of the BODY-high opening region is higher, and the threshold voltage of the BODY-low opening region is low, so that the threshold voltages of the cell in different regions are different, the current zero temperature coefficient point of the device is reduced, the heating uniformity of the device is improved, and the range of the safe operating area SOA of the power device is widened.

[0072] In this embodiment, the same junction depth can be used to realize P-body regions with different concentrations in different regions, that is, the junction depth of the first body region 12 can be the same as the junction depth of the second body region 13. Specifically, the concentration of the P-body region can be adjusted by increasing or decreasing the dose of doped ions while keeping the depth of ion implantation consistent, thereby achieving the purpose of forming P-body regions with different concentrations but the same junction depth in the first body region 12 and the second body region 13, and flexibly adjusting the electrical properties of different parts of the device without changing the overall structural complexity of the device.

[0073] In this embodiment, different junction depths can also be used to achieve different concentrations of P-body in different regions, that is, the first body region 12 with a higher doping concentration has a deeper junction depth, while the second body region 13 with a lower doping concentration has a shallower junction depth. Specifically, when forming the first body region 12, a higher energy is used for ion implantation, so that the doped ions can penetrate into a deeper level and form a deeper junction depth; when forming the second body region 13, the implantation energy is reduced so that the doped ions only stay at a shallower level and form a shallower junction depth.

[0074] As a preferred embodiment, the first isolation layer 51 is a silicon oxide layer, the second isolation layer 52 is a silicon nitride layer, and the third isolation layer 53 is a silicon oxide layer.

[0075] Specifically, the first isolation layer 51 , the second isolation layer 52 and the third isolation layer 53 are sequentially arranged from the inside to the outside to form an oxide-nitride-oxide (ONO) structure.

[0076] In this embodiment, the first isolation layer 51 is formed by thermal oxidation, and the second isolation layer 52 and the third isolation layer 53 are formed by deposition, respectively.

[0077] As a preferred embodiment, the thickness of the first isolation layer 51 is relatively thick, that is, the thickness of the first isolation layer 51 is greater than the thickness of the second isolation layer 52;

[0078] The thickness of the first isolation layer 51 is greater than the thickness of the third isolation layer 53 .

[0079] The present invention also provides a method for preparing a semiconductor power device with a wide safe operating area, such as Figure 2 As shown, including:

[0080] Step S1, such as Figure 3 As shown, an epitaxial layer 2 is grown on a substrate 1, and the epitaxial layer 2 includes a first region and second regions located on both sides of the first region;

[0081] Step S2, growing a barrier layer 3 on the epitaxial layer 2, such as Figure 4 As shown, the barrier layer 3 and the epitaxial layer 2 are etched to form a first trench 41 located in the first area and a second trench 42 located in the second area;

[0082] Specifically, first, a substrate 1 is provided, an epitaxial layer 2 is disposed on the substrate 1, and a silicon dioxide hard mask layer is deposited on the epitaxial layer 2 as a barrier layer 3 for trench etching;

[0083] By photolithography (resin coating, exposure, development, etc.) on the barrier layer 3, the oxide layer mask area at the corresponding groove position to be etched is determined, and etching is performed on the epitaxial layer 2 and the barrier layer 3 to form a first groove 41 and second grooves 42 located on both sides of the first groove 41;

[0084] Step S3, such as Figure 5 As shown, a first isolation layer 51, a second isolation layer 52 and a third isolation layer 53 are sequentially formed on the surface of the epitaxial layer 2, the inner walls of the first trench 41 and the second trench 42;

[0085] Specifically, a first isolation layer 51, a second isolation layer 52 and a third isolation layer 53 are sequentially formed inside the trench 4. The first isolation layer 51, the second isolation layer 52 and the third isolation layer 53 are sequentially arranged from the inside to the outside to form an oxide-nitride-oxide (ONO) structure.

[0086] In particular, the first isolation layer 51 is relatively thick, that is, the thickness of the first isolation layer 51 is greater than the thickness of the second isolation layer 52 and the thickness of the third isolation layer 53 .

[0087] Step S4, such as Figure 6 As shown, a source polysilicon layer 6 is formed in the first trench 41 and the second trench 42;

[0088] Specifically, heavily doped polysilicon is deposited inside the trench, and the polysilicon is etched back by chemical mechanical polishing and dry etching to form a source polysilicon layer 6 .

[0089] Step S5, such as Figure 7 As shown, a first isolation oxide layer 71 is formed on the upper end of the source polysilicon layer 6 of the first trench 41, and a second isolation oxide layer 72 is formed on the upper end of the source polysilicon layer 6 of the second trench 42;

[0090] Specifically, a thicker isolation oxide layer is formed on the source polysilicon layer 6 by thermal oxidation, wherein the isolation oxide layer in the first region is set as the first isolation oxide layer 71 , and the isolation oxide layer in the second region is set as the first isolation oxide layer 71 .

[0091] The material of the isolation oxide layer is the same as that of the first isolation layer 53 .

[0092] Step S6, as Figure 8 and Fig. 9 As shown, the third isolation layer 53 and the second isolation layer 52 are etched until they are flush with the first isolation oxide layer 71 and the second isolation oxide layer 72;

[0093] Specifically, the third isolation layer 53 is etched by a wet etching process until the third isolation layer 53 is flush with the isolation oxide layer.

[0094] Subsequently, the second isolation layer 52 is continuously etched by a wet etching process until the second isolation layer 52 is flush with the isolation oxide layer.

[0095] During the etching process of the second isolation layer 52 and the third isolation layer 53 , a portion of the first isolation oxide layer 71 and the second isolation oxide layer 72 are also removed by etching.

[0096] Step S7, Fig.10 As shown, a first mask layer 81 is formed in the first region;

[0097] Specifically, a thicker first mask layer 81 is firstly provided in the first region, wherein the first mask layer 81 completely covers the first region and does not cover the second region, that is, the region filled by the first mask layer 81 includes the first trench 41 located in region a and the upper surface of the first isolation layer 51 .

[0098] Step S8, Fig.11As shown, part of the first isolation layer 51 and the first isolation oxide layer 71 in the second region are etched, the first isolation layer 51 retained at the upper end of the second trench 42 is used as the second gate oxide layer 102, and the first isolation layer 51 at the upper end of the first trench 41 is used as the first gate oxide layer 101. After etching, the thickness of the first isolation oxide layer 71 is less than the thickness of the second isolation oxide layer 72, and the thickness of the first gate oxide layer 101 is greater than the thickness of the second gate oxide layer 102;

[0099] Specifically, the first isolation layer 51 in the second region is wet-etched with the first mask layer 81 as a shield. Due to the protection of the first mask layer 81, only part of the isolation oxide layer 51 in the first region is etched, so that the thickness of the first gate oxide layer 101 in the first region is greater than the thickness of the second gate oxide layer in the second region.

[0100] Similarly, since the first region is protected by the first mask layer 81 , the first isolation oxide layer 71 and the first isolation layer 51 are made of the same material, and the second isolation oxide layer 72 in the second region is partially etched, thereby forming a thickness difference between the first gate oxide layer 101 and the second gate oxide layer 102 .

[0101] Therefore, the same etching process is used to simultaneously realize the formation of thickness differences in different regions of the gate oxide layer and the isolation oxide layer.

[0102] Step S9, as Fig.12 As shown, the first mask layer 81 is removed, and a first gate polysilicon layer 91 is formed in the first trench 41 , and a second gate polysilicon layer 92 is formed in the second trench 42 .

[0103] Specifically, the first mask layer 81 is removed, a heavily doped polysilicon layer is deposited, and the polysilicon is etched by chemical mechanical polishing and dry etching until it is flush with the surface of the gate oxide layer to form a gate polysilicon layer. The gate polysilicon layer in the first region is set as a first gate polysilicon layer 91, and the gate polysilicon layer in the second region is set as a second gate polysilicon layer 92.

[0104] In this embodiment, the first gate polysilicon layer 91 is flush with the surface of the first gate oxide layer 101 in the first region.

[0105] In this embodiment, the second gate polysilicon layer 92 is flush with the surface of the second gate oxide layer 102 in the second region.

[0106] As a preferred implementation, the method further includes after step S9:

[0107] Step S10, as Fig.13 As shown, a second mask layer 82 is formed in the second region;

[0108] Specifically, a thicker second mask layer 82 is first disposed in the second region, wherein the second mask layer 82 completely covers the second region and does not cover the first region, that is, the region filled by the second mask layer 82 includes the second trench 41 located in the second region and the upper surface of the first isolation layer 51 .

[0109] Step S11, performing a first ion implantation in the first region except the first trench 41 to form a body region 11;

[0110] Specifically, P-type doping elements are ion-implanted into the surface of the epitaxial layer 1, and then the body imp is pushed to a required junction depth by thermally pushing the well, which must be located above the bottom of the gate polysilicon to form a P-body region.

[0111] Since the second region surface is protected by the second mask layer 82, no P-body region is formed in the second region;

[0112] Step S12, as Fig.14 As shown, the second mask layer 82 is removed, and a second ion implantation is performed in the epitaxial layer 2 to form a first body region 12 and a second body region 13;

[0113] Specifically, the second mask layer 82 is removed, and P-type doping elements are implanted on the surface of the epitaxial layer 1 by ion implantation, and then the body imp is pushed to the required junction depth by thermally pushing the well.

[0114] The body region of the first region is subjected to two ion implantations, so the formed first body region 12 has a higher concentration, while the second region is subjected to only one ion implantation, so the formed second body region 13 has a lower concentration.

[0115] Step S13, as Fig.15 As shown, a source region 14 is formed in the first body region 12 and the second body region 13 .

[0116] Specifically, N-type heavily doped elements are ion-implanted, and then the SN imp is pushed to a required junction depth by thermally pushing the well to form an N+ heavily doped source region 14 .

[0117] As a preferred embodiment, the doping concentration of the first body region 12 is greater than the doping concentration of the second body region 13 .

[0118] As a preferred embodiment, the first isolation layer 51 is a silicon oxide layer, the second isolation layer 52 is a silicon nitride layer, and the third isolation layer 53 is a silicon oxide layer.

[0119] In this embodiment, the first isolation layer 51 is formed by thermal oxidation, and the second isolation layer 52 and the third isolation layer 53 are formed by deposition, respectively.

[0120] As a preferred embodiment, the thickness of the first isolation layer 51 is greater than the thickness of the second isolation layer 52;

[0121] The thickness of the first isolation layer 51 is greater than the thickness of the third isolation layer 53 .

[0122] Furthermore, the first mask layer 81 is photoresist.

[0123] Furthermore, the second mask layer 82 is photoresist.

[0124] like Fig.15 As shown, by forming gate oxide layers and isolation oxide layers of different thicknesses and P-body regions of different concentrations in different regions. Specifically, in the first region, the first isolation oxide layer 71 is thicker, the first gate oxide layer 101 is thicker, and the first body region 12 is a BODY-high open region with a high concentration (high threshold voltage); while in the second region, the second isolation oxide layer 72 is thinner, the second gate oxide layer 102 is thinner, and the second body region 13 is a BODY-low open region with a low concentration (low threshold voltage).

[0125] The advantages or beneficial effects of adopting the above technical solution are: the present invention divides the region into gate oxide layers of different thicknesses and P-body regions of different concentrations by using photoresist to separate and displace in the middle of the active region of the device, the a region with high thickness and high concentration and the b region with low thickness and low concentration, respectively forming a BODY-high opening region (high threshold voltage) and a BODY-low opening region (low threshold voltage), so that the threshold voltage of the cell in different regions is different, the device threshold voltage temperature coefficient is reduced, thereby reducing the current zero temperature coefficient point, and realizing that when the device is turned on, some regions are turned on first while other regions are turned on with delay or even not turned on, some regions can complete the work by turning on, and the other regions that are not turned on can be used as heat dissipation field plates, thereby improving the heating uniformity of the device and widening the safe operating area SOA of the power device.

[0126] In addition, isolation oxide layers of different thicknesses are formed, a region with high thickness a and a region with low thickness b, to reduce gate-drain capacitance and increase the switching frequency of the device, thereby achieving a good compromise between the forward conduction capability and reverse recovery capability of the device.

[0127] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A semiconductor power device with a wide safe operating area, characterized in that: include: An epitaxial layer is formed on a substrate, wherein the epitaxial layer includes a first region and second regions located on both sides of the first region; a first trench formed in the first region; a second trench formed in the second region; A source polysilicon layer is formed at the bottom of the first trench and the second trench respectively, and a third isolation layer, a second isolation layer and a first isolation layer are sequentially formed on the outer side of the source polysilicon layer; A first isolation oxide layer is formed on the upper end of the source polysilicon layer at the bottom of the first trench, a first gate polysilicon layer is formed on the upper end of the first isolation oxide layer, and a first gate oxide layer is formed on the outer side of the first gate polysilicon layer; A second isolation oxide layer is formed on the upper end of the source polysilicon layer at the bottom of the second trench, a second gate polysilicon layer is formed on the upper end of the second isolation oxide layer, and a second gate oxide layer is formed on the outer side of the second gate polysilicon layer; The thickness of the first isolation oxide layer is greater than the thickness of the second isolation oxide layer, and the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

2. The semiconductor power device with a wide safe operating area according to claim 1, characterized in that: Also includes: A first body region formed in a region of the first region excluding the first trench; A second body region formed in the second region except for the second trench; A source region is formed in the first body region and the second body region.

3. The semiconductor power device with a wide safe operating area according to claim 2, characterized in that: The doping concentration of the first body region is greater than the doping concentration of the second body region.

4. The semiconductor power device with a wide safe operating area according to claim 1, characterized in that: The first isolation layer is a silicon oxide layer, the second isolation layer is a silicon nitride layer, and the third isolation layer is a silicon oxide layer.

5. The semiconductor power device with a wide safe operating area according to claim 1, characterized in that: The thickness of the first isolation layer is greater than the thickness of the second isolation layer; The thickness of the first isolation layer is greater than the thickness of the third isolation layer.

6. A method for preparing a semiconductor power device with a wide safe operating area, characterized in that: include: Step S1, growing an epitaxial layer on a substrate, wherein the epitaxial layer includes a first region and second regions located on both sides of the first region; Step S2, growing a barrier layer on the epitaxial layer, and etching the barrier layer and the epitaxial layer to form a first trench located in the first region and a second trench located in the second region; Step S3, forming a first isolation layer, a second isolation layer and a third isolation layer in sequence on the surface of the epitaxial layer, the inner walls of the first trench and the second trench; Step S4, forming a source polysilicon layer in the first trench and the second trench; Step S5, forming a first isolation oxide layer on the upper end of the source polysilicon layer of the first trench, and forming a second isolation oxide layer on the upper end of the source polysilicon layer of the second trench; Step S6, etching the third isolation layer and the second isolation layer until they are flush with the first isolation oxide layer and the second isolation oxide layer; Step S7, forming a first mask layer in the first region; Step S8, etching part of the first isolation layer and the first isolation oxide layer in the second region, the first isolation layer retained at the upper end of the second trench is used as the second gate oxide layer, and the first isolation layer at the upper end of the first trench is used as the first gate oxide layer, and after etching, the thickness of the first isolation oxide layer is less than the thickness of the second isolation oxide layer, and the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer; Step S9, removing the first mask layer, and forming a first gate polysilicon layer in the first trench, and forming a second gate polysilicon layer in the second trench.

7. The preparation method according to claim 6, characterized in that: After step S9, the following steps are also included: Step S10, forming a second mask layer in the second region; Step S11, performing a first ion implantation in the first region except the first trench to form a body region; Step S12, removing the second mask layer, and performing a second ion implantation in the epitaxial layer to form a first body region and a second body region; Step S13, forming a source region in the first body region and the second body region.

8. The preparation method according to claim 7, characterized in that: The doping concentration of the first body region is greater than the doping concentration of the second body region.

9. The preparation method according to claim 6, characterized in that: The first isolation layer is a silicon oxide layer, the second isolation layer is a silicon nitride layer, and the third isolation layer is a silicon oxide layer.

10. The preparation method according to claim 6, characterized in that: The thickness of the first isolation layer is greater than the thickness of the second isolation layer; The thickness of the first isolation layer is greater than the thickness of the third isolation layer.

Images