Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the drift region of the first doping type is located in the substrate; the field dielectric layer structure comprises a second dielectric layer and a first dielectric layer; the second dielectric layer is located on one side surface of the drift region away from the substrate; the first dielectric layer comprises a plurality of first dielectric parts, and the plurality of first dielectric parts are inserted into the second dielectric layer along the first direction; wherein the first direction is perpendicular to the direction, pointing to the field dielectric layer structure, of the substrate; the plurality of top regions of the second doping type are arranged in the drift region at intervals along the first direction, and the top regions are arranged corresponding to the first medium parts; the first doping type is opposite to the second doping type. The first dielectric part is inserted into the second dielectric layer, the electric field intensity at the sharp corner of the second dielectric layer can be reduced, and the surface electric field is reduced. The top region and the drift region form a multiple RESURF structure, so that the electric field distribution on the surface of the device can be improved, the injection of carriers in the drift region is promoted, and the on-resistance is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the development of semiconductor technology, semiconductor devices are moving towards low on-resistance and high breakdown voltage. For laterally diffused metal oxide semiconductor (LDMOS), RESURF (reduced surface field) technology is currently used to increase the breakdown voltage, but the on-resistance and breakdown voltage of LDMOS tubes still cannot meet the demand. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor structure with high withstand voltage and low on-resistance and a preparation method thereof.

[0004] In a first aspect, the present application provides a semiconductor structure, comprising:

[0005] substrate;

[0006] A drift region of a first doping type, located in the substrate;

[0007] A field dielectric layer structure, comprising a first dielectric layer and a second dielectric layer; the second dielectric layer is located on a surface of the drift region away from the substrate; the first dielectric layer comprises a plurality of first dielectric portions, the plurality of first dielectric portions are inserted into the second dielectric layer along a first direction; wherein the first direction is perpendicular to a direction from the substrate to the field dielectric layer structure;

[0008] A plurality of second doping type top regions are arranged in the drift region at intervals along a first direction, and the top regions are arranged corresponding to the first dielectric portion; the first doping type is opposite to the second doping type.

[0009] In one embodiment, the second dielectric layer includes a plurality of second dielectric portions, and the first dielectric portions and the second dielectric portions are alternately arranged along a first direction.

[0010] In one of the embodiments, the ion doping concentration of the top region is greater than the ion doping concentration of the drift region.

[0011] In one embodiment, the semiconductor structure further comprises:

[0012] A body region is located in the substrate, and the body region and the drift region are arranged along a second direction, the second direction is the same as the first direction, or the second direction is perpendicular to the first direction and perpendicular to the direction of the substrate pointing to the field dielectric layer structure.

[0013] In one embodiment, the semiconductor structure further comprises:

[0014] A source electrode located in the body region;

[0015] A drain electrode is located in the drift region and on a side of the field dielectric layer structure away from the body region;

[0016] The gate is located on a surface of the substrate close to the drift region and covers a portion of the body region and at least a portion of the second dielectric layer.

[0017] In one embodiment, the gate further covers at least a portion of the first dielectric portion.

[0018] In one embodiment, the first dielectric layer includes silicon nitride.

[0019] In a second aspect, the present application also provides a method for preparing a semiconductor structure, comprising:

[0020] providing a substrate;

[0021] forming a drift region of a first doping type in the substrate;

[0022] forming a second dielectric layer on a surface of the drift region away from the substrate;

[0023] A plurality of grooves are formed in the second dielectric layer and are arranged at intervals along a first direction; the first direction is perpendicular to the direction of the substrate pointing to the second dielectric layer;

[0024] The second dielectric layer is used as an injection blocking layer, and a plurality of top regions of a second doping type are formed in the drift region based on the trench; the first doping type is opposite to the second doping type;

[0025] A first dielectric portion is formed in the groove; wherein a plurality of the first dielectric portions constitute a first dielectric layer, and the first dielectric layer and the second dielectric layer constitute a field dielectric layer structure.

[0026] In one embodiment, forming the first dielectric portion in the groove includes:

[0027] forming a first dielectric material layer in the plurality of trenches and on a surface of the second dielectric layer away from the drift region;

[0028] The first dielectric material layer on a surface of the second dielectric layer away from the drift region is removed to form a first dielectric portion, wherein the thickness of the first dielectric portion is smaller than the thickness of the second dielectric layer.

[0029] In one embodiment, the forming of the first dielectric portion in the groove further includes:

[0030] The second dielectric layer is planarized to make the second dielectric layer flush with the surface of the first dielectric layer.

[0031] In the above semiconductor structure and preparation method thereof, the semiconductor structure includes a substrate, a drift region of a first doping type, a field dielectric layer structure and a plurality of top regions of a second doping type. The drift region is located in the substrate, the field dielectric layer structure is located on a side surface of the drift region away from the substrate, and the top region is arranged in the drift region at intervals along the first direction. The plurality of top regions of the second doping type and the drift region of the first doping type form a multiple RESURF structure, and a plurality of PN junctions are formed at the top of the drift region. The electric field distribution at the top of the drift region is improved by the longitudinal depletion of the plurality of PN junctions, the depletion capacity of the drift region is improved, and the electric field strength on the surface of the device is reduced. In addition, by increasing the doping concentration of the drift region, it is ensured that when the ions in the top region are inverted during the operation of the device, the net doping concentration of the drift region can be maintained within a preset range (the preset range includes the expected value of the net doping concentration and the allowable error range), and the increase in the doping concentration of the drift region can also reduce the on-resistance of the device. By the mutual cooperation of the technical features such as the top region and the drift region forming a multiple RESURF structure and the increase in the doping concentration of the drift region, the on-resistance of the device is reduced while reducing the electric field strength on the surface of the device. Furthermore, the field dielectric layer structure includes a second dielectric layer and a first dielectric layer, the first dielectric layer includes a plurality of first dielectric parts, and the plurality of first dielectric parts are inserted into the second dielectric layer along a first direction. Compared with the structure with only the second dielectric layer, since the dielectric constant of the first dielectric layer is higher than that of the second dielectric layer, the high dielectric constant material is more easily polarized by the electric field, weakening the electric field strength. Therefore, the first dielectric layer can improve the electric field at the sharp corner of the second dielectric layer, further reducing the electric field strength on the device surface. The top region is arranged corresponding to the first dielectric part, so that when the top region is formed, the second dielectric layer can be used as an injection blocking layer, and no additional mask design is required, thereby reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 It is one of the structural schematic diagrams of a semiconductor structure provided in an embodiment;

[0034] Figure 2 The second structural schematic diagram of a semiconductor structure provided in an embodiment;

[0035] Figure 3 The third structural schematic diagram of a semiconductor structure provided in an embodiment;

[0036] Figure 4 A schematic diagram of a process for preparing a semiconductor structure provided by an embodiment;

[0037] Figure 5 A schematic structural diagram of a structure obtained in step S300 of a method for preparing a semiconductor structure provided in an embodiment;

[0038] Figure 6 A schematic structural diagram of a structure obtained in step S400 of a method for preparing a semiconductor structure provided in an embodiment;

[0039] Figure 7 A schematic structural diagram of a structure obtained in step S500 of a method for preparing a semiconductor structure provided in an embodiment;

[0040] Figure 8 A schematic structural diagram of a structure obtained in step S610 of a method for preparing a semiconductor structure provided in an embodiment;

[0041] Fig. 9 A schematic structural diagram of a structure obtained in step S620 of a method for preparing a semiconductor structure provided in an embodiment;

[0042] Fig.10 This is a schematic structural diagram of a structure obtained in step S600 of a method for preparing a semiconductor structure provided in an embodiment.

[0043] Description of reference numerals:

[0044] 100 - substrate, 200 - drift region, 300 - field dielectric layer structure, 310 - second dielectric layer, 311 - trench, 320 - first dielectric layer, 321 - first dielectric material layer, 400 - top region, 500 - body region, 600 - source, 700 - drain, 800 - gate, 900 - substrate end. DETAILED DESCRIPTION

[0045] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0048] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0049] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the regions of the device, and do not limit the scope of the invention.

[0051] In one embodiment, see Figure 1 , Figure 2 or Figure 3 The present application provides a semiconductor structure, including a substrate 100, a drift region 200 of a first doping type, a field dielectric layer structure 300, and a plurality of top regions 400 of a second doping type. The first doping type is opposite to the second doping type.

[0052] The material of the substrate 100 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can also be a ceramic substrate, a quartz or glass substrate, etc., which is not limited in this embodiment.

[0053] The drift region 200 is located in the substrate 100. The surface of the drift region 200 is flush with the surface of the substrate 100. The drift region 200 may be an N-type drift region or a P-type drift region.

[0054] The field dielectric layer structure 300 includes a second dielectric layer 310 and a first dielectric layer 320. The second dielectric layer 310 is located on a surface of the drift region 200 away from the substrate 100, and the first dielectric layer 320 includes a plurality of first dielectric portions, which are inserted into the second dielectric layer 310 along a first direction. The first direction is perpendicular to the direction of the substrate 100 pointing to the field dielectric layer structure 300. The extension length of the first dielectric portion in the third direction may be less than or equal to the extension length of the second dielectric layer 310, and the third direction is perpendicular to the first direction. Figure 1 As shown, the first direction may be the OY direction, and the third direction may be the OX direction; Figure 2 or Figure 3 As shown, the first direction may be the OX direction, and the third direction may be the OY direction. The second dielectric layer 310 may be a field oxide layer, and the material of the second dielectric layer 310 may be a combination of one or more of silicon oxide, silicon oxycarbide, etc. The dielectric constant of the first dielectric layer 320 is higher than the dielectric constant of the second dielectric layer 310. Exemplarily, the first dielectric layer 320 may be silicon nitride. On the XOY plane, the cross-sectional shape of the first dielectric layer 320 may be a fence shape, a sawtooth shape, a diamond shape, etc., which is not limited in the embodiments of the present application.

[0055] A plurality of second doping type top regions 400 are arranged in the drift region 200 at intervals along the first direction, and the top regions 400 are arranged corresponding to the first dielectric portion. A surface of the top region 400 away from the substrate 100 is flush with the surface of the drift region 200. On the XOY plane, the cross-sectional shape of the top region 400 is the same as the cross-sectional shape of the first dielectric portion, which may be fence-shaped, sawtooth-shaped, or diamond-shaped.

[0056] In the embodiment of the present application, the semiconductor structure includes a substrate 100, a drift region 200 of a first doping type, a field dielectric layer structure 300, and a plurality of top regions 400 of a second doping type. The drift region 200 is located in the substrate 100, the field dielectric layer structure 300 is located on a side surface of the drift region 200 away from the substrate 100, and the top regions 400 are arranged in the drift region 200 at intervals along the first direction. The plurality of top regions 400 of the second doping type and the drift region 200 of the first doping type form a multiple RESURF structure, and a plurality of PN junctions are formed on the top of the drift region 200. The longitudinal depletion of the plurality of PN junctions is used to improve the electric field distribution on the top of the drift region 200, improve the depletion capacity of the drift region 200, and reduce the electric field strength on the device surface. In addition, by increasing the doping concentration of the drift region 200, it is ensured that during the operation of the device, when the ions in the top region 400 are inverted, the net doping concentration of the drift region 400 can be maintained within a preset range, and the increase in the doping concentration of the drift region 200 can also reduce the on-resistance of the device. By forming a multiple RESURF structure with the top region 400 and the drift region 200, and increasing the doping concentration of the drift region 200, the on-resistance of the device is reduced while reducing the electric field strength on the device surface. Further, the field dielectric layer structure 300 includes a second dielectric layer 310 and a first dielectric layer 320, and the first dielectric layer 320 includes a plurality of first dielectric portions, and the plurality of first dielectric portions are inserted into the second dielectric layer 310 along the first direction. Compared with the structure with only the second dielectric layer 310, since the dielectric constant of the first dielectric layer 320 is higher than the dielectric constant of the second dielectric layer 310, the high dielectric constant material is more easily polarized by the electric field, and the electric field strength is weakened. Therefore, the first dielectric layer 320 can improve the electric field at the sharp corner of the second dielectric layer 310, and further reduce the electric field strength on the device surface. The top region 400 is arranged corresponding to the first dielectric portion, so that when the top region 400 is formed, the second dielectric layer 310 can be used as an injection blocking layer, and no additional mask design is required, thereby reducing the manufacturing cost.

[0057] In one embodiment, the second dielectric layer 310 includes a plurality of second dielectric portions, and the first dielectric portions and the second dielectric portions are alternately arranged along the first direction. Figure 1 As shown, the first dielectric portion and the second dielectric portion are arranged alternately along the OY direction; Figure 2 As shown, the first dielectric part and the second dielectric part are arranged alternately along the OX direction. The arrangement of the first dielectric part and the second dielectric part can be set according to the actual business scenario, and the layout of the top region 400 in the drift region 200 can be changed to improve the electric field intensity distribution in different directions.

[0058] In one embodiment, the ion doping concentration of the top region 400 is greater than the ion doping concentration of the drift region 200, so that the top region 400 is of the second doping type. The specific values ​​of the ion doping concentration of the top region 400 and the ion doping concentration of the drift region 200 can be reasonably set according to the actual business scenario, and the embodiment of the present application is not limited here.

[0059] In one embodiment, please refer to Figure 1 , Figure 2 or Figure 3 , the semiconductor structure further includes a body region 500. The body region 500 is located in the substrate 100, and the body region 500 and the drift region 200 are arranged along a second direction, the second direction is the same as the first direction, or the second direction is perpendicular to the first direction and perpendicular to the direction of the substrate 100 pointing to the field dielectric layer structure 300. The second direction can be an OY direction. When forming an NMOS tube, the ion doping type of the body region 500 is P type; when forming a PMOS tube, the doping type of the body region 500 is N type.

[0060] Further, the semiconductor structure further includes a source 600, a drain 700 and a gate 800. The source 600 is located in the body region 500. The drain 700 is located in the drift region 200 and is located on the side of the field dielectric layer structure 300 away from the body region 500. The gate 800 is located on the surface of the side of the substrate 100 close to the drift region 200, covering part of the body region 500 and at least part of the second dielectric layer 310. Taking the NMOS transistor as an example, the source 600 and the drain 700 are both N-type doped regions, the source 600 is located in the P-type body region 500, the drain 700 is located in the N-type drift region 200, a P-type top region 400 is provided in the N-type drift region 200 between the source 600 and the drain 700, and a field dielectric layer structure 300 composed of a second dielectric layer 310 and a first dielectric layer 320 is provided on the N-type drift region 200 between the source 600 and the drain 700. The gate 800 is located on a surface of the substrate 100 close to the N-type drift region 200, covering a portion of the P-type body region 500 and at least a portion of the second dielectric layer 310. The gate 800 may be made of polysilicon, metal gate, or the like.

[0061] In addition, a substrate terminal 900 (bulk) is provided in the body region 500 . The substrate terminal 900 is connected to the source 600 . The ion doping type of the substrate terminal 900 is opposite to that of the source 600 .

[0062] In this embodiment, the field dielectric layer structure 300 between the gate 800 and the drift region 200 can prevent the direct current flow between the gate 800 and the drift region 200, and play a role of isolation and protection. In addition, the gate 800 in the embodiment of the present application can also play the role of a field plate, which can improve the electric field distribution and withstand voltage performance of the device. In some embodiments, the gate 800 also covers at least a portion of the first dielectric portion.

[0063] In one embodiment, see Figure 4 , the present application also provides a method for preparing a semiconductor structure, including steps S100-S600.

[0064] S100 , providing a substrate.

[0065] S200 , forming a drift region of a first doping type in a substrate.

[0066] See also Figure 5 A drift region 200 of the first doping type may be formed in the substrate 100 by a doping process or a diffusion process.

[0067] S300, forming a second dielectric layer on a surface of the drift region away from the substrate.

[0068] Please continue reading Figure 5 The second dielectric layer 310 can be formed on the surface of the drift region 200 away from the substrate 100 by a deposition process, such as an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process or a low pressure chemical vapor deposition (LPCVD) process. The material of the second dielectric layer 310 can be one of silicon oxide or silicon oxycarbide or a combination thereof.

[0069] S400, forming a plurality of grooves spaced apart along a first direction in the second dielectric layer; the first direction is perpendicular to the direction of the substrate pointing toward the second dielectric layer.

[0070] See also Figure 6 , a plurality of grooves 311 spaced apart along a first direction may be formed in the second dielectric layer 310 by dry etching, wet etching or a combination of dry etching and wet etching. The first direction may be the OX direction, the OY direction or other directions. The extension length of the groove 311 in the third direction may be the same as the extension length of the second dielectric layer 310, or may be less than the extension length of the second dielectric layer 310. The cross-sectional shape of the groove 311 may be a fence shape, a sawtooth shape or a diamond shape, etc. The formed groove 311 may be used to locate the position of the second doping type top region 400 formed subsequently and the position of the first dielectric portion. In addition, each portion of the second dielectric layer separated by the groove 311 may serve as a second dielectric portion.

[0071] S500, using the second dielectric layer as an injection blocking layer, forming a plurality of second doping type top regions in the drift region based on the trenches. The first doping type is opposite to the second doping type.

[0072] See also Figure 7 , the second dielectric layer 310 can be used as an injection barrier layer, and ion implantation is performed on the drift region 200 based on the groove 311, so as to form a plurality of second doping type top regions 400 in the drift region 200. The concentration and depth of ion implantation can be reasonably set according to the actual business scenario, and the embodiment of the present application is not limited here.

[0073] S600, forming a first dielectric portion in the trench, wherein a plurality of first dielectric portions constitute a first dielectric layer, and the first dielectric layer and the second dielectric layer constitute a field dielectric layer structure.

[0074] See also Fig.10 A deposition process may be used to form a first dielectric portion in the trench. The dielectric constant of the first dielectric portion is higher than the dielectric constant of the second dielectric layer 310. For example, the first dielectric portion may be silicon nitride.

[0075] In an embodiment of the present application, a substrate 100 is provided, a drift region 200 of a first doping type is formed in the substrate 100, a second dielectric layer 310 is formed on a surface of the drift region 200 away from the substrate 100, a plurality of grooves spaced along a first direction are formed in the second dielectric layer 310, the second dielectric layer 310 is used as an injection barrier layer, a plurality of top regions 400 of a second doping type are formed in the drift region 200 based on the grooves, the plurality of top regions 400 of the second doping type and the drift region 200 of the first doping type form a multiple RESURF structure, a plurality of PN junctions are formed on the top of the drift region 200, the electric field distribution at the top of the drift region 200 is improved by longitudinal depletion of the plurality of PN junctions, the depletion capacity of the drift region 200 is improved, and the electric field strength on the device surface is reduced. By increasing the doping concentration of the drift region 200, it is ensured that during the operation of the device, when the ions in the top region 400 are inverted, the net doping concentration of the drift region 400 can be maintained within a preset range. The increase in the doping concentration of the drift region 400 can also reduce the on-resistance of the device. Through the mutual cooperation of technical features such as the top region 400 and the drift region 200 forming a multiple RESURF structure and increasing the doping concentration of the drift region 200, the on-resistance of the device is reduced while reducing the surface electric field strength of the device. In addition, the second dielectric layer 310 is used as an injection blocking layer, and no additional mask is required, which can reduce manufacturing costs. Furthermore, a first dielectric portion is formed in the groove, wherein multiple first dielectric portions constitute a first dielectric layer 320, and the first dielectric layer 320 and the second dielectric layer 310 constitute a field dielectric layer structure 300. Since the dielectric constant of the first dielectric layer 320 is higher than that of the second dielectric layer 310, the high dielectric constant material is more easily polarized by the electric field, thereby weakening the electric field strength. Therefore, the first dielectric layer 320 can improve the electric field at the sharp corners of the second dielectric layer 310, thereby further reducing the electric field strength on the device surface.

[0076] In one embodiment, forming a first dielectric portion in the trench includes steps S610 - S620 .

[0077] S610 , forming a first dielectric material layer in the plurality of trenches and on a surface of a second dielectric layer away from the drift region.

[0078] Please participate Figure 8A deposition process, such as an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process or a low pressure chemical vapor deposition (LPCVD) process, can be used to deposit the first dielectric material in the plurality of grooves 311 and on a surface of the second dielectric layer 310 away from the drift region 200 to form a first dielectric material layer 321.

[0079] S620 , removing the first dielectric material layer on a surface of the second dielectric layer away from the drift region to form a first dielectric portion.

[0080] Please participate Fig. 9 A wet cleaning process (for example, hot phosphoric acid solution (H3PO4) cleaning) can be used to remove the first dielectric material layer 321 on the side surface of the second dielectric layer 310 away from the drift region 200 to form a first dielectric portion. The thickness of the first dielectric portion is less than the thickness of the second dielectric layer 310.

[0081] In this embodiment, since the thickness of the first dielectric portion is less than the thickness of the second dielectric layer 310, the first dielectric layer 320 and the second dielectric layer 310 form a stepped field dielectric layer structure 300, so that the gate 800 formed subsequently and extending above the field dielectric layer structure 300 is a stepped structure. The stepped field plate formed by the gate 800 and the field dielectric layer structure 300 can avoid the formation of a local peak electric field in the drift region 200, make the electric field distribution in the drift region 200 more uniform, reduce the device surface electric field, and prevent the gate oxide layer from being broken down.

[0082] In some embodiments, forming the first dielectric portion in the trench further includes a step of planarizing the second dielectric layer so that the second dielectric layer is flush with the surface of the first dielectric layer.

[0083] See also Fig.10 The second dielectric layer 310 may be planarized by chemical mechanical polishing (CMP) to make the second dielectric layer 310 flush with the surface of the first dielectric layer 320 , thereby improving the flatness of the surface of the field dielectric layer structure 300 composed of the first dielectric layer 320 and the second dielectric layer 310 .

[0084] It should be understood that although Figure 4The steps in the flowchart are shown in the order shown, but these steps are not necessarily executed in this order. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 4 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0085] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0086] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A drift region of a first doping type, located in the substrate; A field dielectric layer structure, comprising a first dielectric layer and a second dielectric layer; The second dielectric layer is located on a surface of the drift region away from the substrate; the first dielectric layer includes a plurality of first dielectric portions, and the plurality of first dielectric portions are inserted into the second dielectric layer along a first direction; wherein the first direction is perpendicular to a direction from the substrate to the field dielectric layer structure; A plurality of second doping type top regions are arranged in the drift region at intervals along a first direction, and the top regions are arranged corresponding to the first dielectric portion; the first doping type is opposite to the second doping type.

2. The semiconductor structure according to claim 1, characterized in that: The second dielectric layer includes a plurality of second dielectric portions, and the first dielectric portions and the second dielectric portions are alternately arranged along a first direction.

3. The semiconductor structure according to claim 1, characterized in that: The ion doping concentration of the top region is greater than the ion doping concentration of the drift region.

4. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A body region is located in the substrate, and the body region and the drift region are arranged along a second direction, the second direction is the same as the first direction, or the second direction is perpendicular to the first direction and perpendicular to the direction of the substrate pointing to the field dielectric layer structure.

5. The semiconductor structure according to claim 4, characterized in that: The semiconductor structure further comprises: a source electrode, located in the body region; A drain electrode is located in the drift region and on a side of the field dielectric layer structure away from the body region; The gate is located on a surface of the substrate close to the drift region and covers a portion of the body region and at least a portion of the second dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that: The gate also covers at least a portion of the first dielectric portion.

7. The semiconductor structure according to claim 1, characterized in that: The first dielectric layer includes silicon nitride.

8. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a drift region of a first doping type in the substrate; forming a second dielectric layer on a surface of the drift region away from the substrate; forming a plurality of grooves spaced apart along a first direction in the second dielectric layer; The first direction is perpendicular to the direction of the substrate pointing to the second dielectric layer; The second dielectric layer is used as an injection blocking layer, and a plurality of top regions of a second doping type are formed in the drift region based on the trench; the first doping type is opposite to the second doping type; A first dielectric portion is formed in the groove; wherein a plurality of the first dielectric portions form a first dielectric layer, and the first dielectric layer and the second dielectric layer form a field dielectric layer structure.

9. The method according to claim 8, characterized in that The forming of the first dielectric portion in the groove comprises: forming a first dielectric material layer in the plurality of trenches and on a surface of the second dielectric layer away from the drift region; The first dielectric material layer on a surface of the second dielectric layer away from the drift region is removed to form a first dielectric portion, wherein the thickness of the first dielectric portion is smaller than the thickness of the second dielectric layer.

10. The method according to claim 9, characterized in that The forming of the first dielectric portion in the groove further comprises: The second dielectric layer is planarized to make the second dielectric layer flush with the surface of the first dielectric layer.

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