A packaging method of an enhanced gallium nitride power semiconductor device

Abstract

The application provides a packaging method of an enhanced gallium nitride power semiconductor device, and belongs to the technical field of chip manufacturing. The application firstly optimizes the electrode spacing and dielectric layer parameters through three-dimensional electric field distribution simulation, then realizes efficient thermal connection of the chip and the heat dissipation substrate by using a silver sintering process, and designs a multilayer field plate structure to disperse the high electric field area. Then, a high dielectric constant resin layer and a low ion content epoxy molding compound are applied for insulation and packaging, and a siloxane modified polyimide protective layer is coated. The reliability is verified through electric field resistance tests, high acceleration life tests and thermal cycle tests, the micro-nano channel structure is formed by using a focused ion beam technology to relieve the local high electric field area, and finally, the performance and life of the device are evaluated based on an electric field distribution and reliability prediction model of a deep learning framework, so that the reliability problem of the gallium nitride power semiconductor device in a high voltage working environment is solved.

Description

Technical Field

[0001] This invention belongs to the field of chip manufacturing technology, and more specifically, relates to a packaging method for an enhanced gallium nitride power semiconductor device. Background Technology

[0002] Gallium nitride (GaN) power semiconductor devices are widely used in high-frequency, high-power-density power electronic systems due to their superior characteristics such as high breakdown electric field, high electron mobility, and low on-resistance. Traditional GaN device packaging technology mainly relies on simple metal lead frame structures and epoxy molding compounds, using conventional chip bonding and wire bonding processes to achieve electrical connections and physical protection. These traditional technologies can meet basic requirements in low-voltage applications, but as the operating voltage of GaN devices continues to increase, the electric field distribution problems inside and on the surface of the devices become increasingly prominent.

[0003] However, traditional packaging methods have significant drawbacks. First, conventional epoxy materials lack sufficient dielectric properties and thermal stability, making them prone to localized breakdown in high-electric-field regions. Second, the electrode structure design lacks optimization for high-electric-field regions, resulting in uneven electric field distribution. Third, the bonding process has excessively high thermal resistance, limiting the device's power density and heat dissipation capabilities. These shortcomings significantly reduce the reliability of conventionally packaged gallium nitride devices under high-voltage operating environments, and their mean time between failures (MTBF) fails to meet practical application requirements.

[0004] The core problem that existing technologies struggle to solve lies in the uneven electric field distribution inside and on the surface of gallium nitride (GaN) devices under high-voltage operating conditions. This uneven distribution creates regions with excessively high peak electric field strength, leading to premature aging of the dielectric layer, accelerated surface charge accumulation, and ultimately, insulation failure and performance degradation. In other words, existing technologies suffer from a technical problem where uneven electric field distribution in GaN power semiconductor devices under high-voltage operating conditions results in excessively high peak electric field strength in localized areas, leading to decreased device reliability. Summary of the Invention

[0005] In view of this, the present invention provides a packaging method for enhanced gallium nitride power semiconductor devices, which can solve the technical problem in the prior art where uneven electric field distribution in gallium nitride power semiconductor devices under high voltage operating conditions leads to excessively high local electric field intensity peaks, resulting in decreased device reliability.

[0006] This invention is implemented as follows: A packaging method for an enhanced gallium nitride (GaN) power semiconductor device includes: performing three-dimensional electric field distribution simulation on a GaN chip, and optimizing the electrode spacing and dielectric layer thickness based on the simulation data; fixing the GaN chip on a heat dissipation substrate to form a heat conduction path; designing surface electrodes of the GaN chip using a multilayer field plate structure; applying a high-dielectric-constant resin layer between the GaN chip and the lead frame; performing primary packaging using a low-ion-content epoxy molding compound; conducting electric field tolerance tests on the packaged GaN chip; coating the outer layer of the GaN chip with a siloxane-modified polyimide insulating coating; conducting high-acceleration lifetime testing and thermal cycling tests; using focused ion beam technology to form a micro / nano channel structure in a high electric field region, constructing a local electric field buffer to complete the packaging; and using an electric field distribution and reliability prediction model to calculate the expected lifespan and failure probability curve of the packaged GaN chip.

[0007] The three-dimensional electric field distribution simulation includes simulations of electric field strengths exceeding 3 × 10⁻⁶ in the three-dimensional electric field distribution simulation results. 6 The region of volts / cm was marked, and the electrode spacing was optimized to 20 to 30 μm and the dielectric layer thickness to 3 to 5 μm based on the three-dimensional electric field distribution simulation data.

[0008] The step of fixing the gallium nitride chip onto the heat dissipation substrate includes fixing the gallium nitride chip onto a heat dissipation substrate made of aluminum nitride ceramic material, and performing chip bonding at a temperature of 250 to 300°C using a silver sintering process to form a heat conduction path with a thermal resistance of less than 0.1 cm²·°C / W.

[0009] The multilayer field plate structure is formed by sequentially depositing titanium, aluminum, nickel, and gold. The total thickness of the multilayer field plate structure is 0.8 to 1.2 μm, and the extension length of the multilayer field plate structure is 25% to 40% of the distance from the source to the drain.

[0010] The high dielectric constant resin layer has a breakdown strength of not less than 500 KV / mm, a thickness of 50 to 100 μm, and covers the entire high electric field region.

[0011] The primary encapsulation using low-ion-content epoxy molding compound includes vacuum injection molding at 120 to 150°C and a pressure of 5 to 8 MPa to ensure no bubbles or delamination.

[0012] The electric field tolerance test of the packaged gallium nitride chip includes applying a voltage 20% higher than the rated operating voltage for 168 hours, and measuring the change in surface leakage current to be no more than 5% of the original value.

[0013] The siloxane-modified polyimide insulating coating has a thickness of 15 to 25 μm, a curing temperature of 180 to 220°C, and a curing time of 60 to 90 minutes.

[0014] The electric field distribution and reliability prediction model is calculated based on the acquired geometric parameters, material parameters, electric field distribution data and surface leakage current data of the gallium nitride chip, and outputs the expected service life and failure probability curve of the gallium nitride chip.

[0015] The electric field distribution and reliability prediction model is a hierarchical deep learning framework consisting of an upper-level electric field distribution model and a lower-level material reliability model. The upper-level electric field distribution model uses a geometric structure perception module based on a graph neural network to extract the physical structure features of the gallium nitride chip, while the lower-level material reliability model uses a long short-term memory network with a hybrid attention mechanism to predict the lifetime evolution curve of the gallium nitride chip under different stress conditions.

[0016] The coupling between the upper-level electric field distribution model and the lower-level material reliability model is reflected in the fact that the peak value of the local electric field intensity, the electric field gradient, and the surface charge distribution output by the upper-level electric field distribution model directly affect the material interface aging rate parameters in the lower-level material reliability model.

[0017] The number of heads in the multi-head attention mechanism of the upper-level electric field distribution model and the lower-level material reliability model is dynamically adjusted based on three key parameters: the extension length of the multilayer field plate structure, the breakdown strength of the high dielectric constant resin layer, and the rated operating voltage.

[0018] This invention combines key technologies such as multilayer field plate structure design, application of high dielectric constant resin layer, silver sintering process, and surface micro / nano channel structure to form a complete high-reliability packaging technology system. The method first optimizes the electrode structure and dielectric layer parameters based on three-dimensional electric field distribution simulation results, then uses high-performance materials and precise processes to achieve packaging, and finally verifies the reliability of the device through rigorous testing and model evaluation.

[0019] This invention addresses the shortcomings of traditional technologies, particularly by achieving effective dispersion and homogenization of the electric field intensity in high-electric-field regions. The multilayer field plate structure and micro / nano channel design significantly reduce local electric field peaks; the high-dielectric-constant resin layer and siloxane-modified polyimide coating provide excellent insulation protection; and the silver sintering process greatly improves thermal conductivity. Through the synergistic effect of these technologies, this invention significantly improves the electric field distribution of gallium nitride devices under high-voltage operating environments.

[0020] This invention optimizes the key structure of gallium nitride (GaN) devices using the principles of electric field engineering, achieving uniform electric field distribution and peak intensity control. Simultaneously, a deep learning-based electric field distribution and reliability prediction model provides precise guidance for device design, enabling end-to-end quality control from simulation optimization to practical verification. This solves the technical problem in existing technologies where uneven electric field distribution in GaN power semiconductor devices under high-voltage operating environments leads to excessively high local electric field peaks, resulting in decreased device reliability. Attached Figure Description

[0021] Figure 1 This is a flowchart of the method of the present invention.

[0022] Figure 2 This is a schematic diagram of the overall structure of the enhanced gallium nitride power semiconductor device in Example 2.

[0023] Figure 3 This is the internal structure of the gallium nitride chip in Example 2.

[0024] Figure 4 This is a schematic diagram of the multilayer field plate structure in Example 2.

[0025] Figure 5 This is a schematic diagram of the micro-nano channel structure in Example 2.

[0026] Figure 6 This is a schematic diagram of the chip heat dissipation direction in Example 2. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0028] like Figure 1 The diagram shown is a flowchart of a packaging method for an enhanced gallium nitride power semiconductor device provided by the present invention. This method includes the following steps:

[0029] S01. Three-dimensional electric field distribution simulation: Perform three-dimensional electric field distribution simulation on the gallium nitride chip. For simulation results where the electric field strength exceeds 3 × 10⁻⁶, the simulation is deemed appropriate. 6 The region of volts / cm was marked, and the electrode spacing was optimized to 20 to 30 μm and the dielectric layer thickness to 3 to 5 μm based on the three-dimensional electric field distribution simulation data;

[0030] S02, Basic Fixing: The gallium nitride chip is fixed on a heat dissipation substrate made of aluminum nitride ceramic material, and chip bonding is performed at a temperature of 250 to 300°C using a silver sintering process to form a heat conduction path with a thermal resistance of less than 0.1 square cm·°C / W.

[0031] S03. Electrode Design: The surface electrodes of the gallium nitride chip are designed with a multilayer field plate structure. The multilayer field plate structure is formed by sequentially depositing titanium, aluminum, nickel and gold. The total thickness of the multilayer field plate structure is 0.8 to 1.2 μm, and the extension length of the multilayer field plate structure is 25% to 40% of the distance from the source to the drain.

[0032] S04. Applying a resin layer: Applying a high dielectric constant resin layer between the gallium nitride chip and the lead frame. The breakdown strength of the high dielectric constant resin layer is not less than 500KV / mm, the thickness of the high dielectric constant resin layer is 50 to 100μm, and the high dielectric constant resin layer covers the entire high electric field region.

[0033] S05, Primary Encapsulation: Primary encapsulation is performed using low-ion content epoxy molding compound, and is carried out by vacuum injection molding at 120 to 150°C and 5 to 8 MPa to ensure no bubbles and no delamination.

[0034] S06, Electric Field Susceptibility Test: The packaged gallium nitride chip is subjected to an electric field susceptibility test. A voltage 20% higher than the rated operating voltage is applied for 168 hours, and the change in surface leakage current is measured to be no more than 5% of the original value.

[0035] S07. Apply an insulating coating: Coat the outer layer of the gallium nitride chip with a siloxane-modified polyimide insulating coating. The thickness of the siloxane-modified polyimide insulating coating is 15 to 25 μm, the curing temperature is 180 to 220°C, and the curing time is 60 to 90 minutes.

[0036] S08. Lifetime Test: The finished gallium nitride chip is subjected to a high-acceleration lifetime test. Under the conditions of 125°C ambient temperature and 85% relative humidity, 80% of the rated voltage is applied. The high-acceleration lifetime test lasts for 1000 hours, and the leakage current change curve is recorded.

[0037] S09. Packaging reliability test: The reliability of the gallium nitride chip packaging is verified by thermal cycling test. The temperature range is -40 to 150°C, the heating rate is 15°C per minute, the cooling rate is 10°C per minute, and the thermal cycling test is performed for a total of 500 cycles.

[0038] S10. Surface electric field distribution analysis: The surface electric field distribution of the gallium nitride chip is analyzed based on the high electric field stress model. Micro-nano channel structures are formed in the high electric field region using focused ion beam technology. The depth of the micro-nano channel structure is 1 to 2 μm, the width of the micro-nano channel structure is 0.5 to 1 μm, and the spacing between the micro-nano channel structures is 5 to 10 μm, thus constructing a local electric field buffer zone.

[0039] S11, Optionally, also includes performance evaluation: using an electric field distribution and reliability prediction model to evaluate the performance of the gallium nitride chip, wherein the electric field distribution and reliability prediction model is calculated based on the geometric parameters, material parameters, electric field distribution data and surface leakage current data of the gallium nitride chip obtained in steps S01 to S10, and outputs the expected service life and failure probability curve of the gallium nitride chip.

[0040] Specifically, the three-dimensional electric field distribution simulation involves using finite element analysis software to construct a geometric model of the gallium nitride chip, inputting the dielectric parameters of each material, and calculating the electric field distribution at various points inside and on the surface of the entire gallium nitride chip structure under different operating voltages.

[0041] The multilayer field plate structure is specifically a metal electrode that extends near the drain or gate of a gallium nitride chip. By increasing the radius of curvature of the electrode edge, the high electric field region is expanded and dispersed, thereby reducing the peak value of the local electric field intensity.

[0042] Specifically, the silver sintering process utilizes nano-silver paste to form a dense connection at a certain temperature, resulting in a chip connection method with higher thermal conductivity and lower resistivity compared to traditional solders.

[0043] Among them, the high-accelerated life test is a method for evaluating the long-term reliability of gallium nitride chips by applying environmental stresses that exceed normal usage conditions to accelerate the aging process of gallium nitride chips.

[0044] Among them, low-ion content epoxy molding compound is a high-purity epoxy resin composite material with impurities such as chloride ions and sodium ions of less than 10 ppm, which can effectively prevent metal migration and electrochemical corrosion.

[0045] Specifically, the siloxane-modified polyimide insulating coating is a high-performance composite insulating material that combines the heat resistance of polyimide with the hydrophobicity of siloxane by introducing siloxane bonds into the molecular structure of polyimide.

[0046] The high electric field stress model equation is used to predict the physical deformation and microstructure changes at the material interface caused by the high electric field. The inputs include the dielectric constant of the high dielectric constant resin layer in step S04, the polarization intensity generated by the electrode geometry obtained in step S03, the local electric field intensity distribution function obtained in step S01, the interface bonding energy between the high dielectric constant resin layer and the gallium nitride chip used in step S04, and the elastic modulus of the high dielectric constant resin layer material used in step S04. The outputs are the stress tensor and critical breakdown electric field intensity at the interface between the high dielectric constant resin layer and the gallium nitride chip in step S04. The high electric field stress model is based on the balance between the electrostatic force and the interface stress caused by the accumulation of polarization charge at the material interface. By solving the coupled equations between the Maxwell stress tensor and the material deformation response, it predicts the stress distribution at the interface under different electric field intensities, and then evaluates the reliability limit and failure mechanism of the gallium nitride chip under high voltage operation. The high electric field stress model can accurately capture the phenomenon of electric stress concentration, providing a theoretical basis for the design and optimization of multilayer field plate structures.

[0047] Among them, the micro-nano channel structure is a micro-groove array formed by etching on the surface of gallium nitride chip through focused ion beam technology. It is used to control the electric field distribution and reduce the peak intensity of the surface electric field.

[0048] The electric field distribution and reliability prediction model is structured as a hierarchical deep learning framework consisting of an upper-level electric field distribution model and a lower-level material reliability model. The upper-level electric field distribution model uses a graph neural network-based geometric structure perception module to extract the physical structure features of the gallium nitride (GaN) chip. The lower-level material reliability model uses a hybrid attention mechanism-based long short-term memory network to predict the lifetime evolution curves of the GaN chip under different stress conditions. The upper-level electric field distribution model's inputs include the GaN chip geometric model obtained in step S01, the electrode shape parameters designed in step S03, and the dielectric material distribution and electrical properties used in step S04. Its objective function is to minimize the mean square error between the simulated and measured electric field distributions. The upper-level electric field distribution model's constraints include that the electric field distribution satisfies the Poisson equation and that the potential is continuous. The lower-level material reliability model's inputs are the electric field distribution results output by the upper-level electric field distribution model and external condition parameters such as temperature, humidity, and operating voltage from steps S08 and S09. The scaling function minimizes the log-likelihood loss between the predicted failure time and the measured failure time. The constraint condition of the lower-level material reliability model is that the failure probability increases monotonically with time and satisfies the basic characteristics of the Weibull distribution. The coupling between the upper-level electric field distribution model and the lower-level material reliability model is reflected in the fact that the peak value of the local electric field intensity, the electric field gradient, and the surface charge distribution output by the upper-level electric field distribution model directly affect the material interface aging rate parameter in the lower-level material reliability model. The failure probability distribution fed back by the lower-level material reliability model guides the upper-level electric field distribution model to optimize the electrode structure design and material selection. The number of heads in the multi-head attention mechanism in the upper-level electric field distribution model and the lower-level material reliability model is dynamically adjusted according to three key parameters: the extension length of the multilayer field plate structure in step S03, the breakdown strength of the high dielectric constant resin layer in step S04, and the rated operating voltage in step S06. The calculation of the number of heads in the multi-head attention mechanism adopts an adaptive algorithm, allocating more attention heads to capture more complex electric field distribution features when the voltage level of the gallium nitride chip is higher.

[0049] The steps involved in establishing the training dataset for the electric field distribution and reliability prediction model training process specifically include: collecting a total of 5,000 gallium nitride power device samples with different structural parameters; each sample containing complete gallium nitride chip geometric parameters, material property parameters, operating voltage parameters, and measured failure data; using finite element software to generate corresponding high-precision electric field distribution simulation results as labeled data; performing data augmentation on the samples, expanding the sample size to 15,000 groups by randomly perturbing the geometric and material parameters; dividing the training set, validation set, and test set into an 8:1:1 ratio; standardizing the data to ensure that all feature values ​​are evenly distributed within the zero-mean, unit-variance range; constructing a multi-level labeling system, including multi-dimensional label information such as electric field distribution tensor, key point electric field strength values, expected lifespan, and failure probability curves; and cleaning and consistency checking the dataset based on physical knowledge to ensure that the data conforms to basic electromagnetic principles and materials science laws.

[0050] The training steps for the electric field distribution and reliability prediction model specifically include: firstly, training the upper-level electric field distribution model using unsupervised learning, establishing a mapping relationship between the geometric structure and the electric field distribution using the finite element simulation data obtained in step S01; then, training the lower-level material reliability model using supervised learning, using the actual failure data obtained in step S08 as labels to train the network; next, jointly training the entire electric field distribution and reliability prediction model, optimizing the parameters of the upper-level electric field distribution model and the lower-level material reliability model through end-to-end gradient backpropagation; during the training process, a learning rate annealing strategy is adopted, with an initial learning rate set to 0.001, decaying every 20 cycles. The weights are reduced to 0.9 times their original value; a regularization term is added to prevent overfitting, and the weight decay coefficient is set to 0.0005; gradient pruning is used to prevent gradient explosion, and the maximum gradient norm is set to 5.0; an early stopping strategy is used, terminating training when the loss function on the validation set no longer decreases for 10 consecutive cycles; after training, the performance of the electric field distribution and reliability prediction model is evaluated on the test set, requiring the relative error of electric field distribution prediction to be less than 5% and the relative error of failure time prediction to be less than 15%; finally, the weights of the trained electric field distribution and reliability prediction model are saved as a lightweight version, and the complexity of the electric field distribution and reliability prediction model is reduced through knowledge distillation to ensure efficient operation on embedded systems.

[0051] The specific implementation of the above steps is described in detail below. Step S01 involves constructing a three-dimensional geometric model of the gallium nitride (GaN) chip using finite element analysis software. This model includes the entire structure, including the GaN epitaxial layer, channel layer, field plate electrodes, source, drain, and gate. First, the dielectric constants of each material are input, such as 9.0 for GaN, 3.9 for silicon dioxide, and 7.5 for silicon nitride. The mesh density is set to at least 10 mesh points per μm in the high electric field region and at least 3 mesh points per μm in the low electric field region. Then, under different voltage conditions, the potential distribution is solved using the Poisson equation, and the three-dimensional electric field distribution is obtained through the potential gradient calculation. For electric field strengths exceeding 3 × 10⁻⁶, the electric field distribution is further optimized. 6 For regions with electric field strength of volts per centimeter (V / cm), the system employs an adaptive labeling algorithm for identification. These regions are typically located at the gate edge and field plate terminations. Based on this electric field distribution data, the electrode spacing is optimized through parameter scanning, set within the range of 20 to 30 μm. Simultaneously, the dielectric layer thickness is optimized to 3 to 5 μm, a thickness that ensures sufficient dielectric strength without excessively increasing thermal resistance. These parameters are determined by comparing the maximum electric field strength under different geometries. The ultimate optimization goal is to reduce the maximum electric field strength below the critical breakdown electric field while maintaining good device conduction characteristics.

[0052] The specific implementation of step S02 involves using a high thermal conductivity aluminum nitride ceramic material as the heat dissipation substrate. This material has a thermal conductivity of 170 to 220 W / m·Kelvin, significantly higher than that of traditional alumina ceramics. A three-layer metal plating of titanium, nickel, and silver is deposited on the back of the gallium nitride chip, with thicknesses of 50 nm, 200 nm, and 1000 nm respectively, to enhance the bonding strength with the silver nanoparticle paste. The particle size of the silver nanoparticle paste is controlled within the range of 20 to 50 nm, with a solid content of 85% to 90%. Under vacuum conditions, the temperature is raised to 250 to 300 °C at a heating rate of 2 to 5 °C / min, and held for 30 to 45 minutes, causing the silver nanoparticles to sinter and form a dense silver interconnect layer. The interconnect interface formed by this silver sintering process has a thickness of approximately 10 to 20 μm and a thermal conductivity of 200 to 250 W / m·Kelvin, far superior to the thermal conductivity of traditional solder (approximately 50 to 70 W / m·Kelvin). After implementing this process, the thermal resistance of the heat conduction path formed between the chip and the substrate is less than 0.1 cm²·°C / W, which can effectively dissipate the heat generated by the device under high frequency and high power operating conditions, and prevent the device performance degradation and reliability decline caused by heat accumulation.

[0053] The specific implementation of step S03 involves fabricating a multilayer field plate structure using photolithography and metal deposition techniques. First, a silicon dioxide or silicon nitride dielectric layer with a thickness of 200 to 300 nanometers is deposited on the surface of the gallium nitride chip using plasma-enhanced chemical vapor deposition (PECVD). A pattern is formed by coating with photoresist, exposure, and development. Then, a stepped structure is formed on the dielectric layer using reactive ion etching (RIE), with the dielectric layer thickness decreasing sequentially at different steps. Subsequently, a titanium layer (50 to 80 nanometers thick), an aluminum layer (400 to 600 nanometers thick), a nickel layer (50 to 100 nanometers thick), and a gold layer (200 to 300 nanometers thick) are sequentially deposited using electron beam evaporation or magnetron sputtering, forming a multilayer field plate electrode structure with a total thickness of 0.8 to 1.2 μm. The titanium layer acts as an adhesion layer, providing good interfacial bonding energy; the aluminum layer provides the main conductive channels; the nickel layer acts as a diffusion barrier layer, preventing interdiffusion between gold and aluminum; and the gold layer provides oxidation resistance and good solderability. The multilayer field plate structure extends from the source to the drain, with an extension length of 25% to 40% of the distance between the source and drain. This multilayer field plate structure effectively reduces the peak electric field intensity by increasing the radius of curvature of the electrode edges. Theoretically, it can reduce the peak electric field intensity by 30% to 50%, thereby significantly improving the breakdown voltage and reliability of the device.

[0054] The specific implementation of step S04 involves selecting a high-dielectric-constant resin material, such as polyaryletherketone or epoxy-modified polyimide, with a dielectric constant between 4.0 and 6.0 and a breakdown strength of not less than 500 kV / mm. First, the chip surface is subjected to plasma treatment to improve surface wettability and adhesion. Then, a high-dielectric-constant resin layer is precisely applied between the chip and the lead frame using precision dispensing equipment. The dispensing head temperature is controlled at 30 to 40°C, the dispensing pressure at 0.2 to 0.4 MPa, and the dispensing speed at 5 to 10 mm / s. After resin coating, it is pre-cured at 60 to 80°C for 1 to 2 hours, and then finally cured at 150 to 180°C for 2 to 3 hours. The thickness of the cured high-dielectric-constant resin layer is controlled at 50 to 100 μm, with a thickness uniformity deviation controlled within ±5%. This high-dielectric-constant resin layer completely covers the high-electric-field regions identified in step S01, ensuring that the electric field strength in these regions is reduced to a safe level. In addition, adding nano-alumina particles (content of 2% to 5%) to the resin can further improve the resin's thermal conductivity and mechanical strength, reduce the coefficient of thermal expansion, and reduce the risk of failure caused by thermal stress.

[0055] The specific implementation of step S05 involves selecting an epoxy molding compound with an ion content of less than 1 part per 10 million, achieving a temperature cycling reliability level of Level 3 in JEDEC standard J-STD-020D, and a glass transition temperature higher than 150°C. First, the mold is preheated under vacuum at 80-100°C for 60-90 minutes to completely remove moisture and gases. Then, the epoxy molding compound is preheated to 90-110°C to reduce viscosity. Vacuum injection molding is then performed at 120-150°C and a pressure of 5-8 MPa. During injection, the vacuum level is maintained at no less than 10 Pascals, and the injection speed is controlled at 5-10 cm / s. After injection, the molding compound is cured in stages within the mold: first, it is held at 150-170°C for 1-2 hours, then at 180-200°C for 2-3 hours, and finally slowly cooled to room temperature at a rate not exceeding 2°C / minute. This multi-stage curing process effectively reduces internal stress and prevents bubbles and delamination during encapsulation. After curing, ultrasonic scanning and X-ray inspection are used to evaluate the encapsulation quality, ensuring that the encapsulation is free of voids, cracks, and delamination, and that the contact interfaces are well bonded.

[0056] The specific implementation of step S06 involves constructing a high-voltage electric field withstand test platform. This platform includes a high-precision voltage source (accuracy better than 0.1%), a micro-current measurement system (accuracy reaching the nanoampere level), and a constant temperature control system (temperature fluctuation controlled within ±0.5℃). First, the packaged gallium nitride chip is stabilized at an ambient temperature of 25±2℃. The voltage is then gradually applied to 120% of the rated operating voltage, with the voltage rise rate controlled at 1% of the rated voltage per second. After reaching the target voltage, a constant voltage state is maintained for 168 hours (7 days), during which the surface leakage current value is recorded every 6 hours. During the test, the relative humidity is controlled within the range of 40% to 60% to eliminate the influence of humidity. After the test, the trend of leakage current change over time is analyzed to ensure that its change does not exceed 5% of the original value. If the leakage current change exceeds the threshold, the electrode structure and dielectric layer quality in the high electric field region need to be checked, and steps S03 and S04 need to be optimized and adjusted. This test aims to verify the stability of the packaged structure under long-term high electric field stress and evaluate the electric field distribution at the electrode edges and the performance of the dielectric material.

[0057] The specific implementation of step S07 involves preparing a siloxane-modified polyimide solution. This solution consists of a polyimide precursor, a siloxane modifier (content 10% to 15%), and an N-methylpyrrolidone solvent, with a solid content adjusted to 15% to 20%. The solution is uniformly coated onto the outer layer of a gallium nitride chip using a spin-coating process at a speed of 1000 to 1500 rpm for 30 to 45 seconds. After coating, pre-curing is performed at 60 to 80°C for 30 to 45 minutes to remove most of the solvent. Then, curing is carried out according to a multi-stage heat treatment process: first, holding at 100 to 120°C for 30 minutes, then raising the temperature to 150 to 170°C and holding for 30 minutes, and finally raising the temperature to 180 to 220°C and holding for 60 to 90 minutes. After curing, the thickness of the siloxane-modified polyimide insulating coating is 15 to 25 μm, with thickness uniformity controlled within ±10%. This coating combines the high heat resistance of polyimide (glass transition temperature >250℃) with the excellent hydrophobicity of siloxane (contact angle >100 degrees), achieving a dielectric strength of 200 to 250 KV / mm. It can effectively protect against moisture, ionic contaminants, and mechanical damage in the external environment, improving the environmental tolerance and long-term reliability of gallium nitride chips.

[0058] The specific implementation of step S08 involves using a high-accelerated life testing system conforming to JEDEC standard JESD22-A110, which has a temperature control accuracy of ±0.5℃ and a humidity control accuracy of ±2%. The packaged gallium nitride chip is placed in the test chamber, with the ambient temperature set at 125℃ and the relative humidity at 85%. Before testing, the chip is pretreated by baking at 60℃ for 24 hours to remove adsorbed moisture. After the test begins, 80% of the rated voltage is applied between the drain and source of the chip, with the gate voltage set to a turn-off state below the threshold voltage. The test lasts for 1000 hours, with a high-precision source meter recording the leakage current value hourly, with a current measurement resolution better than 10 nanoamps. After the test, the leakage current versus time curve is plotted, and the curve slope and abrupt change points are analyzed to identify potential failure mechanisms such as electrode migration, dielectric breakdown, or interface degradation. Simultaneously, scanning electron microscopy and energy dispersive spectroscopy are used to examine the chip surface morphology and composition changes, verifying the stability of the packaged structure under the triple stress of high temperature, high humidity, and high voltage.

[0059] The specific implementation of step S09 involves placing the packaged gallium nitride chip in a programmable temperature-controlled thermal cycling chamber. The chamber's temperature range is -65 to 200°C, with temperature fluctuation accuracy controlled within ±1°C. First, the chip undergoes pretreatment by baking at 60°C for 12 hours to remove moisture. Then, a thermal cycling test is performed: the temperature is lowered from 25°C to -40°C and held for 15 minutes; then increased to 150°C at a rate of 15°C / minute and held for 15 minutes; then lowered back to -40°C at a rate of 10°C / minute, and this process is repeated for a total of 500 cycles. At the end of the 1st, 100th, 200th, 300th, 400th, and 500th cycles, samples are removed for intermediate inspections, including visual inspection, ultrasonic scanning, and electrical parameter testing (leakage current, breakdown voltage, and dynamic on-resistance). The parameter changes before and after the test are compared, and the drift rate is calculated. The requirements are that the increase in leakage current should not exceed 20%, the decrease in breakdown voltage should not exceed 10%, and the increase in dynamic on-resistance should not exceed 15%. This test evaluates the mechanical stability and material interface reliability of the package structure under extreme temperature variations, with particular attention to the bonding interfaces, lead connections, and the interface between the molding compound and the chip.

[0060] The specific implementation of step S10 is based on the three-dimensional electric field distribution simulation results of step S01, constructing a high electric field stress model. This model integrates Maxwell's stress tensor theory and the finite element analysis method to calculate the mechanical stress distribution caused by the electric field. First, the electric field strength exceeds 2.5 × 10⁻⁶. 6 Regions with a voltage / cm² intensity were identified as high electric field stress areas. Then, a focused ion beam system equipped with a gallium ion source was used, with an accelerating voltage of 30 kEV and an adjustable beam current ranging from 10 picoamps to 10 nanoamps. In the high electric field region, an automated patterning algorithm was employed to design the micro / nano channel structure layout, using the gate spacing as a reference. The focused ion beam formed parallel channel structures in the high electric field region, with channel depths controlled at 1–2 μm, widths at 0.5–1 μm, and adjacent channel spacing at 5–10 μm. During etching, the ion beam current density was controlled at 0.1–0.5 picoamps / μm², and the etching rate at approximately 0.1 μm / min to ensure etching quality and dimensional accuracy. These micro / nano channels reduced the peak electric field intensity by altering the surface electric field distribution; theoretical calculations showed that this reduction could reach 15%–25%. Meanwhile, the channel structure increases the surface area, improves heat dissipation, and acts as a charge trap to capture free surface charges, forming a local electric field buffer, suppressing electric field concentration, and improving the stability and reliability of the device under high voltage operating conditions.

[0061] Step S11 is optional. Its specific implementation involves constructing an electric field distribution and reliability prediction model based on the gallium nitride chip's geometric parameters, material parameters, electric field distribution data, and surface leakage current data obtained in the preceding steps. This model consists of an upper-level electric field distribution model and a lower-level material reliability model. The upper-level electric field distribution model takes the actual geometric structure of the gallium nitride chip as input, uses a graph neural network to extract spatial features, and simulates the propagation law of the electric field in space through a message passing mechanism. The lower-level material reliability model is based on a long short-term memory network with a hybrid attention mechanism to capture the temporal characteristics of material aging. Model training adopts a phased strategy: first, the upper-level model is trained using finite element simulation data; then, the lower-level model is trained using actual failure data; and finally, joint optimization is performed. After training, the model input includes the specific geometric parameters, material parameters, and operating conditions of the gallium nitride chip, and the output is the expected service life and failure probability curves. This model can accurately predict the reliability performance of the device under given operating conditions. For example, under operating conditions of 125℃ and 85% of rated voltage, it can predict the device's mean time between failures, failure modes, and failure time distribution. This model, guiding chip structure design and packaging process optimization, can effectively improve product reliability and reduce R&D costs and time. In terms of prediction accuracy, the relative error for electric field distribution prediction is controlled within 5%, and the relative error for failure time prediction is controlled within 15%.

[0062] The detailed structure of the upper-level electric field distribution model is based on a graph neural network-based geometric perception framework, comprising a node embedding layer, a graph convolutional layer, a global pooling layer, and a fully connected output layer. The node embedding layer represents the discrete geometry of the gallium nitride (GaN) chip as a graph structure, with each node containing location coordinates and material property information. The graph convolutional layer consists of 3 to 5 layers of graph convolutional networks, each containing 64 to 128 convolutional kernels, and employs a residual connection structure to enhance gradient propagation. The global pooling layer uses an attention mechanism to weighted aggregate node features, paying particular attention to node information in high electric field regions. The fully connected output layer maps the features to a three-dimensional electric field distribution tensor. The model takes into account the GaN chip geometry, electrode shape parameters, and dielectric material distribution, and optimizes it by minimizing the mean square error between the predicted electric field distribution and the finite element simulation results, while ensuring that the electric field distribution satisfies the Poisson equation and the potential continuity constraint.

[0063] The detailed structure of the lower-level material reliability model is a hybrid attention mechanism long short-term memory network, comprising a multi-head temporal attention layer, a bidirectional long short-term memory layer, and an adaptive prediction layer. The multi-head temporal attention layer contains 4 to 8 attention heads, dynamically adjusted according to voltage levels, focusing on failure characteristics at different time scales. The bidirectional long short-term memory layer has a two-layer structure, each containing 128 to 256 hidden units, capturing long-term dependencies in the time series through forward and backward propagation. The adaptive prediction layer adjusts prediction parameters according to different operating conditions, outputting the evolution curve of the failure probability over time. The model's input consists of the electric field distribution results output from the upper-level model and external condition parameters such as temperature, humidity, and operating voltage. Optimization is achieved by minimizing the log-likelihood loss between the predicted and measured failure times, ensuring that the failure probability monotonically increases over time and conforms to the Weibull distribution.

[0064] The detailed steps for establishing the training dataset for the electric field distribution and reliability prediction model are as follows: First, sample collection was conducted, selecting 5000 sets of gallium nitride power device samples with different structural parameters, covering various geometric variations, material combinations, and operating voltage levels. Each sample set includes complete geometric structural parameters, material property parameters, operating voltage parameters, and measured failure data. Then, high-precision electric field distribution simulation results were generated using finite element method software as labeled data, with the simulation mesh accuracy set to at least 15 mesh points per μm in key areas. Next, data augmentation was performed, expanding the sample to 15000 sets by randomly perturbing the geometric parameters (±5%) and material parameters (±10%). The samples were divided into training, validation, and test sets in an 8:1:1 ratio. Data standardization adjusted all feature values ​​to a zero-mean, unit-variance distribution. A multi-level labeling system was constructed, including the electric field distribution tensor, key-point electric field strength values, expected lifetime, and failure probability curves. Finally, the dataset was cleaned and its consistency was checked based on electromagnetic principles and materials science laws to ensure data quality and physical validity.

[0065] The mathematical model or calculation process involved in this invention will be described in detail below.

[0066] The three-dimensional electric field distribution simulation in step S01 involves solving the Poisson equation, as shown below:

[0067]

[0068] In the formula, ε is the gradient operator; φ is the electric potential field function, in volts; r ε0 is the relative permittivity of the material, dimensionless; ε0 is the vacuum permittivity, with a value of 8.85 × 102. -12 Farads per meter; ρ is the charge volume density distribution function, with units of coulombs per cubic meter.

[0069] Under boundary conditions, the potential difference between the source and drain is expressed as:

[0070] φ DS =φ D -φ S =V DS ;

[0071] In the formula, φ D φ is the drain potential, measured in volts. S V is the source potential, usually set to 0 volts; DS This is the source-drain voltage, measured in volts.

[0072] After solving the Poisson equation to obtain the potential distribution, the formula for calculating the electric field strength is:

[0073]

[0074] In the formula, This is the electric field intensity vector, with units of volts per meter.

[0075] The scalar value of electric field strength is calculated as follows:

[0076]

[0077] In the formula, E x E y E z These represent the components of the electric field intensity in the x, y, and z directions, respectively, with units of volts per meter.

[0078] The parameter is obtained by using the material's relative permittivity ε. r Obtained through material handbooks, such as ε of gallium nitride. r The ε of silicon dioxide is 9.0. r The value is 3.9; the charge volume density distribution ρ is calculated using the device physical model and doping concentration distribution; the boundary potential is set by simulating the voltage distribution under the device's operating conditions.

[0079] This Poisson equation, based on electrostatic field theory, considers the discontinuity of dielectric constant at interfaces between different materials, accurately reflecting the electric field distribution in complex geometric structures. The gradient operator in the equation characterizes the spatial rate of change of the electric field, the dielectric constant term considers the influence of different materials on the electric field, and the charge density term characterizes the contribution of space charge to the electric field. Compared to traditional one-dimensional or two-dimensional simulations, three-dimensional solutions can more accurately capture edge and corner effects, providing a theoretical basis for the optimization of field plate structures.

[0080] The thermal resistance calculation in step S02 involves the heat conduction equation, which is expressed as follows:

[0081]

[0082] In the formula, R th t is the thermal resistance value, in square cm·degree Celsius / watt; t is the thickness of the silver sintered layer, in μm; k is the thermal conductivity of the silver sintered layer, in watts / meter·Kelvin; A is the chip contact area, in square cm; R int1 R represents the thermal resistance at the interface between the chip and the silver sintered layer, expressed in square cm·degrees Celsius / watt. int2 R represents the thermal resistance at the interface between the silver sintered layer and the ceramic substrate, expressed in square cm·degrees Celsius / watt. sp is the thermal resistance coefficient of the heat dissipation path, with units of square cm·degree Celsius / watt; n is the number of parallel heat channels, dimensionless.

[0083] Formula for calculating interfacial thermal resistance:

[0084]

[0085] In the formula, R int γ is the interfacial thermal resistance, in square cm·°C / W; γ is the interfacial roughness correlation coefficient, dimensionless, ranging from 0.5 to 2.0; P is the interfacial pressure, in megapascals; k1 and k2 are the thermal conductivity of the two materials, in watts / m·Kelvin; ρ1 and ρ2 are the densities of the two materials, in kilograms / m³; c1 and c2 are the specific heat capacities of the two materials, in joules / kg·Kelvin.

[0086] The parameter acquisition method is as follows: the thickness t of the silver sintered layer is obtained by cross-sectional scanning electron microscopy; the thermal conductivity k is measured by laser flare method, and the specific steps include: (1) coating the sample surface with a graphite-enhanced absorption layer; (2) irradiating the front surface of the sample with a pulsed laser; (3) measuring the temperature change curve of the back surface with time using an infrared detector; (4) calculating the thermal conductivity according to the formula k=α·ρ·c, where α is the thermal diffusivity. Interface thermal resistance R int1 and R int2 The thermal resistance coefficient R of the heat dissipation path is obtained through transient thermal resistance testing. sp The results were obtained through simulation calculations using finite element thermal analysis software.

[0087] This thermal resistance calculation equation considers both conductive and interfacial thermal resistance in multilayer structures, conforming to the basic theory of heat conduction. It calculates the total thermal resistance using a layered, cumulative approach. The thickness-to-thermal conductivity ratio term characterizes the pure conductive thermal resistance, while the interfacial thermal resistance term characterizes the contact thermal resistance at the material interfaces. The heat dissipation path coefficient considers the three-dimensional thermal diffusion effect. The reciprocal relationship reflects the thermal resistance reduction effect of parallel heat channels, consistent with actual physical phenomena. The advantage of this equation lies in its comprehensive consideration of both material bulk and interfacial factors, enabling accurate prediction of the thermal conductivity performance of complex structures.

[0088] The calculation of the multilayer field plate effect in step S03 involves the field plate electric field modulation equation, which is specifically expressed as follows:

[0089]

[0090] In the formula, E peak E0 is the peak electric field intensity after modulation by the field plate, in volts / cm; E0 is the peak electric field intensity without the field plate, in volts / cm; β is the field plate efficiency coefficient, dimensionless, ranging from 0.3 to 0.6; L FP L is the extension length of the field plate, in μm. GD The distance from source to drain is in μm; t die T represents the thickness of the dielectric layer, in μm. FP α is the thickness of the field plate metal, in μm; α is the thickness influence index, dimensionless, ranging from 0.2 to 0.5; δ is the position correction coefficient, dimensionless, ranging from 0.1 to 0.3; x is the distance from the gate edge to the measurement point, in μm.

[0091] Calculation of effective electric field distribution in multilayer field plate structures:

[0092]

[0093] In the formula, E eff (x, y, z) represents the effective electric field intensity distribution function considering the multilayer field plate structure, with units of volts / cm; E i (x, y, z) represents the electric field intensity distribution function independently contributed by the i-th layer of the field plate, in volts / cm; w i Let be the weighting coefficient of the i-th layer field plate, dimensionless, satisfying . d i (x, y, z) represents the shortest distance from the spatial point (x, y, z) to the i-th layer of the field plate, in μm; λ i denoted as the characteristic length of electric field attenuation of the i-th field plate, in μm; n is the number of field plate layers.

[0094] The parameter acquisition method is as follows: the peak electric field intensity E0 without the field plate is obtained through finite element simulation; the field plate efficiency coefficient β is determined by a combination of experimental verification and theoretical calculation. The specific steps include: (1) preparing comparative samples with different field plate lengths; (2) measuring the breakdown voltage of each sample; (3) determining the β value through curve fitting. Field plate extension length L FP Source-drain distance L GD The thickness influence index α was determined through mask design. The position correction coefficient δ was obtained through parametric scanning simulation, and the result was obtained by calibrating the measured electric field distribution with the theoretical model.

[0095] The electric field modulation equation for this field plate is constructed based on the theories of electric field concentration effect and edge passivation, considering the comprehensive influence of field plate length, thickness ratio, and location on the electric field distribution. Fractional terms in the equation characterize the field plate extension coverage effect, power terms reflect the nonlinear influence of the thickness ratio on the modulation effect, and sinusoidal terms consider the special effects of the field plate edge location. The multi-layer field plate superposition equation considers the electric field shielding effect and distance attenuation characteristics of each field plate layer, using an exponential attenuation function to describe the far-field effect, and weighting coefficients reflect the relative importance of different field plate layers. Compared with the traditional single-layer field plate model, this equation system can more accurately describe the electric field modulation effect of complex multi-layer field plate structures.

[0096] The high dielectric constant resin layer design in step S04 involves a dielectric layer breakdown model, specifically represented as follows:

[0097]

[0098] In the formula, E br E represents the actual breakdown field strength of the dielectric layer, expressed in kV / mm. br0 t represents the intrinsic breakdown field strength of the dielectric layer under standard conditions, in kV / mm; t represents the actual thickness of the dielectric layer, in μm; t0 represents the reference thickness, with a value of 1 μm; γ represents the thickness effect exponent, dimensionless, ranging from 0.2 to 0.4; T represents the operating temperature, in Kelvin; T0 represents the reference temperature, with a value of 298 Kelvin; T c η is the temperature characteristic constant, in Kelvin, ranging from 50 to 100 Kelvin; η is the humidity sensitivity coefficient, dimensionless, ranging from 0.05 to 0.15; RH is the relative humidity, in percentage; RH0 is the reference relative humidity, taken as 50%; ξ is the impurity influence coefficient, dimensionless, ranging from 0.8 to 1.2; f imp This is a dimensionless normalization function for impurity concentration, ranging from 0 to 0.5.

[0099] High dielectric constant resin layer thickness design model:

[0100]

[0101] In the formula, t min V represents the minimum safe thickness of the high dielectric constant resin layer, in μm. max This is the maximum operating voltage, measured in volts; σ V K is the voltage fluctuation coefficient, dimensionless, ranging from 0.1 to 0.2. sf The safety factor is dimensionless and ranges from 1.5 to 2.5; E br σ is the dielectric breakdown field strength, expressed in kV / mm; E t is the material breakdown strength dispersion coefficient, dimensionless, ranging from 0.1 to 0.15;add This is an additional thickness margin, in μm, ranging from 5 to 10 μm.

[0102] The parameter is obtained as follows: the intrinsic breakdown field strength E of the dielectric layer under standard conditions. br0 The breakdown test was conducted, and the specific steps included: (1) preparing a standard thickness sample; (2) placing the sample in a constant temperature and humidity environment; (3) applying a slowly increasing voltage until breakdown; and (4) recording the breakdown voltage and calculating the breakdown field strength. The thickness effect index γ was obtained by comparing the breakdown field strength of samples with different thicknesses. The temperature characteristic constant T... c The humidity sensitivity coefficient η and the impurity influence coefficient ξ were obtained through orthogonal experimental design, that is, the breakdown strength was tested under different temperature, humidity and impurity concentration conditions, and the values ​​of each parameter were determined by multiple regression analysis.

[0103] This dielectric layer breakdown model is constructed based on the physical mechanism of dielectric breakdown, considering multiple influencing factors such as thickness, temperature, humidity, and impurities. The power terms in the equations reflect the nonlinear relationship between the breakdown field strength and thickness, the exponential terms describe the influence of temperature on dielectric properties, the logarithmic terms characterize the effects of humidity, and the linear terms reflect the influence of impurity concentration. The thickness design model is based on worst-case analysis, comprehensively considering voltage fluctuations, material dispersion, and safety margins to ensure sufficient safety margins even under extreme conditions. The advantage of this system of equations lies in its integration of various environmental factors and material properties, enabling it to guide dielectric layer thickness optimization in practical engineering designs.

[0104] The electric field tolerance assessment in step S06 involves a leakage current evolution model, specifically represented as follows:

[0105]

[0106] In the formula, I leak (t) represents the surface leakage current at time t, in amperes; I0 represents the initial leakage current, in amperes; A represents the rapid aging factor, dimensionless, ranging from 0.01 to 0.05; τ1 represents the characteristic time of the rapid process, in hours, ranging from 10 to 20 hours; B represents the slow aging factor, dimensionless, ranging from 0.001 to 0.01; τ2 represents the reference time of the slow process, in hours, with a value of 168 hours; n represents the aging time exponent, dimensionless, ranging from 0.3 to 0.7; E represents the actual electric field strength, in volts per centimeter; E th E0 is the threshold electric field at which leakage current increases significantly, measured in volts per centimeter; E0 is the characteristic constant of the electric field, measured in volts per centimeter.

[0107] Criteria for electric field tolerance assessment:

[0108]

[0109] In the formula, ΔI max I0 is the maximum change in leakage current, in amperes; I0 is the initial leakage current, in amperes; λ crit The critical rate of change threshold is dimensionless and has a value of 0.05.

[0110] The parameter acquisition method is as follows: the initial leakage current I0 is obtained by measuring the device characteristic tester under standard conditions. The rapid aging coefficient A, the rapid process characteristic time τ1, the slow aging coefficient B, and the aging time exponent n are obtained by curve fitting of historical test data. The specific steps include: (1) collecting a large amount of data on the leakage current of the device under high electric field conditions over time; (2) fitting the leakage current model using the nonlinear least squares method; (3) extracting the best fitting value of each parameter and its statistical distribution. Threshold electric field E th The characteristic constant of the electric field, E0, is determined by gradient electric field testing, that is, by measuring the leakage current under different electric field intensities and analyzing the functional relationship between the current and the electric field.

[0111] This leakage current evolution model is built upon dielectric aging and charge trapping theories, considering the dual effects of both fast and slow processes. The exponential term in the equation characterizes the rapid trap filling process, the power term describes the slow interface degradation process, and the electric field exponential term reflects the nonlinear dependence of the leakage current on the electric field strength. The model considers the accelerating effect of the electric field strength on the aging process, consistent with actual physical phenomena. The judgment criterion is based on the relative rate of change of the leakage current, setting a clear acceptable range, facilitating quality control in engineering practice. Compared with traditional fixed-time-point detection methods, this model can comprehensively capture the dynamic evolution trend of the leakage current and more accurately assess the long-term reliability of devices.

[0112] The high-accelerated life test in step S08 involves a failure acceleration model, specifically represented as follows:

[0113]

[0114] In the formula, AF is the acceleration factor, which is dimensionless; E a The activation energy is the temperature, expressed in electron volts (eV), ranging from 0.5 to 1.2 eV; k is the Boltzmann constant, with a value of 8.617 × 10⁻⁶. -5 Electron volts / Kelvin; T use Normal operating temperature, unit: Kelvin; T test Temperature is measured in Kelvin (V). test This is a test voltage, measured in volts (V). use The voltage used is measured in volts; γ is the voltage acceleration index, dimensionless, ranging from 2.5 to 3.5; RH testTo measure relative humidity, the unit is percentage; RH use The values ​​are relative humidity, expressed as a percentage; β is the humidity acceleration index, dimensionless, ranging from 2.0 to 3.0; ΔH is the humidity-temperature synergistic effect parameter, expressed in electron volts, ranging from 0.01 to 0.05 electron volts.

[0115] Lifetime prediction model:

[0116]

[0117] In the formula, t life To predict device lifetime under actual operating conditions, the unit is hours; t test Failure time under high accelerated life testing conditions, in hours; AF is the acceleration factor, dimensionless; SF i is the reduction factor for the i-th type of additional stress, which is dimensionless; m is the number of additional stress types considered.

[0118] The parameter acquisition method is as follows: temperature activation energy E a The lifetime test results were obtained through tests at different temperatures. The specific steps included: (1) conducting lifetime tests under different temperature conditions; (2) recording the average failure time at each temperature; and (3) plotting ln(t). fail (4) The slope was determined by linear regression, and the activation energy was calculated. The voltage acceleration index γ and the humidity acceleration index β were obtained by variable control under the condition of fixing other parameters using a similar method. The humidity-temperature synergistic effect parameter ΔH was determined by orthogonal experimental design and variance analysis. The additional stress reduction coefficient SF i Determined through historical data analysis and expert experience.

[0119] This failure acceleration model is a comprehensive extension of the Arrhenius equation, the inverse power law, and the Peck humidity model (temperature and humidity acceleration model), considering the triple stress factors of temperature, voltage, and humidity, and their interactions. The exponential terms in the equation reflect the Arrhenius relationship between the chemical reaction rate and temperature, the power terms describe the acceleration effects of the electric field and humidity, and the interaction terms characterize the synergistic effect of humidity and temperature. Compared with traditional single-stress models, this model more comprehensively considers multiple stresses and synergistic effects, enabling more accurate prediction of device lifetime under actual operating conditions. The lifetime prediction model further considers other additional stress factors and improves prediction accuracy through reduction factors.

[0120] The high electric field stress model in step S10 involves electromechanical coupling equations, specifically expressed as follows:

[0121]

[0122] In the formula, σij (r) is the total stress tensor at spatial location r, in Pascals; is the mechanical stress tensor, measured in Pascals; Let be the Maxwell stress tensor, with units of Pascals; i and j are tensor indices, taking values ​​of 1, 2, and 3, representing the x, y, and z directions, respectively.

[0123] Maxwell's stress tensor calculation formula:

[0124]

[0125] In the formula, ε0 is the vacuum permittivity, with a value of 8.85 × 10⁻⁶. -12 Farads / meters; ε r (r) is the relative permittivity of the material at position r, which is dimensionless; E i (r) and E j (r) represents the electric field intensity tensor component at location r, in volts per meter; δ ij P is the Kronecker delta function, which has a value of 1 when i = j and 0 otherwise; k (r) represents the polarization intensity tensor component at position r, in units of coulombs per square meter.

[0126] Prediction model for critical breakdown electric field intensity at the interface:

[0127]

[0128] In the formula, denoted as the critical breakdown electric field strength at interface location r, in volts per cm. The intrinsic breakdown field strength at the interface under stress-free conditions is expressed in volts per centimeter; α stress σ is the stress sensitivity coefficient, dimensionless, ranging from 0.1 to 0.3; nn (r) represents the interface normal stress, in Pascals; σ crit α is the critical stress, measured in Pascals; curv κ(r) is the curvature sensitivity coefficient, dimensionless, ranging from 0.2 to 0.4; κ(r) is the curvature at interface position r, in units of 1 / μm; t die W represents the thickness of the dielectric layer, in μm. trap (r) represents the trap energy density at position r, in joules per cubic meter; W0 represents the reference energy density, in joules per cubic meter.

[0129] The parameter is obtained using the mechanical stress tensor. Obtained through finite element analysis, taking into account factors such as thermal expansion coefficient mismatch and residual stress. Electric field intensity tensor E i(r) Obtained through electric field distribution simulation in step S01. Polarization intensity P k (r) via formula P k (r)=ε0(ε r (r)-1)E k (r) Calculation. Intrinsic breakdown field strength at the interface under stress-free conditions. Obtained through special sample testing, the specific steps include: (1) preparing stress-relieving interface samples; (2) conducting breakdown tests in a controlled environment; and (3) recording the breakdown voltage and calculating the breakdown field strength. The stress sensitivity coefficient α stress and curvature sensitivity coefficient α curv The trap energy density W was determined using a combination of parameter scanning and experimental verification. trap (r) was obtained by measurement using a deep-level transient spectrometer.

[0130] This electromechanical coupling model is constructed based on Maxwell's stress theory induced by an electric field and the mechanical properties of material interfaces, considering the combined effects of multiple factors such as electric field distribution, material polarization, interfacial stress, and microstructure. The stress tensor superposition term in the model reflects the independent superposition effect of mechanical stress and electric field stress, while the Maxwell stress tensor formula considers the force exerted by the electric field on the medium. The interfacial critical breakdown model comprehensively considers the influence of stress state, geometric curvature, and trap density on the interfacial breakdown strength. Compared with traditional methods that only consider electric field strength, this model can more accurately predict the breakdown behavior at the material interface in practical devices, providing theoretical guidance for the design of micro / nano channel structures.

[0131] The main equations involved in the electric field distribution and reliability prediction model in step S11 include an upper-level electric field distribution model and a lower-level material reliability model. The upper-level electric field distribution model is based on a graph neural network structure, and the key message passing equation is specifically represented as follows:

[0132]

[0133] In the formula, Let i be the feature vector of node i in the l-th layer of the network; Let be the feature vector of node i in the (l+1)th layer of the network; φ is the node feature update function, which is usually implemented using a multilayer perceptron. Let c be the set of neighboring nodes of node i; ij ψ is a normalization constant, typically taken as the square root of the number of neighbors; ψ is the message generation function, usually implemented using a multilayer perceptron; e ij The edge feature vector between node i and node j contains material interface information.

[0134] The lower-level model for material reliability is based on a long short-term memory network with a hybrid attention mechanism. The key attention calculation equation is specifically expressed as follows:

[0135]

[0136] In the formula, α i，t e represents the weight of the i-th attention head at time step t; i，t v is the energy value of the i-th attention head at time step t; a W a U a and b a For learnable network parameters; s t-1 The hidden state of the previous time step; h i，t Let be the feature representation of the i-th attention head at time step t.

[0137] The coupling equations of the two models:

[0138] f coupling (G, X, t) = λ1f GNN (G, X) + λ2f LSTM (f GNN (G,X),t)+λ3f GNN (G, f) LSTM (f GNN (G, X), t-1);

[0139] In the formula, f coupling is the output function of the coupled model; G is a graph representing the geometry and material distribution of the gallium nitride chip; X is the input feature matrix, containing operating condition parameters; t is the time step; f GNN For graph neural network functions; f LSTM λ1, λ2, and λ3 are the long short-term memory network functions; λ1, λ2, and λ3 are the weight coefficients, satisfying λ1 + λ2 + λ3 = 1.

[0140] The parameter acquisition method is as follows: the parameters of the graph neural network and long short-term memory network are learned through a data-driven approach. First, a training dataset containing 5000 samples is constructed, each sample including the geometric parameters, material parameters, corresponding electric field distribution, and failure data of the gallium nitride chip. Then, data augmentation is performed by randomly perturbing the geometric and material parameters, expanding the dataset to 15000 samples. The training set is used to optimize the network parameters, and the backpropagation algorithm is employed to minimize the prediction error. The optimal values ​​of the weight coefficients λ1, λ2, and λ3 are determined using a grid search method, that is, different combinations are tried in the range [0, 1] with a step size of 0.1, and the combination with the best performance on the validation set is selected.

[0141] Compared to existing technologies, this electric field distribution and reliability prediction model integrates the advantages of graph neural networks and long short-term memory networks, enabling it to simultaneously process spatial structure information and time-series data. The graph neural network captures the mapping relationship between geometric structure and electric field distribution through a message-passing mechanism, while the long short-term memory network captures the temporal characteristics of the failure process through an attention mechanism. The coupling equations enable mutual feedback and information exchange between the two sub-models. Compared to traditional purely statistical models or single neural network models, this model can more accurately predict the long-term reliability of complex gallium nitride chips, providing theoretical guidance for design optimization.

[0142] Specifically, the principle of this invention is based on the innovative integration of electric field engineering theory, high-performance materials science, and intelligent prediction models. Fundamentally, the reliability problem of gallium nitride power devices under high voltage stems primarily from localized overstress caused by uneven electric field distribution. This invention addresses this problem through a multi-dimensional and multi-layered comprehensive technical solution.

[0143] First, this invention utilizes the principles of electric field engineering to accurately identify high electric field regions in devices through three-dimensional electric field distribution simulation, which is the premise and foundation for solving the problem. For the identified high electric field regions, a multilayer field plate structure and a micro / nano channel structure are designed and implemented. These two structural designs fundamentally alter the electric field distribution characteristics. The multilayer field plate structure, by increasing the radius of curvature at the electrode edges, expands and disperses the originally concentrated high electric field regions, effectively reducing local electric field intensity peaks. The micro / nano channel structure, by forming a micro-groove array on the surface, creates a local electric field buffer zone, breaking the continuity of electric field lines and suppressing the formation of electric field intensity peaks. These two structural designs, based on the principle of electric field interaction, achieve a uniform electric field distribution through precise control of geometry and material interfaces.

[0144] Secondly, this invention employs a high-performance material system to enhance the overall performance of the packaging structure. Compared to traditional solders, the silver sintering process exhibits lower thermal resistance, efficiently conducting heat generated by the chip and preventing performance degradation due to heat accumulation. A high-dielectric-constant resin layer covers high-electric-field regions, and its high breakdown strength provides effective electrical insulation protection for the device. A siloxane-modified polyimide insulating coating combines heat resistance and hydrophobicity, preventing electrical performance degradation in humid and hot environments. The selection and application of these materials are based on materials science theory, constructing a multi-layered protective barrier to address the specific needs of gallium nitride devices operating in high-voltage and high-temperature environments.

[0145] Third, this invention innovatively constructs a deep learning-based electric field distribution and reliability prediction model, elevating traditional empirical design methods to a data-driven intelligent prediction method. This model employs a hierarchical architecture, with the upper-level model capturing the mapping relationship between geometry and electric field distribution, and the lower-level model predicting the failure behavior of materials under different stress conditions. Through extensive data training and physical constraints, the model can accurately predict the expected lifespan and failure probability of devices, providing scientific guidance for packaging design. This data-driven approach combined with a physical model breaks through the limitations of traditional empirical design, achieving quantitative assessment and accurate prediction of packaging reliability.

[0146] In summary, this invention optimizes the electric field distribution through electric field engineering design, improves packaging quality through high-performance materials, and guides design optimization through intelligent predictive models. These three elements work together to form a complete technical solution that solves the reliability problem of gallium nitride power semiconductor devices in high-voltage operating environments.

[0147] The following provides a specific embodiment 1 of the present invention, and the specific implementation of each step in this embodiment 1 is described in detail below.

[0148] The specific implementation of step S01 involves constructing a three-dimensional geometric model of the gallium nitride (GaN) chip using finite element analysis software. This model includes the entire structure, including the GaN epitaxial layer, channel layer, field plate electrodes, source, drain, and gate. First, the dielectric constants of each material are input, such as 9.0 for GaN, 3.9 for silicon dioxide, and 7.5 for silicon nitride. The mesh density is set to at least 10 mesh points per μm in the high electric field region and at least 3 mesh points per μm in the low electric field region. Then, under different voltage conditions, the potential distribution is solved using the Poisson equation, and the three-dimensional electric field distribution is obtained through the potential gradient calculation. The specific expression of the Poisson equation is as follows:

[0149]

[0150] In the formula, ε is the gradient operator; φ is the electric potential field function, in volts; r ε0 is the relative permittivity of the material, dimensionless; ε0 is the vacuum permittivity, with a value of 8.85 × 102. -12 Farads per meter; ρ is the charge volume density distribution function, with units of coulombs per cubic meter.

[0151] Under boundary conditions, the potential difference between the source and drain is expressed as:

[0152] φ DS =φ D -φ S =V DS ;

[0153] In the formula, φ Dφ is the drain potential, measured in volts. S V is the source potential, usually set to 0 volts; DS This is the source-drain voltage, measured in volts.

[0154] After solving the Poisson equation to obtain the potential distribution, the formula for calculating the electric field strength is:

[0155]

[0156] In the formula, This is the electric field intensity vector, with units of volts per meter.

[0157] The scalar value of electric field strength is calculated as follows:

[0158]

[0159] In the formula, E x E y E z These represent the components of the electric field intensity in the x, y, and z directions, respectively, with units of volts per meter.

[0160] For electric field strength exceeding 3×10 6 For regions with electric field strength of volts per centimeter (V / cm), the system employs an adaptive labeling algorithm for identification. These regions are typically located at the gate edge and field plate terminations. Based on this electric field distribution data, the electrode spacing is optimized through parameter scanning, set within the range of 20 to 30 μm. Simultaneously, the dielectric layer thickness is optimized to 3 to 5 μm, a thickness that ensures sufficient dielectric strength without excessively increasing thermal resistance. These parameters are determined by comparing the maximum electric field strength under different geometries. The ultimate optimization goal is to reduce the maximum electric field strength below the critical breakdown electric field while maintaining good device conduction characteristics.

[0161] The specific implementation of step S02 involves using a high thermal conductivity aluminum nitride ceramic material as the heat dissipation substrate. This material has a thermal conductivity of 170 to 220 W / m·Kelvin, significantly higher than that of traditional alumina ceramic. A three-layer metal plating of titanium / nickel / silver is deposited on the back of the gallium nitride chip, with thicknesses of 50 nm / 200 nm / 1000 nm, to enhance the bonding strength with the silver nanoparticle paste. The particle size of the silver nanoparticle paste is controlled within the range of 20 to 50 nm, with a solid content of 85% to 90%. Under vacuum conditions, the temperature is increased to 250 to 300 °C at a heating rate of 2 to 5 °C / min, and held for 30 to 45 minutes, causing the silver nanoparticles to sinter and form a dense silver interconnect layer. The thermal resistance is calculated using the heat conduction equation, specifically expressed as follows:

[0162]

[0163] In the formula, R tht is the thermal resistance value, in square cm·degree Celsius / watt; t is the thickness of the silver sintered layer, in μm; k is the thermal conductivity of the silver sintered layer, in watts / meter·Kelvin; A is the chip contact area, in square cm; R int1 R represents the thermal resistance at the interface between the chip and the silver sintered layer, expressed in square cm·degrees Celsius / watt. int2 R represents the thermal resistance at the interface between the silver sintered layer and the ceramic substrate, expressed in square cm·degrees Celsius / watt. sp is the thermal resistance coefficient of the heat dissipation path, with units of square cm·degree Celsius / watt; n is the number of parallel heat channels, dimensionless.

[0164] Formula for calculating interfacial thermal resistance:

[0165]

[0166] In the formula, R int γ is the interfacial thermal resistance, in square cm·°C / W; γ is the interfacial roughness correlation coefficient, dimensionless, ranging from 0.5 to 2.0; P is the interfacial pressure, in megapascals; k1 and k2 are the thermal conductivity of the two materials, in watts / m·Kelvin; ρ1 and ρ2 are the densities of the two materials, in kilograms / m³; c1 and c2 are the specific heat capacities of the two materials, in joules / kg·Kelvin.

[0167] After implementing this process, the thermal resistance of the heat conduction path formed between the chip and the substrate is less than 0.1 cm²·°C / W, which can effectively dissipate the heat generated by the device under high frequency and high power operating conditions, and prevent the device performance degradation and reliability decline caused by heat accumulation.

[0168] The specific implementation of step S03 involves fabricating a multilayer field plate structure using photolithography and metal deposition techniques. First, a silicon dioxide or silicon nitride dielectric layer with a thickness of 200 to 300 nanometers is deposited on the surface of a gallium nitride chip using plasma-enhanced chemical vapor deposition (PECVD). A pattern is formed by coating with photoresist, exposure, and development. Then, a stepped structure is formed on the dielectric layer using reactive ion etching (RIE), with the dielectric layer thickness decreasing sequentially at different steps. Subsequently, a titanium layer (50 to 80 nanometers thick), an aluminum layer (400 to 600 nanometers thick), a nickel layer (50 to 100 nanometers thick), and a gold layer (200 to 300 nanometers thick) are sequentially deposited using electron beam evaporation or magnetron sputtering techniques, forming a multilayer field plate electrode structure with a total thickness of 0.8 to 1.2 μm. The multilayer field plate effect is calculated using the field plate electric field modulation equation, specifically expressed as follows:

[0169]

[0170] In the formula, E peakE0 is the peak electric field intensity after modulation by the field plate, in volts / cm; E0 is the peak electric field intensity without the field plate, in volts / cm; β is the field plate efficiency coefficient, dimensionless, ranging from 0.3 to 0.6; L FP L is the extension length of the field plate, in μm. GD The distance from source to drain is in μm; t die t represents the thickness of the dielectric layer, in μm. FP α is the thickness of the field plate metal, in μm; α is the thickness influence index, dimensionless, ranging from 0.2 to 0.5; δ is the position correction coefficient, dimensionless, ranging from 0.1 to 0.3; x is the distance from the gate edge to the measurement point, in μm.

[0171] Calculation of effective electric field distribution in multilayer field plate structures:

[0172]

[0173] In the formula, E eff (x, y, z) represents the effective electric field intensity distribution function considering the multilayer field plate structure, with units of volts / cm; E i (x, y, z) represents the electric field intensity distribution function independently contributed by the i-th layer of the field plate, in volts / cm; w i Let be the weighting coefficient of the i-th layer field plate, dimensionless, satisfying . λ is the shortest distance from a spatial point (x, y, z) to the i-th layer of the field plate, in μm; i denoted as the characteristic length of electric field attenuation of the i-th field plate, in μm; n is the number of field plate layers.

[0174] The multilayer field plate structure extends from the source to the drain, with an extension length of 25% to 40% of the distance between the source and drain. This multilayer field plate structure effectively reduces the peak electric field intensity by increasing the radius of curvature of the electrode edges. Theoretically, it can reduce the peak electric field intensity by 30% to 50%, thereby significantly improving the breakdown voltage and reliability of the device.

[0175] The specific implementation of step S04 involves selecting a high dielectric constant resin material, such as polyaryletherketone or epoxy-modified polyimide, with a dielectric constant between 4.0 and 6.0 and a breakdown strength of not less than 500 kV / mm. First, the chip surface is subjected to plasma treatment to improve surface wettability and adhesion. Then, a high dielectric constant resin layer is precisely applied between the chip and the lead frame using precision dispensing equipment. The dispensing head temperature is controlled at 30 to 40°C, the dispensing pressure is 0.2 to 0.4 MPa, and the dispensing speed is 5 to 10 mm / s. The dielectric layer breakdown model is specifically represented as follows:

[0176]

[0177] In the formula, E br E represents the actual breakdown field strength of the dielectric layer, expressed in kV / mm. br0 t represents the intrinsic breakdown field strength of the dielectric layer under standard conditions, in kV / mm; t represents the actual thickness of the dielectric layer, in μm; t0 represents the reference thickness, with a value of 1 μm; γ represents the thickness effect exponent, dimensionless, ranging from 0.2 to 0.4; T represents the operating temperature, in Kelvin; T0 represents the reference temperature, with a value of 298 Kelvin; T c η is the temperature characteristic constant, in Kelvin, ranging from 50 to 100 Kelvin; η is the humidity sensitivity coefficient, dimensionless, ranging from 0.05 to 0.15; RH is the relative humidity, in percentage; RH0 is the reference relative humidity, taken as 50%; ξ is the impurity influence coefficient, dimensionless, ranging from 0.8 to 1.2; f imp This is a dimensionless normalization function for impurity concentration, ranging from 0 to 0.5.

[0178] High dielectric constant resin layer thickness design model:

[0179]

[0180] In the formula, t min V represents the minimum safe thickness of the high dielectric constant resin layer, in μm. max This is the maximum operating voltage, measured in volts; σ V K is the voltage fluctuation coefficient, dimensionless, ranging from 0.1 to 0.2. sf The safety factor is dimensionless and ranges from 1.5 to 2.5; E br σ is the dielectric breakdown field strength, expressed in kV / mm; E t is the material breakdown strength dispersion coefficient, dimensionless, ranging from 0.1 to 0.15; add This is an additional thickness margin, in μm, ranging from 5 to 10 μm.

[0181] After resin coating, pre-curing is performed at 60 to 80°C for 1 to 2 hours, followed by final curing at 150 to 180°C for 2 to 3 hours. The thickness of the cured high-dielectric-constant resin layer is controlled at 50 to 100 μm, with thickness uniformity deviation controlled within ±5%. This high-dielectric-constant resin layer completely covers the high electric field regions identified in step S01, ensuring that the electric field strength in these regions is reduced to a safe level. Furthermore, the addition of nano-alumina particles (at a content of 2% to 5%) to the resin further improves its thermal conductivity and mechanical strength, reduces the coefficient of thermal expansion, and decreases the risk of failure caused by thermal stress.

[0182] The specific implementation of step S05 involves selecting an epoxy molding compound with an ion content of less than 1 part per 10 million, achieving a temperature cycling reliability level of Level 3 in JEDEC standard J-STD-020D, and a glass transition temperature higher than 150°C. First, the mold is preheated under vacuum at 80-100°C for 60-90 minutes to completely remove moisture and gases. Then, the epoxy molding compound is preheated to 90-110°C to reduce viscosity. Vacuum injection molding is then performed at 120-150°C and a pressure of 5-8 MPa. During injection, the vacuum level is maintained at no less than 10 Pascals, and the injection speed is controlled at 5-10 cm / s. After injection, the molding compound is cured in stages within the mold: first, it is held at 150-170°C for 1-2 hours, then at 180-200°C for 2-3 hours, and finally slowly cooled to room temperature at a rate not exceeding 2°C / minute. This multi-stage curing process effectively reduces internal stress and prevents bubbles and delamination during encapsulation. After curing, ultrasonic scanning and X-ray inspection are used to evaluate the encapsulation quality, ensuring that the encapsulation is free of voids, cracks, and delamination, and that the contact interfaces are well bonded.

[0183] The specific implementation of step S06 involves constructing a high-voltage electric field withstand test platform. This platform includes a high-precision voltage source (accuracy better than 0.1%), a micro-current measurement system (accuracy reaching the nanoampere level), and a constant temperature control system (temperature fluctuation controlled within ±0.5℃). First, the packaged gallium nitride chip is stabilized at an ambient temperature of 25±2℃. The voltage is then gradually applied to 120% of the rated operating voltage, with the voltage rise rate controlled at 1% of the rated voltage per second. After reaching the target voltage, a constant voltage state is maintained for 168 hours (7 days), during which the surface leakage current value is recorded every 6 hours. The leakage current evolution model is specifically represented as follows:

[0184]

[0185] In the formula, I leak (t) represents the surface leakage current at time t, in amperes; I0 represents the initial leakage current, in amperes; A represents the rapid aging factor, dimensionless, ranging from 0.01 to 0.05; τ1 represents the characteristic time of the rapid process, in hours, ranging from 10 to 20 hours; B represents the slow aging factor, dimensionless, ranging from 0.001 to 0.01; η2 represents the reference time of the slow process, in hours, with a value of 168 hours; n represents the aging time exponent, dimensionless, ranging from 0.3 to 0.7; E represents the actual electric field strength, in volts per centimeter; E th E0 is the threshold electric field at which leakage current increases significantly, measured in volts per centimeter; E0 is the characteristic constant of the electric field, measured in volts per centimeter.

[0186] Criteria for electric field tolerance assessment:

[0187]

[0188] In the formula, ΔI max I0 is the maximum change in leakage current, in amperes; I0 is the initial leakage current, in amperes; λ crit The critical rate of change threshold is dimensionless and has a value of 0.05.

[0189] During the test, the relative humidity was controlled within the range of 40% to 60% to eliminate the influence of humidity. After the test, the trend of leakage current over time was analyzed to ensure that its change did not exceed 5% of the original value. If the leakage current change exceeded the threshold, the electrode structure and dielectric layer quality in the high electric field region needed to be checked, and steps S03 and S04 needed to be optimized and adjusted. This test aims to verify the stability of the packaging structure under long-term high electric field stress and to evaluate the electric field distribution at the electrode edges and the performance of the dielectric material.

[0190] The specific implementation method of step S07 is the same as described above, and will not be repeated in detail here.

[0191] The specific implementation of step S08 involves using a high-acceleration lifetime testing system conforming to JEDEC standard JESD22-A110, which has a temperature control accuracy of ±0.5℃ and a humidity control accuracy of ±2%. The packaged gallium nitride chip is placed in the test chamber, with the ambient temperature set at 125℃ and the relative humidity at 85%. Before testing, the chip is pretreated by baking at 60℃ for 24 hours to remove adsorbed moisture. After the test begins, 80% of the rated voltage is applied between the drain and source of the chip, and the gate voltage is set to a turn-off state below the threshold voltage. The failure acceleration model is specifically represented as follows:

[0192]

[0193] In the formula, AF is the acceleration factor, which is dimensionless; E a The activation energy is the temperature, expressed in electron volts (eV), ranging from 0.5 to 1.2 eV; k is the Boltzmann constant, with a value of 8.617 × 10⁻⁶. -5 Electron volts / Kelvin; T use Normal operating temperature, unit: Kelvin; T test Temperature is measured in Kelvin (V). test This is a test voltage, measured in volts (V). use The voltage used is measured in volts; γ is the voltage acceleration index, dimensionless, ranging from 2.5 to 3.5; RH test To measure relative humidity, the unit is percentage; RH useThe values ​​are relative humidity, expressed as a percentage; β is the humidity acceleration index, dimensionless, ranging from 2.0 to 3.0; ΔH is the humidity-temperature synergistic effect parameter, expressed in electron volts, ranging from 0.01 to 0.05 electron volts.

[0194] Lifetime prediction model:

[0195]

[0196] In the formula, t life To predict device lifetime under actual operating conditions, the unit is hours; t test Failure time under high accelerated life testing conditions, in hours; AF is the acceleration factor, dimensionless; SF i is the reduction factor for the i-th type of additional stress, which is dimensionless; m is the number of additional stress types considered.

[0197] The test lasted 1000 hours, with a high-precision source meter recording the leakage current value hourly, achieving a current measurement resolution better than 10 nanoamps. After the test, the leakage current versus time curve was plotted, and the curve slope and abrupt change points were analyzed to identify potential failure mechanisms such as electrode migration, dielectric breakdown, or interface degradation. Simultaneously, scanning electron microscopy and energy dispersive spectroscopy were used to examine the chip surface morphology and composition changes, verifying the stability of the packaging structure under the triple stress of high temperature, high humidity, and high voltage.

[0198] The specific implementation method of step S09 is the same as described above, and will not be repeated in detail here.

[0199] The specific implementation of step S10 is based on the three-dimensional electric field distribution simulation results of step S01, constructing a high electric field stress model. This model integrates Maxwell's stress tensor theory and the finite element analysis method to calculate the mechanical stress distribution caused by the electric field. The electro-mechanical coupling equation is specifically expressed as follows:

[0200]

[0201] In the formula, σ ij (r) is the total stress tensor at spatial location r, in Pascals; is the mechanical stress tensor, measured in Pascals; Let be the Maxwell stress tensor, with units of Pascals; i and j are tensor indices, taking values ​​of 1, 2, and 3, representing the x, y, and z directions, respectively.

[0202] Maxwell's stress tensor calculation formula:

[0203]

[0204] In the formula, ε0 is the vacuum permittivity, with a value of 8.85 × 10⁻⁶. -12Farads / meters; ε r (r) is the relative permittivity of the material at position r, which is dimensionless; E i (r) and E j (r) represents the electric field intensity tensor component at location r, in volts per meter; δ ij P is the Kronecker delta function, which has a value of 1 when i = j and 0 otherwise; k (r) represents the polarization intensity tensor component at position r, in units of coulombs per square meter.

[0205] Prediction model for critical breakdown electric field intensity at the interface:

[0206]

[0207] In the formula, denoted as the critical breakdown electric field strength at interface location r, in volts per cm. The intrinsic breakdown field strength at the interface under stress-free conditions is expressed in volts per centimeter; α stress σ is the stress sensitivity coefficient, dimensionless, ranging from 0.1 to 0.3; nn (r) represents the interface normal stress, in Pascals; σ crit α is the critical stress, measured in Pascals; curv κ(r) is the curvature sensitivity coefficient, dimensionless, ranging from 0.2 to 0.4; κ(r) is the curvature at interface position r, in units of 1 / μm; t die W represents the thickness of the dielectric layer, in μm. trap (r) represents the trap energy density at position r, in joules per cubic meter; W0 represents the reference energy density, in joules per cubic meter.

[0208] First, the electric field strength exceeds 2.5 × 10⁻⁶. 6Regions with a voltage / cm² were identified as high electric field stress areas. Then, a focused ion beam system equipped with a gallium ion source was used, with an accelerating voltage of 30 kEV and an adjustable beam current ranging from 10 picoamps to 10 nanoamps. In the high electric field region, an automated patterning algorithm was employed to design the micro / nano channel structure layout, using the gate spacing (i.e., the distance between gates) as a reference. The focused ion beam formed parallel channel structures in the high electric field region, with channel depths controlled at 1–2 μm, widths at 0.5–1 μm, and adjacent channel spacing at 5–10 μm. During etching, the ion beam current density was controlled at 0.1–0.5 picoamps / μm², and the etching rate at approximately 0.1 μm / min to ensure etching quality and dimensional accuracy. These micro / nano channels reduced the peak electric field intensity by altering the surface electric field distribution; theoretical calculations showed that this reduction could reach 15%–25%. Meanwhile, the channel structure increases the surface area, improves heat dissipation, and acts as a charge trap to capture free surface charges, forming a local electric field buffer, suppressing electric field concentration, and improving the stability and reliability of the device under high voltage operating conditions.

[0209] The specific implementation of step S11 involves constructing an electric field distribution and reliability prediction model based on the gallium nitride chip's geometric parameters, material parameters, electric field distribution data, and surface leakage current data obtained in the preceding steps. This model consists of an upper-level electric field distribution model and a lower-level material reliability model. The upper-level electric field distribution model is based on a graph neural network structure, and its message passing equation is specifically expressed as follows:

[0210]

[0211] In the formula, Let r be the feature vector of node r in the l-th layer of the network; Let be the feature vector of node i in the (l+1)th layer of the network; φ is the node feature update function, which is usually implemented using a multilayer perceptron. Let c be the set of neighboring nodes of node i; ij ψ is a normalization constant, typically taken as the square root of the number of neighbors; ψ is the message generation function, usually implemented using a multilayer perceptron; e ij The edge feature vector between node i and node j contains material interface information.

[0212] The lower-level model for material reliability is based on a long short-term memory network with a hybrid attention mechanism. The specific expression of its attention calculation equation is as follows:

[0213]

[0214] In the formula, α i，t e represents the weight of the i-th attention head at time step t; i，t v is the energy value of the i-th attention head at time step t;a W a U a and b a For learnable network parameters; s t-1 The hidden state of the previous time step; h i，t Let be the feature representation of the i-th attention head at time step t.

[0215] The coupling equations of the two models:

[0216] f coupling (G, X, t) = λ1f GNN (G, X) + λ2f LSTM (f GNN (G,X),t)+λ3f GNN (G, f) LSTM (f GNN (G, X), t-1);

[0217] In the formula, f coupling is the output function of the coupled model; G is a graph representing the geometry and material distribution of the gallium nitride chip; X is the input feature matrix, containing operating condition parameters; t is the time step; f GNN For graph neural network functions; f LSTM λ1, λ2, and λ3 are the long short-term memory network functions; λ1, λ2, and λ3 are the weight coefficients, satisfying λ1 + λ2 + λ3 = 1.

[0218] To better understand and implement this invention, a specific application scenario of the invention is provided below as Example 2: Researchers used the gallium nitride power semiconductor device enhancement packaging method of this invention to fabricate a high-voltage gallium nitride power switching device for use in a fast charging system for electric vehicles. This application scenario requires the device to have a rated breakdown voltage of 1200V and a rated current of 25A, while maintaining stable operation within a wide temperature range of -40℃ to 125℃ and being able to withstand harsh temperature and humidity environments.

[0219] First, researchers conducted a three-dimensional electric field distribution simulation of a gallium nitride (GaN) epitaxial wafer. A complete three-dimensional geometric model was constructed using COMSOL Multiphysics software, including a 5.2 μm thick GaN epitaxial layer, a 1.8 μm thick AlGaN barrier layer, and source, drain, and gate electrode structures. During the simulation, the potential distribution was obtained by solving the Poisson equation, with the relative permittivity set to 9.0 for GaN, 8.6 for AlGaN, and 3.9 for the SiO2 dielectric layer. Simulation results showed that the electric field strength reached 3.78 × 10⁻⁶ at the gate edge region. 6The voltage (V / cm) is far greater than the critical breakdown electric field strength of gallium nitride (GaN) materials. Through parameter scanning optimization, the optimal structural parameters were determined to be 26 μm electrode spacing and 4.2 μm dielectric layer thickness, as shown in Table 1.

[0220] Table 1 Optimized electrode structure parameters

[0221] Structural parameters initial value Optimized value Improvement effect Gate-drain spacing 18μm 26μm Maximum electric field reduced by 22% Dielectric layer thickness 2.8μm 4.2μm Surface leakage current reduced by 35% Field plate extension length 3.5μm 8.2μm Electric field uniformity improved by 40%. Field plate edge curvature 0.5μm 2.1μm The peak value of the edge electric field is reduced by 28%.

[0222] Next, the researchers used an aluminum nitride ceramic substrate as the heat dissipation substrate, with a thermal conductivity of 185 W / m·K. Chip bonding was performed using a nano-silver sintering process; the average particle diameter of the silver nanoparticles was 35 nm, and the solid content was 87%. Under vacuum, the substrate was heated to 280 °C at a heating rate of 3 °C / min and held for 40 minutes, forming a 15 μm thick silver sintered layer. Transient thermal resistance testing showed that the chip-to-substrate thermal resistance was 0.072 cm⁻¹. 2 ·℃ / W, far lower than the 0.18cm of traditional solder joints. 2 ·℃ / W, as shown in Table 2:

[0223] Table 2 Comparison of thermal properties of different bonding processes

[0224]

[0225] Subsequently, researchers designed a three-layer field plate structure on the surface of a gallium nitride chip, consisting of titanium (70nm), aluminum (550nm), nickel (80nm), and gold (250nm) metal layers, with a total thickness of 0.95μm. The field plate structure extends from the source to the drain, with an extension length of 32% of the source-drain distance. Calculations based on the field plate electric field modulation equation show that this multilayer field plate structure reduces the peak electric field intensity from 3.78 × 10⁻⁶ to 3.95 μm. 6 V / cm decreased to 2.12×10 6 The electric field strength decreased by 43.9% (V / cm). Simultaneously, the electric field distribution became more uniform, and the edge electric field gradient decreased by 52%.

[0226] Between the chip and the lead frame, researchers applied a modified polyaryletherketone (POG) high-dielectric-constant resin layer with a dielectric constant of 5.2 and a breakdown strength of 625 kV / mm. The resin layer thickness was controlled to 85 μm using precision dispensing equipment, with thickness uniformity maintained within ±3.5%. The addition of 3.5% nano-alumina particles to the resin improved the thermal conductivity to 0.8 W / m·K while reducing the coefficient of thermal expansion to 22 ppm / ℃, as shown in Table 3.

[0227] Table 3 Performance parameters of high dielectric constant resin layers

[0228] Performance parameters numerical values Test methods Dielectric constant 5.2 Impedance analyzer @ 1MHz Breakdown strength 625kV / mm High voltage breakdown test thermal conductivity 0.8 W / m·K Laser flash method coefficient of thermal expansion 22ppm / ℃ Thermomechanical analyzer Glass transition temperature 218℃ Differential scanning calorimetry Volume resistivity <![CDATA[2.8×10 14 Ohm cm]]> High resistance meter

[0229] Primary encapsulation was performed using a low-ion-content epoxy molding compound, with a chloride ion content of only 5.2 ppm and a sodium ion content of 3.8 ppm. Encapsulation was carried out using a vacuum injection molding process at 135℃ and a pressure of 6.5 MPa to ensure no bubbles or delamination. X-ray inspection and ultrasonic scanning results showed no internal defects and good interface bonding.

[0230] Researchers conducted electric field withstand tests on the packaged gallium nitride chips, applying a high voltage of 1440V (120% of the rated voltage of 1200V) for 168 hours. The measured change in surface leakage current was only 3.2% of the original value, far below the 5% limit requirement. The test data conforms to the prediction of the surface leakage current evolution model, with a rapid aging factor A of 0.022, a slow aging factor B of 0.005, and an aging time exponent n of 0.42.

[0231] A siloxane-modified polyimide insulating coating with a thickness of 18 μm was applied to the outer layer of the chip and cured at 200 °C for 80 minutes. This coating achieved a contact angle of 112 degrees, exhibiting excellent moisture resistance. High-accelerated life testing was conducted for 1000 hours at 125 °C / 85% RH, during which 80% of the rated voltage (960 V) was applied. The leakage current variation curves recorded during the test are shown in Table 4.

[0232] Table 4 Leakage current variation data during high-accelerated life testing

[0233] Test duration (hours) Leakage current (nA) Relative rate of change (%) 0 58.2 0 100 62.4 7.2 200 65.3 12.2 300 67.1 15.3 400 68.5 17.7 500 69.4 19.2 600 70.2 20.6 700 70.8 21.6 800 71.2 22.3 900 71.5 22.9 1000 71.8 23.4

[0234] Thermal cycling tests were completed for 500 cycles within a temperature range of -40℃ to 150℃, with a heating rate of 15℃ / min and a cooling rate of 10℃ / min. The test results show that the package structure remained intact, without delamination or cracking. The changes in electrical parameters before and after the test were less than 10%, indicating that the package exhibits excellent thermomechanical stability.

[0235] Researchers used focused ion beam technology to form micro / nanochannel structures in a high-electric-field region. The channels are 1.5 μm deep, 0.8 μm wide, and 7.5 μm apart. This structure effectively reduces the peak surface electric field intensity and minimizes local electric field concentration. Scanning electron microscopy (SEM) observations show that the micro / nanochannel structures are uniformly distributed in the high-field region without damaging the main device structure. The final chip structure and some of its components are shown below. Figure 2-5 As shown; the heat dissipation direction of the chip is as follows Figure 6 As shown.

[0236] Finally, the device's performance was evaluated based on an electric field distribution and reliability prediction model. The graph neural network in the model contains four graph convolutional layers, each with 96 convolutional kernels; the long short-term memory network uses six attention heads, and the hidden layer dimension is 192. Prediction results show that under normal operating conditions (85℃, 60% RH, 90% of rated voltage), the device's expected lifespan exceeds 100,000 hours, and the failure probability is less than 0.1% over a 10-year service life.

[0237] Traditional gallium nitride (GaN) power device packaging methods primarily employ single-layer field plate structures and ordinary epoxy resin encapsulation. These methods lack specific structural optimization for high-electric-field regions and do not utilize high-thermal-conductivity silver sintering processes. These traditional methods are prone to device performance degradation and failure under high-temperature, high-humidity, and high-voltage environments, with mean time between failures (MTBF) typically below 30,000 hours and poor reliability under temperature cycling and high-humidity conditions. Traditional methods mainly rely on increasing safety margins to ensure reliability, such as lowering operating voltages or increasing design dimensions, which prevents the device from fully realizing its potential.

[0238] Compared to traditional methods, the enhanced packaging method provided by this invention optimizes structural parameters through three-dimensional electric field simulation, employs a multi-layer field plate structure to reduce peak electric field intensity, uses silver sintering to improve heat dissipation, forms micro-nano channel structures in high electric field regions to alleviate electric field concentration, and combines a high-dielectric-constant resin layer and a siloxane-modified polyimide outer layer for protection, significantly improving device reliability and lifespan. In particular, the design optimization method based on an electric field distribution and reliability prediction model realizes a shift from empirical design to theory-guided design, greatly improving product development efficiency.

[0239] It should be noted that the variables involved in this invention are explained in detail in Tables 5, 6, and 7 below.

[0240] Table 5. Variable Explanation Table (Part 1)

[0241]

[0242] Table 6. Variable Explanation Table (Part Two)

[0243]

[0244]

[0245] Table 7. Variable Explanation Table (Part 3)

[0246]

[0247]

[0248] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A packaging method of an enhanced gallium nitride power semiconductor device, characterized by, The method comprises the following sequential steps: simulating the three-dimensional electric field distribution of a gallium nitride chip, and optimizing the electrode spacing and dielectric layer thickness based on the simulation data; fixing one side of the gallium nitride chip on a heat dissipation substrate to form a heat conduction path; designing the surface electrode of the gallium nitride chip by using a multi-layer field plate structure; applying a high dielectric constant resin layer between the surface electrode opposite to the one side of the gallium nitride chip and a lead frame; performing primary packaging by using a low ion content epoxy molding compound; testing the electric field resistance of the packaged gallium nitride chip; coating a silicone modified polyimide insulating coating on the outer layer of the gallium nitride chip; and performing high acceleration life test and thermal cycle test. A micro-nano channel structure is formed on the high electric field area of the surface of the gallium nitride chip by using focused ion beam technology, the depth of the micro-nano channel structure is 1-2 μm, the width of the micro-nano channel structure is 0.5-1 μm, and the spacing of the micro-nano channel structure is 5-10 μm, a local electric field buffer zone is constructed to complete packaging, and an electric field distribution and reliability prediction model is used to calculate the expected service life and failure probability curve of the packaged gallium nitride chip.

2. The packaging method of the enhanced gallium nitride power semiconductor device according to claim 1, wherein The three-dimensional electric field distribution simulation comprises marking the area with an electric field intensity exceeding 3×10^6 volts / cm in the three-dimensional electric field distribution simulation result, and optimizing the electrode spacing to 20-30 μm and the dielectric layer thickness to 3-5 μm based on the three-dimensional electric field distribution simulation data.

3. The packaging method of the enhanced gallium nitride power semiconductor device according to claim 1, wherein The fixing of the gallium nitride chip on the heat dissipation substrate comprises fixing the gallium nitride chip on a heat dissipation substrate made of aluminum nitride ceramic material, using a silver sintering process to bond the chip at a temperature of 250-300 °C to form a heat conduction path with a thermal resistance value of less than 0.1 square cm·degree Celsius / watt.

4. The packaging method of the enhanced gallium nitride power semiconductor device according to claim 1, wherein The multi-layer field plate structure is formed by sequentially depositing titanium, aluminum, nickel and gold, the total thickness of the multi-layer field plate structure is 0.8-1.2 μm, and the extension length of the multi-layer field plate structure is 25%-40% of the distance from the source electrode to the drain electrode.

5. The packaging method of the enhanced gallium nitride power semiconductor device according to claim 1, wherein The breakdown strength of the high dielectric constant resin layer is not less than 500 KV / mm, the thickness of the high dielectric constant resin layer is 50-100 μm, and the high dielectric constant resin layer covers all high electric field areas.

6. The packaging method of the enhanced gallium nitride power semiconductor device according to claim 1, wherein The primary packaging by using a low ion content epoxy molding compound comprises performing vacuum injection molding process at a temperature of 120-150 °C and a pressure of 5-8 megapascals to ensure no bubbles and no delamination.

7. The packaging method of the enhanced gallium nitride power semiconductor device according to claim 1, wherein The electric field resistance test of the packaged gallium nitride chip comprises applying a voltage 20% higher than the rated working voltage for 168 hours, and measuring that the change amplitude of the surface leakage current is not more than 5% of the original value.

8. The packaging method of the enhanced gallium nitride power semiconductor device according to claim 1, wherein The thickness of the silicone modified polyimide insulating coating is 15-25 μm, the curing temperature is 180-220 °C, and the curing time is 60-90 minutes.

9. The packaging method of the enhanced gallium nitride power semiconductor device according to claim 1, wherein The electric field distribution and reliability prediction model is calculated based on the obtained geometric parameters, material parameters, electric field distribution data and surface leakage current data of the gallium nitride chip, and outputs the expected service life and failure probability curve of the gallium nitride chip.

10. The packaging method of the enhanced gallium nitride power semiconductor device according to claim 1, wherein The structure of the electric field distribution and reliability prediction model is a hierarchical deep learning framework composed of an upper layer model of electric field distribution and a lower layer model of material reliability. The electric field distribution upper model adopts a geometry structure perception module based on a graph neural network to extract physical structure features of a gallium nitride chip, and the material reliability lower model adopts a long short-term memory network with a hybrid attention mechanism to predict life evolution curves of the gallium nitride chip under different stress conditions.

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