TFT structure, manufacturing method, array substrate, display panel and display device

Abstract

The invention provides a TFT structure, a manufacturing method, an array substrate, a display panel and a display device, and belongs to the technical field of display, the TFT structure comprises a substrate, an active layer and a crystallization induction layer, the active layer is arranged on one side of the substrate in the thickness direction, the active layer comprises a first crystalline oxide and a second crystalline oxide, and the second crystalline oxide is arranged on one side of the substrate in the thickness direction. Orthographic projections of the first crystal oxide and the second crystal oxide on the substrate are arranged at intervals. The TFT structure provided by the invention can improve the use performance of the display device.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and more specifically, relates to a TFT structure, a manufacturing method, an array substrate, a display panel and a display device. Background Art

[0002] Organic Light Emitting Display (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) can achieve narrow borders and a wide range of refresh rates, and are widely used in various electronic products such as mobile phones, televisions, laptops, and desktop computers.

[0003] However, the performance of OLED display devices needs to be further improved. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a TFT structure, a manufacturing method, an array substrate, a display panel and a display device to improve the performance of an OLED display device.

[0005] To achieve the above purpose, the technical solution adopted in this application is:

[0006] In a first aspect, the present application provides a TFT structure, comprising a substrate, an active layer and a crystallization inducing layer, wherein the active layer is arranged on one side in the thickness direction of the substrate, the active layer comprises a first crystalline oxide and a second crystalline oxide, and the first crystalline oxide and the second crystalline oxide are arranged at intervals in their orthographic projection on the substrate.

[0007] The crystallization inducing layer is disposed on a side of the active layer facing the substrate, and the crystallization inducing layer is adjacent to one of the first crystalline oxide and the second crystalline oxide, wherein at least a portion of an orthographic projection of one of the first crystalline oxide and the second crystalline oxide on the substrate is located within the orthographic projection of the crystallization inducing layer on the substrate.

[0008] Through the above technical solution, the crystallization inducing layer can improve the crystallization effect of the crystallized oxide, so the crystallization inducing layer can improve the crystallization effect of one of the first crystallized oxide and the second crystallized oxide adjacent to the crystallization inducing layer, improve the mobility, and facilitate a large output current. In addition, the other of the first crystallized oxide and the second crystallized oxide is not adjacent to the crystallization inducing layer, maintaining a large subthreshold swing. Therefore, the TFT structure provided by the present application can take into account both high mobility and large subthreshold swing, thereby facilitating improving the performance of the display device.

[0009] Therefore, the TFT structure provided by the present application can improve the performance of the display device.

[0010] In some embodiments, an orthographic projection of one of the first crystalline oxide and the second crystalline oxide on the substrate coincides with an orthographic projection of the crystallization inducing layer on the substrate.

[0011] Thus, the crystallization effect of the one of the first crystalline oxide and the second crystalline oxide adjacent to the crystallization inducing layer is better.

[0012] In some embodiments, the crystallization inducing layer is adjacent to the first crystallized oxide, at least a portion of an orthographic projection of the first crystallized oxide on the substrate is located within the orthographic projection of the crystallization inducing layer on the substrate, the TFT structure includes a switching region and a driving region, the first crystallized oxide is located in the switching region, and the second crystallized oxide is located in the driving region.

[0013] In this way, in the TFT structure provided by the present application, the first crystalline oxide in the switching area can have high mobility, which is conducive to achieving narrow borders and a wide range of refresh rates, and the second crystalline oxide in the driving area can have a large subthreshold swing to meet driving requirements.

[0014] In some embodiments, the first crystalline oxide and / or the second crystalline oxide comprises a metal oxide.

[0015] In some embodiments, the first crystalline oxide and / or the second crystalline oxide includes indium gallium oxide, wherein a ratio of gallium content to indium content is a, and a has a value range of 0<a≤1.

[0016] In some embodiments, the first crystalline oxide and / or the second crystalline oxide includes indium oxide.

[0017] In some embodiments, the first crystalline oxide and / or the second crystalline oxide contains a doping element, the doping element includes at least one of zinc, tin and germanium, the content of the doping element is b, and the value range of b is: 0<b≤20%.

[0018] In some embodiments, the thickness of the first crystalline oxide and / or the second crystalline oxide is d, and the value range of d is: 5nm≤c≤100nm.

[0019] In some embodiments, the crystallization inducing layer includes aluminum oxide.

[0020] In some embodiments, the crystallization inducing layer includes indium gallium oxide, and the hydrogen content in the crystallization inducing layer is c, and the value range of c is: 1%≤c≤20%.

[0021] In a second aspect, the present application provides a method for manufacturing a TFT structure, the manufacturing method comprising:

[0022] forming a crystallization inducing layer on the substrate;

[0023] forming a first crystalline oxide in the region where the crystallization inducing layer is located;

[0024] A second crystalline oxide is formed in regions other than the crystallization inducing layer.

[0025] In this way, the manufacturing method provided by the present application forms a first crystalline oxide in the area where the crystallization induction layer is located, so the crystallization induction layer can improve the crystallization effect of the first crystalline oxide, improve the mobility, and facilitate a large output current. In addition, the second crystalline oxide is not affected by the crystallization induction layer in the area outside the crystallization induction layer, and can maintain a large subthreshold swing. Therefore, the manufacturing method provided by the present application can make the TFT structure take into account both high mobility and large subthreshold swing, which is conducive to improving the performance of the display device.

[0026] In some embodiments, the TFT structure includes a switching region and a driving region, the crystallization inducing layer is located in the switching region, and the second crystalline oxide is located in the driving region.

[0027] In this way, the manufacturing method provided in the present application can make the first crystalline oxide in the switching area of ​​the TFT structure have high mobility, which is conducive to achieving narrow borders and a wide range of refresh rates, and can also make the second crystalline oxide in the driving area have a large subthreshold swing, thereby meeting driving requirements.

[0028] In some embodiments, the first crystalline oxide and / or the second crystalline oxide is formed by an atomic layer deposition technique.

[0029] In a third aspect, the present application provides an array substrate, including the TFT structure of any of the above embodiments. The array substrate provided by the present application has the same technical effects as the TFT structure of the above embodiments, which will not be described in detail here.

[0030] In a fourth aspect, the present application provides a display panel, comprising the array substrate of the above embodiment. The display panel provided by the present application has the same technical effect as the array substrate of the above embodiment, which will not be described in detail here.

[0031] In a fifth aspect, the present application provides a display device, comprising the display panel of the above embodiment. The display device provided by the present application has the same technical effect as the display panel of the above embodiment, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0033] Figure 1 This is one of the cross-sectional structural schematic diagrams of the TFT structure provided in the embodiment of the present application;

[0034] Figure 2 The second schematic cross-sectional view of the TFT structure provided in the embodiment of the present application;

[0035] Figure 3 The third schematic diagram of the cross-sectional structure of the TFT structure provided in the embodiment of the present application;

[0036] Figure 4 One of the structural schematic diagrams of the TFT structure provided in the embodiment of the present application during the manufacturing process;

[0037] Figure 5 The second structural schematic diagram of the TFT structure provided in the embodiment of the present application during the manufacturing process;

[0038] Figure 6 The third structural schematic diagram of the TFT structure provided in the embodiment of the present application during the manufacturing process;

[0039] Figure 7 One of the flow diagrams of the method for manufacturing a TFT structure provided in an embodiment of the present application;

[0040] Figure 8 A second schematic flow chart of a method for manufacturing a TFT structure provided in an embodiment of the present application;

[0041] Fig. 9 The third schematic flow chart of the method for manufacturing the TFT structure provided in the embodiment of the present application.

[0042] Among them, the reference numerals in the figure are:

[0043] 10 - substrate; 20 - barrier layer; 31 - first gate; 32 - second gate; 40 - first gate dielectric layer; 50 - crystallization inducing layer; 61 - first crystalline oxide; 62 - second crystalline oxide; 70 - second gate dielectric layer; 80 - interlayer dielectric layer; 90 - source / drain. DETAILED DESCRIPTION

[0044] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0046] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0047] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0048] An embodiment of the present application provides a display device, which can be an electronic product such as a mobile phone, a television, a tablet computer, a laptop computer, a desktop computer, a vehicle-mounted display terminal, a wearable device, a human-computer interaction terminal device, etc.

[0049] The display device includes a display panel, which may include an array substrate and other film layers supported by the array substrate. The other film layers may include a polarizing film, an optically clear adhesive (OCA), and the like.

[0050] The display panel includes an array substrate, a pixel defined layer (Pixel Defined Layer, PDL) disposed on the array substrate, and a light emitting element disposed on the pixel defined layer.

[0051] The array substrate includes a plurality of TFT (Thin Film Transistor) structures arranged in an array. The TFT structure generally uses a high-transformation oxide to form a semiconductor layer.

[0052] High mobility oxide has high mobility and low leakage current, which is conducive to achieving narrow borders and a wide range of refresh rates, and has great advantages in active matrix organic light emitting diode (AMOLED) applications. According to crystallinity, high mobility oxide can be divided into amorphous high mobility oxide and crystalline high mobility oxide.

[0053] The inventors found that materials with good crystallinity have higher mobility, which is more conducive to large output current. However, when the mobility is high, the subthrehold swing (SS) will be smaller, which is not conducive to the development of grayscale. Among them, mobility refers to the average drift speed of carriers (electrons or holes) generated under unit electric field strength. Mobility represents the size of the carrier's conductivity. It and the carrier concentration jointly determine the conductivity of the semiconductor; subthreshold swing is a performance indicator that measures the mutual conversion rate between the on and off states of the transistor. It represents the change in gate voltage required for the source-drain current to change tenfold.

[0054] The inventors also found that it is difficult for crystalline high-mobility oxide to simultaneously achieve both high mobility and large subthreshold swing. The TFT structure provided in the embodiment of the present application can use crystalline high-mobility oxide to form a semiconductor layer.

[0055] Therefore, the display device provided in the embodiment of the present application can achieve a narrow border and a wide range of refresh rates, but the performance needs to be further improved, for example, how to meet the requirements of both high mobility and large subthreshold swing.

[0056] Please also read Figure 1 , Figure 2 and Figure 3 An embodiment of the present application provides a TFT structure, including a substrate 10 and a barrier layer 20, a first gate dielectric layer 40, a second gate dielectric layer 70 and an interlayer dielectric layer 80 stacked in sequence in a direction away from the substrate 10.

[0057] The TFT structure provided in the embodiment of the present application further includes an active layer, which is disposed on one side of the substrate 10 in the thickness direction and is located between the first gate dielectric layer 40 and the second gate dielectric layer 70. The TFT structure provided in the embodiment of the present application further includes a source / drain electrode 90, a first gate electrode 31 and a second gate electrode 32, wherein the first gate electrode 31 is located between the barrier layer 20 and the first gate dielectric layer 40, the second gate electrode 32 is located between the second gate dielectric layer 70 and the interlayer dielectric layer 80, and the source / drain electrode 90 passes through the interlayer dielectric layer 80 and the second gate dielectric layer 70 to contact the active layer.

[0058] The active layer includes a first crystalline oxide 61 and a second crystalline oxide 62 . The first crystalline oxide 61 and the second crystalline oxide 62 are connected to the source / drain electrodes 90 . The first crystalline oxide 61 and the second crystalline oxide 62 are spaced apart from each other in an orthographic projection on the substrate 10 .

[0059] That is, the first crystalline oxide 61 and the second crystalline oxide 62 are separated and located in different regions of the TFT structure. It is understandable that different regions of the TFT structure have different requirements for the crystallization performance of the crystalline oxide. For example, in the switch region (i.e., the region where the switch transistor is located), the crystalline oxide needs to have good crystallization performance and high mobility; in the drive region (i.e., the region where the drive transistor is located), the crystalline oxide needs to have a large subthreshold swing to meet the drive requirements.

[0060] The TFT structure provided in the embodiment of the present application further includes a crystallization inducing layer 50 , which is disposed on the side of the active layer facing the substrate 10 and between the active layer and the first gate dielectric layer 40 , and is adjacent to one of the first crystalline oxide 61 and the second crystalline oxide 62 .

[0061] In this case, at least a portion of the orthographic projection of one of the first crystalline oxide 61 and the second crystalline oxide 62 adjacent to the crystallization inducing layer 50 on the substrate 10 is located within the orthographic projection of the crystallization inducing layer 50 on the substrate 10 .

[0062] It can be understood that the crystallization inducing layer 50 can improve the crystallization effect of the crystalline oxide, so the crystallization inducing layer 50 can improve the crystallization effect of one of the first crystalline oxide 61 and the second crystalline oxide 62 adjacent to the crystallization inducing layer 50, improve the mobility, and facilitate a large output current.

[0063] In addition, the other of the first crystalline oxide 61 and the second crystalline oxide 62 is not adjacent to the crystallization inducing layer 50, maintaining a large subthreshold swing. Therefore, the TFT structure provided by the present application can take into account both high mobility and large subthreshold swing, thereby facilitating improving the performance of the display device.

[0064] Therefore, the TFT structure provided by the present application can improve the performance of the display device.

[0065] For example, the first crystalline oxide 61 is adjacent to the crystallization inducing layer 50 , the first crystalline oxide 61 has a higher mobility, and the second crystalline oxide 62 has a larger subthreshold swing.

[0066] For example, the second crystalline oxide 62 is adjacent to the crystallization inducing layer 50 , the second crystalline oxide 62 has a higher mobility, and the first crystalline oxide 61 has a larger subthreshold swing.

[0067] See also Figure 1, illustratively, the orthographic projection of one of the first crystalline oxide 61 and the second crystalline oxide 62 adjacent to the crystallization inducing layer 50 on the substrate 10 covers the orthographic projection of the crystallization inducing layer 50 on the substrate 10. Optionally, the orthographic projection area of ​​one of the first crystalline oxide 61 and the second crystalline oxide 62 adjacent to the crystallization inducing layer 50 (e.g., the first crystalline oxide 61) on the substrate 10 is greater than the orthographic projection area of ​​the crystallization inducing layer 50 on the substrate 10.

[0068] See also Figure 2 , illustratively, the orthographic projection of one of the first crystalline oxide 61 and the second crystalline oxide 62 adjacent to the crystallization inducing layer 50 on the substrate 10 is located within the orthographic projection of the crystallization inducing layer 50 on the substrate 10. Optionally, the area of ​​the orthographic projection of the crystallization inducing layer 50 on the substrate 10 is larger than the area of ​​the orthographic projection of one of the first crystalline oxide 61 and the second crystalline oxide 62 adjacent to the crystallization inducing layer 50 on the substrate 10. The crystallization inducing layer 50 can improve the overall crystallization performance of the one of the first crystalline oxide 61 and the second crystalline oxide 62 adjacent to the crystallization inducing layer 50, and the crystallization effect is better.

[0069] See also Figure 3 For example, the orthographic projection of one of the first crystalline oxide 61 and the second crystalline oxide 62 adjacent to the crystallization inducing layer 50 on the substrate 10 coincides with the orthographic projection of the crystallization inducing layer 50 on the substrate 10 .

[0070] Thus, the crystallization effect of the one of the first crystalline oxide 61 and the second crystalline oxide 62 adjacent to the crystallization inducing layer 50 is better.

[0071] In some embodiments, the crystallization inducing layer 50 is adjacent to the first crystalline oxide 61, and at least a portion of the orthographic projection of the first crystalline oxide 61 on the substrate 10 is located within the orthographic projection of the crystallization inducing layer 50 on the substrate 10. That is, the one of the first crystalline oxide 61 and the second crystalline oxide 62 adjacent to the crystallization inducing layer 50 is the first crystalline oxide 61.

[0072] The TFT structure includes a switch region (ie, a region where a switch transistor is located) and a drive region (ie, a region where a drive transistor is located). The first crystalline oxide 61 is located in the switch region, and the second crystalline oxide 62 is located in the drive region.

[0073] In this way, in the TFT structure provided in the embodiment of the present application, the first crystalline oxide 61 in the switching area can have high mobility, which is conducive to achieving narrow borders and a wide range of refresh rates, and the second crystalline oxide 62 in the driving area can have a large subthreshold swing to meet driving requirements.

[0074] In some embodiments, the first crystalline oxide 61 and / or the second crystalline oxide 62 include metal oxides. The metal oxides include indium oxide (In Oxide), indium zinc oxide (In-Zn Oxide), indium tin oxide (In-Sn Oxide), indium titanium oxide (In-Ti Oxide), indium gallium oxide (In-Ga Oxide), indium gallium aluminum oxide (In-Ga-Al Oxide), indium gallium tin oxide (In-Ga-Sn Oxide, also written as IGTO), gallium zinc oxide (Ga-Zn Oxide, also written as GZO), aluminum zinc oxide (Al-Zn Oxide, also written as AZO), indium aluminum zinc oxide (In-Al-Zn Oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn Oxide, also written as ITZO), indium titanium zinc oxide (In-Ti-Zn Oxide), indium gallium zinc oxide (In-Ga-ZnOxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn Oxide, also written as IGZO), Oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn Oxide, also written as IGAZO, IGZAO or IAGZO), gallium tin oxide (Ga-Sn Oxide), aluminum tin oxide (Al-Sn Oxide), etc.

[0075] In some embodiments, the first crystalline oxide 61 and / or the second crystalline oxide 62 includes indium gallium oxide (IGO), wherein the ratio of gallium (Ga) content to indium (In) content is a, and the value range of a is: 0<a≤1.

[0076] Exemplarily, the value of a can be: 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, etc.

[0077] It can be understood that when the total amount of gallium and indium is 1, the value range of gallium content a1 is: 0<a1≤50%, and the value range of indium content a2 is: 50%≤a2<100%. The gallium content is less than or equal to the indium content, which can make the crystalline oxide more likely to crystallize after film formation and annealing to a certain extent, thereby facilitating the crystalline oxide to have better crystallinity and higher mobility.

[0078] Exemplarily, the first crystalline oxide 61 is indium gallium oxide, wherein the ratio of the gallium content to the indium content is a, and the value range of a is: 0<a≤1.

[0079] Exemplarily, the second crystalline oxide 62 is indium gallium oxide, wherein the ratio of the gallium content to the indium content is a, and the value range of a is: 0<a≤1.

[0080] Exemplarily, the first crystalline oxide 61 and the second crystalline oxide 62 are both indium gallium oxide, wherein the ratio of the gallium content to the indium content in the first crystalline oxide 61 is a, and the ratio of the gallium content to the indium content in the second crystalline oxide 62 is also a, and the value range of a is: 0<a≤1.

[0081] In some other embodiments, the first crystalline oxide 61 and / or the second crystalline oxide 62 includes indium oxide. That is, the first crystalline oxide 61 and / or the second crystalline oxide 62 does not contain gallium.

[0082] Exemplarily, the first crystalline oxide 61 is indium oxide. Exemplarily, the second crystalline oxide 62 is indium oxide. Exemplarily, the first crystalline oxide 61 and the second crystalline oxide 62 are both indium oxide.

[0083] In some embodiments, the first crystalline oxide 61 and / or the second crystalline oxide 62 contains doping elements, the doping elements include at least one of zinc (Zn), tin (Sn) and germanium (Ge), the content of the doping element is b, and the value range of b is: 0<b≤20%.

[0084] Exemplarily, the doping element includes zinc. Exemplarily, the doping element includes tin. Exemplarily, the doping element includes germanium. Exemplarily, the doping element includes zinc, tin and germanium.

[0085] Exemplarily, the value of b may be 5%, 10%, 15%, 20%, etc.

[0086] It is understood that the inclusion of zinc in the crystalline oxide can make the light-emitting element emit light with good light stability, easier to shape, convenient to process, and have good compatibility. In addition, the inclusion of germanium in the crystalline oxide can make it easier to shape, convenient to process, and have good compatibility.

[0087] Exemplarily, the first crystalline oxide 61 contains a doping element. Exemplarily, the second crystalline oxide 62 contains a doping element. Exemplarily, both the first crystalline oxide 61 and the second crystalline oxide 62 contain a doping element.

[0088] In some embodiments, the crystallization inducing layer 50 may be aluminum oxide.

[0089] In some other embodiments, the crystallization inducing layer 50 is indium gallium oxide, the hydrogen content in the crystallization inducing layer 50 is c, and the value range of c is: 1%≤c≤20%.

[0090] Exemplarily, the value of c may be: 1%, 3%, 5%, 10%, 15%, 20%, etc.

[0091] In some embodiments, the thickness of the first crystalline oxide 61 and / or the second crystalline oxide 62 is d, and the value range of d is: 5 nm≤d≤100 nm.

[0092] Exemplarily, the value of d can be: 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc.

[0093] Please also read Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 , an embodiment of the present application further provides a method for manufacturing a TFT structure, the manufacturing method comprising the following steps:

[0094] S1, forming a crystallization inducing layer 50 on the substrate 10. The specific formation process of the crystallization inducing layer 50 is as follows:

[0095] S11, forming a crystallization inducing film layer on the substrate 10;

[0096] S12, removing the crystallization inducing film layer outside the first preset area on the substrate 10, wherein the first preset area may be a switch area.

[0097] Please also read Figure 4 , Figure 5 , Figure 7 and Figure 8 It can be understood that the manufacturing method provided in the embodiment of the present application sequentially forms the blocking layer 20, the first gate 31 and the first gate dielectric layer 40 on the substrate 10 after providing the substrate 10 and before forming the crystallization inducing layer 50 on the substrate 10.

[0098] S21, forming a first crystalline oxide 61 in the region where the crystallization inducing layer 50 is located, wherein the region where the crystallization inducing layer 50 is located may be a first preset region.

[0099] S22, forming a second crystalline oxide 62 in a region outside the crystallization inducing layer 50, wherein the second crystalline oxide 62 is formed in a second preset region, and the second preset region is outside the crystallization inducing layer 50.

[0100] It can be understood that step S21 and step S22 can be performed simultaneously, and the specific formation process of the first crystalline oxide 61 and the second crystalline oxide 62 is as follows:

[0101] S23, forming a crystalline oxide film layer on the substrate 10;

[0102] S24, removing the crystalline oxide film layer outside the first preset area and the second preset area on the substrate 10, thereby obtaining the first crystalline oxide 61 and the second crystalline oxide 62.

[0103] Please also read Figure 6 , Figure 7 and Fig. 9 The manufacturing method provided in the present application forms a first crystalline oxide 61 in the area (first preset area) where the crystallization inducing layer 50 is located. Therefore, the crystallization inducing layer 50 can improve the crystallization effect of the first crystalline oxide 61 and improve the mobility, which is conducive to a large output current.

[0104] In addition, the second crystalline oxide 62 in the region outside the crystallization inducing layer 50 is not affected by the crystallization inducing layer 50 and can maintain a larger subthreshold swing.

[0105] Therefore, the manufacturing method provided in the present application can enable the TFT structure to have both high mobility and large subthreshold swing, thereby facilitating improving the performance of the display device.

[0106] Optionally, the TFT structure includes a switch region and a drive region, the crystallization inducing layer 50 is located in the switch region, and the second crystallized oxide 62 is located in the drive region. That is, the first preset region is the switch region, and the second preset region is the drive region.

[0107] In this way, the manufacturing method provided in the present application can make the first crystalline oxide 61 in the switching area of ​​the TFT structure have high mobility, which is conducive to achieving narrow borders and a wide range of refresh rates, and can also make the second crystalline oxide 62 in the driving area have a large subthreshold swing, thereby meeting driving requirements.

[0108] In some embodiments, the first crystalline oxide 61 and / or the second crystalline oxide 62 are formed by an atomic layer deposition technique.

[0109] It is understood that by forming the crystalline oxide through the atomic layer deposition technology, the content of the element components in the crystalline oxide can be changed in the thickness direction of the substrate 10. For example, the indium content in the crystalline oxide can gradually increase or decrease in the direction away from the substrate 10. For example, the indium content in the crystalline oxide can first decrease and then increase in the direction away from the substrate 10. For example, the indium content in the crystalline oxide can first increase and then decrease in the direction away from the substrate 10.

[0110] Exemplarily, the first crystalline oxide 61 is formed by atomic layer deposition technology. Exemplarily, the second crystalline oxide 62 is formed by atomic layer deposition technology. Exemplarily, the first crystalline oxide 61 and the second crystalline oxide 62 are formed by atomic layer deposition technology.

[0111] Optionally, the TFT structure provided in the embodiment of the present application can be manufactured by the manufacturing method of any of the above embodiments.

[0112] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A TFT structure, characterized in that: include: substrate; An active layer is arranged on one side of the substrate in the thickness direction, the active layer comprises a first crystalline oxide and a second crystalline oxide, and the first crystalline oxide and the second crystalline oxide are arranged at an interval in their orthographic projections on the substrate; a crystallization inducing layer, disposed on a side of the active layer facing the substrate, the crystallization inducing layer being adjacent to one of the first crystalline oxide and the second crystalline oxide, Wherein, at least a portion of an orthographic projection of one of the first crystalline oxide and the second crystalline oxide on the substrate is located within an orthographic projection of the crystallization inducing layer on the substrate.

2. The TFT structure according to claim 1, wherein: An orthographic projection of one of the first crystalline oxide and the second crystalline oxide on the substrate coincides with an orthographic projection of the crystallization inducing layer on the substrate.

3. The TFT structure according to claim 1, wherein: The crystalline inducing layer is adjacent to the first crystalline oxide, and at least a portion of an orthographic projection of the first crystalline oxide on the substrate is located within the orthographic projection of the crystalline inducing layer on the substrate. The TFT structure includes a switching region and a driving region, the first crystalline oxide is located in the switching region, and the second crystalline oxide is located in the driving region.

4. The TFT structure according to any one of claims 1 to 3, characterized in that: The first crystalline oxide and / or the second crystalline oxide comprises a metal oxide; Preferably, the first crystalline oxide and / or the second crystalline oxide comprises indium gallium oxide, wherein the ratio of the content of gallium to the content of indium is a, and the value range of a is: 0<a≤1; Alternatively, the first crystalline oxide and / or the second crystalline oxide comprises indium oxide; Preferably, the first crystalline oxide and / or the second crystalline oxide contains a doping element, the doping element includes at least one of zinc, tin and germanium, the content of the doping element is b, and the value range of b is: 0<b≤20%; Preferably, the thickness of the first crystalline oxide and / or the second crystalline oxide is d, and the value range of d is: 5nm≤c≤100nm.

5. The TFT structure according to any one of claims 1 to 3, characterized in that: The crystallization inducing layer comprises aluminum oxide; Alternatively, the crystallization inducing layer includes indium gallium oxide, the hydrogen content in the crystallization inducing layer is c, and the value range of c is: 1%≤c≤20%.

6. A method for manufacturing a TFT structure, characterized in that: include: forming a crystallization inducing layer on the substrate; forming a first crystalline oxide in the region where the crystallization inducing layer is located; A second crystalline oxide is formed in the region outside the crystallization inducing layer.

7. The manufacturing method according to claim 6, characterized in that: The TFT structure comprises a switch region and a drive region, the crystallization induction layer is located in the switch region, and the second crystallized oxide is located in the drive region; Preferably, the first crystalline oxide and / or the second crystalline oxide are formed by atomic layer deposition technology.

8. An array substrate, characterized in that: It comprises the TFT structure according to any one of claims 1 to 5, or the TFT structure manufactured by the manufacturing method according to any one of claims 6 to 7.

9. A display panel, characterized in that: Comprising the array substrate as claimed in claim 8.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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