Quantum dot-nanowire avalanche diode single-photon detector and preparation method thereof

Abstract

This invention relates to an avalanche diode single-photon detector and its fabrication method, particularly to a quantum dot-nanowire avalanche diode single-photon detector and its fabrication method, solving the problems of low detection efficiency in existing single-photon detectors and the high fabrication difficulty and limited improvement effect when using existing methods to improve efficiency. The detector includes detector N. + The substrate, multiple quantum dot-nanowire units spaced apart on its surface, and also include a passivation layer, a P-type electrode, and an N-type electrode; the quantum dot-nanowire unit includes semiconductor nanowires, a porous nanomaterial layer, and a quantum dot material layer; the semiconductor nanowires include heavily doped N-type... + Layer, undoped type I layer and heavily doped P + Layers; a porous nanomaterial layer covering the semiconductor nanowire; a quantum dot material layer covering the porous nanomaterial layer; a passivation layer filling the spaces between the quantum dot-nanowire units; a P-type electrode grown on top of the quantum dot-nanowire units; and an N-type electrode grown on the detector N. + On the upper surface of the substrate.

Description

Technical Field

[0001] This invention relates to an avalanche diode single-photon detector and its fabrication method, and particularly to a quantum dot-nanowire avalanche diode single-photon detector and its fabrication method. Background Technology

[0002] Single-photon detectors possess extremely high sensitivity at the photon scale, playing a crucial role in advancing cutting-edge fields such as quantum communication, biomedicine, and remote sensing. Avalanche diode single-photon detector arrays are an important type of single-photon detector, offering advantages over other single-photon detectors such as photomultiplier tubes and superconducting single-photon detectors, including high integration, low power consumption, and versatility in applications. However, the photon detection efficiency of single-photon avalanche diodes is limited by the photon absorption efficiency of the photon-absorbing material. Existing Si, SiGe, and III-V group single-photon avalanche diodes have limited response bands and relatively low photon absorption efficiencies, restricting further improvements in the performance of avalanche diode single-photon detectors.

[0003] Existing methods to improve photon absorption efficiency include integrating a microlens structure into the light-gathering surface of an avalanche diode single-photon detector or introducing a distributed Bragg mirror structure within it. These two methods are detailed below:

[0004] (1) Integrating a microlens structure on the light-receiving surface of the detector. The principle of this method is to utilize the deflection and converging effect of the microlens structure integrated on the light-receiving surface of the detector to focus light onto the active region of the detector, thereby improving the absorption rate of incident light. The disadvantage of this method is that the deflection and converging effect of the microlens structure on light not only depends on the size and structural design, but also the final appearance of the microlens structure morphology is affected by the photolithography mask preparation and etching process, making it difficult to strictly control the morphology of the microlens structure. This results in high fabrication costs and a lower-than-expected focusing effect. In addition, because the microlens units are isolated from each other, their fill factor in the entire detector chip is low, which has a limited effect on improving photon absorption efficiency, and thus the effect on improving the photon detection efficiency of the detector is not obvious.

[0005] (2) Introducing a distributed Bragg mirror structure inside the detector. The principle of this method is to improve the peak value of photon absorption and the in-band flatness of broadband light absorption by using a distributed Bragg mirror structure introduced inside the detector. The disadvantage of this method is that the specific composition of the distributed Bragg mirror structure involves the stacking of multiple thin film materials with different refractive indices, making it difficult to find the optimal solution for material thickness design, thus limiting its effect on improving photon absorption efficiency; in addition, introducing a distributed Bragg mirror structure increases the number of detector fabrication steps, increasing the difficulty and complexity of the process, and resulting in higher fabrication costs.

[0006] In summary, developing an avalanche diode single-photon detector that is easy to fabricate, has low fabrication cost, and high photon detection efficiency is an urgent problem to be solved. Summary of the Invention

[0007] The purpose of this invention is to address the technical problems of low photon detection efficiency in existing avalanche diode single-photon detectors, and the increased difficulty and cost of fabrication, as well as the limited effect on improving photon detection efficiency when using existing methods to enhance their photon detection efficiency. The invention provides a quantum dot-nanowire avalanche diode single-photon detector and its fabrication method.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0009] A quantum dot-nanowire avalanche diode single-photon detector, which is special in that:

[0010] Including detector N + Substrates and spacers are arranged in the N-type detector. + The substrate consists of multiple quantum dot-nanowire units on its surface, as well as a passivation layer, a P-type electrode, and an N-type electrode.

[0011] Each of the quantum dot-nanowire units comprises a semiconductor nanowire, a porous nanomaterial layer, and a quantum dot material layer;

[0012] The semiconductor nanowires include heavily doped N. + Layer, undoped type I layer and heavily doped P + Layer; the heavily doped N + Epitaxial growth of the layer on detector N + On the upper surface of the substrate, its shape is a cone, wider at the bottom and narrower at the top; the undoped type I layer is epitaxially grown on a heavily doped N-type substrate. + On the outer surface of the layer, heavily doped N + Layer coverage, its lower end face is connected to detector N + A gap is left between the upper surfaces of the substrates, and the distance of this gap meets the following condition: to ensure that the undoped type I layer and the detector N... + Electrical isolation is formed between the substrates; the heavily doped P + The epitaxial layer is grown on the outer surface of the undoped type I layer, covering the undoped type I layer, and its lower end face is adjacent to the detector N. + A gap is left between the upper surfaces of the substrate, and the distance of this gap meets the following condition: allowing heavily doped P + Layer and detector N + Electrical isolation is formed between the substrates;

[0013] The porous nanomaterial layer is grown on the outer surface of the semiconductor nanowire, covering the semiconductor nanowire; the quantum dot material layer is coated on the outer surface of the porous nanomaterial layer, covering the porous nanomaterial layer; the quantum dot material layer is used to absorb photons; the porous nanomaterial layer is used to absorb photogenerated excitons and realize electron-hole separation; the semiconductor nanowire is used to realize photogenerated carrier multiplication;

[0014] The passivation layer fills the gaps between the quantum dot-nanowire units and the outer ring surrounding all the quantum dot-nanowire units; the upper surface of the passivation layer is parallel to the detector N. + The top of the quantum dot-nanowire unit extends beyond the top surface of the passivation layer on the upper surface of the substrate.

[0015] The P-type electrode is grown on the outer surface of the protruding portion of each quantum dot-nanowire unit that extends beyond the upper surface of the passivation layer. Its lower surface is coplanar with the upper surface of the passivation layer, covering the upper surface of the passivation layer and the outer surface of the protruding portion of each quantum dot-nanowire unit that extends beyond the upper surface of the passivation layer.

[0016] The N-type electrode is grown on the detector N + It is located on the upper surface of the substrate, and outside the outer contour of the passivation layer.

[0017] Furthermore, the detector N + The substrate refers to a doping concentration in the range of 5 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer;

[0018] The heavily doped N + A layer refers to a doping concentration range of 5 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer;

[0019] The heavily doped P + A layer refers to a doping concentration range of 5 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 The P-type semiconductor layer.

[0020] Furthermore, the height of the top of the quantum dot-nanowire unit extending beyond the upper surface of the passivation layer is greater than or equal to 10 nm and less than or equal to 1 μm.

[0021] Furthermore, the detector N + The substrate and the semiconductor nanowires are made of silicon, germanium, or group III-V semiconductor materials;

[0022] The porous nanomaterial layer is made of a two-dimensional material;

[0023] The quantum dot material layer is made of lead sulfide, indium phosphide, cadmium selenide, or indium arsenide.

[0024] The passivation layer is made of benzocyclobutene, SU-8 resin, or spin-coated glass.

[0025] The P-type electrode is made of a transparent conductive film;

[0026] The N-type electrode is made of a metallic material or a multilayer material of multiple metals.

[0027] Furthermore, for the sake of process simplicity, the heavily doped P + The lower end face of the layer and the detector N + The distance between the upper surfaces of the substrate is greater than the distance between the lower end face of the undoped type I layer and the detector N. + The distance between the upper surfaces of the substrate.

[0028] Meanwhile, the present invention also provides a method for fabricating the above-mentioned quantum dot-nanowire avalanche diode single-photon detector, which is characterized by including the following steps:

[0029] Step 1: Based on the size and material requirements of the quantum dot-nanowire avalanche diode single-photon detector to be fabricated, prepare the detector N... + Substrate;

[0030] Step 2: The detector N prepared in step 1 + Gold nanoparticles are deposited by aerosol on the substrate surface as epitaxial growth of heavily doped N nanoparticles. + The catalyst layer; when depositing gold nanoparticles in an aerosol, the concentration of gold nanoparticles in the aerosol is determined according to the requirements of the detector N in the quantum dot-nanowire avalanche diode single-photon detector to be prepared. + The number of quantum dot-nanowire units spaced per unit area on the substrate surface is determined;

[0031] Step 3: In step 2, gold nanoparticles were deposited in the aerosol to form the detector N. + On the surface of the substrate, heavily doped N is epitaxially grown. + Layers, grown at intervals on detector N + Multiple heavily doped N-type cones with a larger bottom and a smaller top on the upper surface of the substrate + layer;

[0032] Step 4: The heavily doped N obtained in step 3 + On the outer surface of the layer, undoped type I layers are epitaxially grown, resulting in spaced layers grown on the detector N. +Multiple outer surfaces on the substrate surface are covered by an undoped type I layer with heavily doped N + layer;

[0033] Step 5: The heavily doped N₂ with its outer surface covered by an undoped type I layer obtained in step 4. + On the outer surface of each undoped type I layer corresponding to the layer, heavily doped P is epitaxially grown. + Layers, grown at intervals on detector N + Multiple prototype semiconductor nanowires on the surface of the substrate;

[0034] Step 6: The heavily doped P corresponding to each semiconductor nanowire prototype obtained in Step 5 + On the outer surface of the layer, photoresist is spin-coated; then, a plasma ashing process is used to remove the heavily doped P atoms. + On the outer surface of the layer, with detector N + The distance between the upper surfaces of the substrate is equal to the heavily doped P required in the quantum dot-nanowire avalanche diode single-photon detector to be fabricated. + The lower end face of the layer and the detector N + The photoresist, spin-coated, is removed from the region above the lower contour line formed by the points spaced apart between the upper surfaces of the substrate. Then, a metal deposition process is used to deposit metal on the overall outer surface of the semiconductor nanowire prototype, which retains the photoresist, on the lower outer surface. Finally, a lift-off process is used to remove the photoresist and the metal deposited on the photoresist's outer surface, resulting in a nanowire structure grown at intervals on the detector N. + Semiconductor nanowire prototypes with metal masks deposited on multiple upper outer surfaces of the substrate surface;

[0035] Step 7: Using a semiconductor wet etching process, expose the heavily doped P at the lower end of the semiconductor nanowire prototypes with metal masks deposited on their upper outer surfaces obtained in Step 6. + The layer and the corresponding undoped type I layer within it are removed to prevent heavy doping of P. + Layer and undoped type I layer, with detector N + Electrical connections are created on the substrate to eliminate leakage paths; then, a wet etching process is used to remove the metal mask deposited on the outer surface of each semiconductor nanowire prototype, resulting in nanowires arranged at intervals and grown on the detector N. + Multiple semiconductor nanowires on the surface of the substrate;

[0036] Step 8: On the outer surface of each of the semiconductor nanowires obtained in step 7, a porous nanomaterial layer is grown to cover each of the semiconductor nanowires;

[0037] Step 9: On the outer surface of the porous nanomaterial layer corresponding to each semiconductor nanowire that has been grown on the outer surface in step 8, a quantum dot material layer is coated to cover each porous nanomaterial layer, resulting in a layer arranged at intervals on the detector N. + Multiple quantum dot-nanowire units on the surface of the substrate;

[0038] Step 10: The gap positions between each quantum dot-nanowire unit obtained in step 9 and the outer ring position surrounding all the quantum dot-nanowire units are coated with passivation material and subjected to heat treatment to form a thermosetting polymer, i.e., a passivation layer is formed.

[0039] Step 11: Use an etching process to remove excess passivation material from the passivation layer formed in step 10 to expose the top of each quantum dot-nanowire unit obtained in step 9; then grow a P-type electrode on the outer surface of the protruding portion of the top of each quantum dot-nanowire unit that extends beyond the upper surface of the passivation layer.

[0040] Step 12: On the outer surface of the protruding portion extending from the top of the passivation layer of each quantum dot-nanowire unit in step 11, the detector N where the P-type electrode of each quantum dot-nanowire unit is located is grown. + On the upper surface of the substrate, at the position outside the outer contour of the passivation layer formed in step 10, an N-type electrode is grown; thus completing the fabrication of the quantum dot-nanowire avalanche diode single-photon detector.

[0041] Furthermore, in step 3, the epitaxial growth of heavily doped N + During the epitaxial growth of undoped type I layers in step 4 and during the epitaxial growth of heavily doped P layers in step 5 + In the case of layers, the growth methods are all chemical vapor deposition or molecular beam epitaxy.

[0042] Furthermore, in step 8, when growing the porous nanomaterial layer, the growth method can be pulsed laser deposition, chemical vapor deposition, or electrolytic etching.

[0043] Furthermore, in step 9, when coating the quantum dot material layer, the coating is performed by spin coating or spray coating.

[0044] Furthermore, in step 11, when growing the P-type electrode, the growth method is magnetron sputtering;

[0045] In step 12, when growing the N-type electrode, the growth method can be magnetron sputtering, electron beam evaporation, or conductive silver paste coating.

[0046] The beneficial effects of this invention are:

[0047] (1) The quantum dot-nanowire avalanche diode single-photon detector of the present invention integrates semiconductor nanowires with a quantum dot material layer. The quantum dot material layer is coated on the outer surface of a porous nanomaterial layer grown on the outer surface of the semiconductor nanowire. The quantum dot material is designed as a photon absorbing material to three-dimensionally cover the nanowire PIN avalanche diode. The quantum dot material layer is used as a photosensitive layer to efficiently capture incident photons and generate photogenerated carriers. The nanowire avalanche diode operates in Geiger mode, and the carriers undergo collisional ionization under high electric field conditions to form a detectable current. The present invention breaks through the limitation that the quantum dot material layer in conventional single-photon detectors can only cover a certain plane of the device, greatly increasing the effective area of ​​the photon absorbing layer and expanding the effective incident photon angle. The increased field of view of the detector enhances photon absorption efficiency, thereby significantly improving the photon detection efficiency of the single-photon detector. In the fabrication process of the quantum dot-nanowire avalanche diode single-photon detector of this invention, a simple liquid-phase processing technique is used to uniformly coat quantum dot materials over a large area onto the outer surface of a porous nanomaterial layer grown on the outer surface of semiconductor nanowires. This process is not limited by lattice mismatch, exhibiting excellent material compatibility. The fabrication is easy, process parameters are easy to control, and the fabrication cost is low. Therefore, this invention solves the technical problems of low photon detection efficiency in existing avalanche diode single-photon detectors, and the increased fabrication difficulty, higher fabrication cost, and limited effect on improving photon detection efficiency when using existing methods to improve their photon detection efficiency.

[0048] (2) In the quantum dot-nanowire avalanche diode single-photon detector of the present invention, quantum dot material is used as photon absorption material. By utilizing the quantum confinement effect of quantum dots, the material band gap can be precisely controlled by adjusting the size and material of quantum dots, and flexible spectral response can be achieved. Simple liquid phase processing technology such as spin coating and spraying is used to replace epitaxial material growth. Quantum dot material is uniformly coated on the outer surface of the porous nanomaterial layer grown on the outer surface of semiconductor nanowires, so that quantum dots and carrier avalanche multiplication structure are integrated, which improves the flexibility of device structure design. Photogenerated carrier multiplication is achieved by using vertical semiconductor nanowires. Since each semiconductor nanowire can undergo avalanche multiplication independently, the dark count and after-pulse effect of the single-photon detector can be effectively suppressed.

[0049] (3) The quantum dot-nanowire avalanche diode single-photon detector of the present invention effectively reduces the area per unit number of pixels while improving photon detection efficiency, which is beneficial to reducing the pixel center distance and the total area of ​​a single chip. Compared with the existing single-photon detectors, in order to improve the sensitivity of a single pixel, the diameter of a single pixel of the single-photon avalanche diode reaches tens of micrometers, which limits the spatial resolution and array size of the detector and increases the cost of fabrication. The present invention improves the upper limit of the array size of the single-photon detector.

[0050] (4) The quantum dot-nanowire avalanche diode single-photon detector of the present invention has the avalanche confined inside the quantum dot-nanowire unit, which effectively suppresses crosstalk between different pixels of the single-photon detector and reduces detector noise. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the structure of an embodiment of the quantum dot-nanowire avalanche diode single-photon detector of the present invention;

[0052] Figure 2 This is a flowchart of an embodiment of the fabrication method of the quantum dot-nanowire avalanche diode single-photon detector of the present invention.

[0053] The labels in the diagram are explained as follows:

[0054] 1-Detector N + Substrate, 2-N-type electrode, 3-semiconductor nanowire, 31-heavily doped N + Layer 32 - Undoped Type I layer, Layer 33 - Heavily doped P + 4-Porous nanomaterial layer, 5-Quantum dot material layer, 6-Passivation layer, 7-P-type electrode. Detailed Implementation

[0055] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0056] See Figure 1 This invention discloses a quantum dot-nanowire avalanche diode single-photon detector, comprising detector N. + Substrate 1, spaced apart and arranged in the detector N + The substrate 1 has multiple quantum dot-nanowire units on its surface, and also includes a passivation layer 6, a P-type electrode 7, and an N-type electrode 2. The aforementioned detector N... + Substrate 1 refers to a doping concentration range of 5 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 The N-type semiconductor layer.

[0057] Each of the above quantum dot-nanowire units comprises a semiconductor nanowire 3, a porous nanomaterial layer 4, and a quantum dot material layer 5. The semiconductor nanowire 3 comprises heavily doped N... + Layer 31, undoped type I layer 32, and heavily doped P + Layer 33; the above heavily doped N + Layer 31 typically refers to a doping concentration range of 5 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3The N-type semiconductor layer; the above-mentioned heavily doped P + Layer 33 typically refers to a doping concentration range of 5 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 The P-type semiconductor layer; the above-mentioned heavily doped N + Layer 31 is epitaxially grown on detector N + On the upper surface of substrate 1, its shape is a cone, wider at the bottom and narrower at the top; the undoped type I layer 32 is epitaxially grown on heavily doped N. + On the outer surface of layer 31, heavily doped N + Layer 31 covers the area, and its lower end face is adjacent to detector N. + A gap is left between the upper surfaces of substrate 1, and the distance of this gap meets the following condition: so that the undoped type I layer 32 and the detector N are aligned. + Electrical isolation is formed between substrates 1; the above heavily doped P + Layer 33 is epitaxially grown on the outer surface of undoped type I layer 32, covering undoped type I layer 32, and its lower end face is adjacent to detector N. + A gap is left between the upper surfaces of substrate 1, and the distance of this gap meets the following condition: allowing heavily doped P + Layer 33 and detector N + Electrical isolation is formed between substrates 1; for process simplicity, the heavily doped P in this embodiment is... + The lower end face of layer 33 and detector N + The distance between the upper surfaces of substrate 1 is greater than the distance between the lower end face of the undoped type I layer 32 and the detector N. + The distance between the upper surfaces of substrate 1. The aforementioned detector N. + The materials of substrate 1 and the aforementioned semiconductor nanowires 3 include, but are not limited to, silicon, germanium, or group III-V semiconductor materials; in this embodiment, detector N + Substrate 1 is made of silicon, and semiconductor nanowire 3 is made of indium phosphide (InP). A porous nanomaterial layer 4 is grown on the outer surface of the semiconductor nanowire 3, covering it. The material of the porous nanomaterial layer 4 includes, but is not limited to, surface defect materials and loosely structured two-dimensional materials; in this embodiment, the porous nanomaterial layer 4 is made of porous graphene. A quantum dot material layer 5 is coated on the outer surface of the porous nanomaterial layer 4, covering it. The material of the quantum dot material layer 5 includes, but is not limited to, lead sulfide, indium phosphide, cadmium selenide, or indium arsenide; in this embodiment, the quantum dot material layer 5 is made of indium arsenide (InAs). The quantum dot material layer 5 is used to absorb photons; the porous nanomaterial layer 4 is used to absorb photoexcitons and achieve electron-hole separation; the semiconductor nanowire 3 is used to achieve photogenerated carrier multiplication.

[0058] The passivation layer 6 fills the gaps between the quantum dot-nanowire units and the outer ring surrounding all the quantum dot-nanowire units; the upper surface of the passivation layer 6 is parallel to the detector N. + The passivation layer 6 is located on the upper surface of the substrate 1, with the top of the quantum dot-nanowire unit extending beyond the upper surface of the passivation layer 6. Preferably, the height of the top of the quantum dot-nanowire unit extending beyond the upper surface of the passivation layer 6 is greater than or equal to 10 nm and less than or equal to 1 μm. The material of the passivation layer 6 includes, but is not limited to, benzocyclobutene (BCB), SU-8 resin, or spin-coated glass. In this embodiment, the passivation layer 6 is made of spin-coated glass.

[0059] The aforementioned P-type electrode 7 is grown on the outer surface of the protruding portion extending from the top of each quantum dot-nanowire unit onto the upper surface of the passivation layer 6. Its lower surface is coplanar with the upper surface of the passivation layer 6, covering both the upper surface of the passivation layer 6 and the outer surface of the protruding portion extending from the top of each quantum dot-nanowire unit onto the upper surface of the passivation layer 6. The material of the P-type electrode 7 includes, but is not limited to, transparent conductive films such as ITO; in this embodiment, the P-type electrode 7 is a transparent conductive film made of ITO material.

[0060] The aforementioned N-type electrode 2 is grown on detector N. + The N-type electrode 2 is located on the upper surface of the substrate 1, and outside the outer contour of the passivation layer 6. The material of the N-type electrode 2 includes, but is not limited to, metals such as gold, aluminum, titanium, and nickel, or multi-metal stacks; in this embodiment, the N-type electrode 2 is a (titanium / gold stack) Ti / Au stack.

[0061] In addition, this invention also provides a method for fabricating the above-mentioned quantum dot-nanowire avalanche diode single-photon detector, see [link to documentation]. Figure 2 This includes the following steps:

[0062] Step 1: Based on the size and material requirements of the quantum dot-nanowire avalanche diode single-photon detector to be fabricated, prepare the detector N... + Substrate 1;

[0063] Step 2: The detector N prepared in step 1 + On the upper surface of substrate 1, gold nanoparticles are deposited by aerosol as epitaxial growth of heavily doped N. + The catalyst in layer 31; during aerosol deposition of gold nanoparticles, the concentration of gold nanoparticles in the aerosol is determined according to the requirements of the detector N in the quantum dot-nanowire avalanche diode single-photon detector to be prepared. + The number of quantum dot-nanowire units arranged at unit area intervals on the upper surface of substrate 1 is determined;

[0064] Step 3: In step 2, gold nanoparticles were deposited in the aerosol to form the detector N. + On the upper surface of substrate 1, heavily doped N is epitaxially grown.+ Layer 31, grown using methods including but not limited to chemical vapor deposition or molecular beam epitaxy, is arranged in a spaced pattern on detector N. + Multiple heavily doped N-type cones with a larger bottom and a smaller top on the upper surface of substrate 1 + Layer 31;

[0065] Step 4: The heavily doped N obtained in step 3 + On the outer surface of layer 31, an undoped type I layer 32 is epitaxially grown. The growth method includes, but is not limited to, chemical vapor deposition or molecular beam epitaxy, resulting in a layer spaced apart and grown on detector N. + Multiple outer surfaces on the upper surface of substrate 1 are covered by a heavily doped N-type layer 32 without doping. + Layer 31;

[0066] Step 5: The heavily doped N₂ obtained in step 4 has its outer surface covered by an undoped type I layer 32. + On the outer surface of each undoped type I layer 32 corresponding to layer 31, heavily doped P is epitaxially grown. + Layer 33, grown using methods including but not limited to chemical vapor deposition or molecular beam epitaxy, is arranged in a spaced pattern on detector N. + Multiple semiconductor nanowire prototypes on the upper surface of substrate 1;

[0067] Step 6: The heavily doped P corresponding to each of the above-mentioned semiconductor nanowire prototypes obtained in Step 5. + On the outer surface of layer 33, photoresist is spin-coated; then, a plasma ashing process is used to remove the heavily doped P atoms. + On the outer surface of layer 33, with detector N + The distance between the upper surfaces of substrate 1 is equal to the heavily doped P required in the quantum dot-nanowire avalanche diode single-photon detector to be fabricated. + The lower end face of layer 33 and detector N + The photoresist spin-coated portion is removed from the region above the lower contour line formed by the points spaced apart on the upper surface of substrate 1. Then, a metal deposition process is used to deposit metal on the overall outer surface of the semiconductor nanowire prototype, which retains the photoresist, on the lower outer surface. Finally, a lift-off process is used to remove the photoresist and the metal deposited on the photoresist's outer surface, resulting in a nanowire structure grown at intervals on detector N. + Semiconductor nanowire prototypes with metal masks deposited on multiple upper outer surfaces of the upper surface of substrate 1;

[0068] Step 7: Using a semiconductor wet etching process, expose the heavily doped P at the lower end of the semiconductor nanowire prototypes with metal masks deposited on their upper outer surfaces obtained in Step 6. +Layer 33 and the corresponding undoped type I layer 32 within it are removed to prevent heavy doping with P. + Layer 33 and undoped type I layer 32, with detector N + Substrate 1 generates electrical connections, eliminating leakage paths; then, a wet etching process is used to remove the metal mask deposited on the outer surface of each semiconductor nanowire prototype, resulting in a series of nanowires grown on detector N. + Multiple semiconductor nanowires 3 on the upper surface of substrate 1;

[0069] Step 8: On the outer surface of each of the semiconductor nanowires 3 obtained in step 7, a porous nanomaterial layer 4 is grown to cover each of the semiconductor nanowires 3; the growth method includes, but is not limited to, pulsed laser deposition, chemical vapor deposition or electrolytic etching, etc.

[0070] Step 9: On the outer surface of each of the porous nanomaterial layers 4 corresponding to the semiconductor nanowires 3 grown on the outer surface in step 8, a quantum dot material layer 5 is coated to cover each of the porous nanomaterial layers 4. The coating method includes, but is not limited to, spin coating, spray coating, etc., to obtain a quantum dot material layer 5 arranged at intervals on the detector N. + Multiple quantum dot-nanowire units on the upper surface of substrate 1;

[0071] Step 10: The gap positions between the quantum dot-nanowire units obtained in step 9 and the outer ring positions surrounding all the quantum dot-nanowire units are coated with passivation material and heat-treated to form a thermosetting polymer, i.e., passivation layer 6 is formed.

[0072] Step 11: Use an etching process to remove excess passivation material on the passivation layer 6 formed in step 10, so as to expose the top of each quantum dot-nanowire unit obtained in step 9; then grow a P-type electrode 7 on the outer surface of the protruding portion of the top of each quantum dot-nanowire unit extending from the upper surface of the passivation layer 6, and the growth method includes, but is not limited to, magnetron sputtering.

[0073] Step 12: On the outer surface of the protruding portion of the passivation layer 6 extending from the top of each quantum dot-nanowire unit in step 11, the detector N where the P-type electrode 7 is located is grown. + On the upper surface of substrate 1, at the position outside the outer contour of the passivation layer 6 formed in step 10, an N-type electrode 2 is grown. The growth method includes, but is not limited to, magnetron sputtering, electron beam evaporation, or conductive silver paste coating. The fabrication of the quantum dot-nanowire avalanche diode single-photon detector is completed.

[0074] In summary, the quantum dot-nanowire avalanche diode single-photon detector of the present invention effectively reduces the area per unit pixel while improving photon detection efficiency. This is beneficial for reducing pixel center-to-center distance and the total area of ​​a single chip, thereby increasing the upper limit of the single-photon detector array size. Furthermore, the fabrication method of the quantum dot-nanowire avalanche diode single-photon detector of the present invention is simple, the process parameters are easy to control, and the fabrication cost is low.

Claims

1. A quantum dot-nanowire avalanche diode single-photon detector, characterized in that: Including detector N + Substrates (1) are spaced apart and arranged in the detector N. + The substrate (1) has multiple quantum dot-nanowire units on its upper surface, and also includes a passivation layer (6), a P-type electrode (7), and an N-type electrode (2); Each of the quantum dot-nanowire units comprises a semiconductor nanowire (3), a porous nanomaterial layer (4), and a quantum dot material layer (5); The semiconductor nanowire (3) includes heavily doped N + Layer (31), undoped type I layer (32), and heavily doped P + Layer (33); the heavily doped N + Layer (31) is epitaxially grown on detector N + On the upper surface of the substrate (1), its shape is a cone, larger at the bottom and smaller at the top; the undoped type I layer (32) is epitaxially grown on a heavily doped N-type substrate. + On the outer surface of layer (31), heavily doped N + Layer (31) covers the area, and its lower end face is adjacent to detector N. + A gap is left between the upper surfaces of the substrate (1), and the distance of this gap meets the following condition: so that the undoped type I layer (32) and the detector N are separated. + Electrical isolation is formed between the substrates (1); the heavily doped P + Layer (33) is epitaxially grown on the outer surface of the undoped type I layer (32), covering the undoped type I layer (32), and its lower end face is adjacent to the detector N. + A gap is left between the upper surfaces of the substrate (1), and the distance of this gap meets the following condition: so that the heavily doped P + Layer (33) and detector N + Electrical isolation is formed between the substrates (1); The porous nanomaterial layer (4) is grown on the outer surface of the semiconductor nanowire (3), covering the semiconductor nanowire (3); the quantum dot material layer (5) is coated on the outer surface of the porous nanomaterial layer (4), covering the porous nanomaterial layer (4); the quantum dot material layer (5) is used to absorb photons; the porous nanomaterial layer (4) is used to absorb photogenerated excitons and realize the separation of electrons and holes; the semiconductor nanowire (3) is used to realize the multiplication of photogenerated carriers; The passivation layer (6) fills the gaps between each quantum dot-nanowire unit and the outer ring surrounding all the quantum dot-nanowire units. The upper surface of the passivation layer (6) is parallel to the detector N. + The top surface of the substrate (1) extends out of the passivation layer (6); The P-type electrode (7) is grown on the outer surface of the protruding portion of the top of each quantum dot-nanowire unit extending out of the upper surface of the passivation layer (6), and its lower surface is coplanar with the upper surface of the passivation layer (6), covering the upper surface of the passivation layer (6) and the outer surface of the protruding portion of the top of each quantum dot-nanowire unit extending out of the upper surface of the passivation layer (6). The N-type electrode (2) is grown on the detector N + On the upper surface of the substrate (1), and located outside the outer contour of the passivation layer (6).

2. The quantum dot-nanowire avalanche diode single-photon detector according to claim 1, characterized in that: The detector N + Substrate (1) refers to a doping concentration range of 5×10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer; The heavily doped N + Layer (31) refers to a doping concentration range of 5×10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer; The heavily doped P + Layer (33) refers to a doping concentration range of 5×10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 The P-type semiconductor layer.

3. The quantum dot-nanowire avalanche diode single-photon detector according to claim 1, characterized in that: The height of the quantum dot-nanowire unit extending from the top of the passivation layer (6) on the upper surface is greater than or equal to 10 nm and less than or equal to 1 μm.

4. The quantum dot-nanowire avalanche diode single-photon detector according to any one of claims 1 to 3, characterized in that: The detector N + The substrate (1) and the semiconductor nanowire (3) are made of silicon, germanium, or group III-V semiconductor materials; The porous nanomaterial layer (4) is made of a two-dimensional material; The quantum dot material layer (5) is made of lead sulfide, indium phosphide, cadmium selenide or indium arsenide; The passivation layer (6) is made of benzocyclobutene, SU-8 resin or spin-coated glass; The P-type electrode (7) is made of a transparent conductive film; The material of the N-type electrode (2) is a metallic material or a multilayer material of multiple metals.

5. The quantum dot-nanowire avalanche diode single-photon detector according to claim 4, characterized in that: The heavily doped P + The lower end face of layer (33) and detector N + The distance between the upper surfaces of the substrate (1) is greater than the distance between the lower end face of the undoped type I layer (32) and the detector N. + The distance between the upper surfaces of the substrate (1).

6. A method for fabricating a quantum dot-nanowire avalanche diode single-photon detector, characterized in that, Includes the following steps: Step 1: Based on the size and material requirements of the quantum dot-nanowire avalanche diode single-photon detector to be fabricated, prepare the detector N... + Substrate (1); Step 2: The detector N prepared in step 1 + On the upper surface of substrate (1), gold nanoparticles are deposited by aerosol as epitaxial growth of heavily doped N nanoparticles. + The catalyst of layer (31); when gold nanoparticles are deposited in aerosol, the concentration of gold nanoparticles in the aerosol is determined according to the requirements of the detector N in the quantum dot-nanowire avalanche diode single-photon detector to be prepared. + The number of quantum dot-nanowire units arranged at unit area intervals on the upper surface of the substrate (1) is determined; Step 3: In step 2, gold nanoparticles were deposited as detector N in the aerosol. + On the upper surface of substrate (1), heavily doped N is epitaxially grown. + Layer (31) is obtained by growing spaced-out layers on detector N. + Multiple heavily doped N-type cones with larger lower diameter and smaller upper diameter on the upper surface of substrate (1) + Layer (31); Step 4: The heavily doped N obtained in step 3 + On the outer surface of layer (31), an undoped type I layer (32) is epitaxially grown, resulting in a spaced arrangement grown on detector N. + The substrate (1) has multiple outer surfaces covered by an undoped type I layer (32) of heavily doped N. + Layer (31); Step 5: The heavily doped N₂ with its outer surface covered by an undoped type I layer (32) obtained in step 4. + On the outer surface of each undoped type I layer (32) corresponding to layer (31), heavily doped P is epitaxially grown. + Layer (33) is obtained by growing spaced-out layers on detector N. + Multiple semiconductor nanowire prototypes on the upper surface of substrate (1); Step 6: The heavily doped P corresponding to each semiconductor nanowire prototype obtained in Step 5 + Photoresist is spin-coated onto the outer surface of layer (33); Next, plasma ashing is used to aerate each heavily doped P + On the outer surface of layer (33) and detector N + The distance between the upper surfaces of the substrate (1) is equal to the heavily doped P required in the quantum dot-nanowire avalanche diode single-photon detector to be fabricated. + The lower end face of layer (33) and detector N + In the region above the lower contour line formed by the points spaced apart on the upper surface of the substrate (1), the spin-coated photoresist is removed; then, a metal deposition process is used to deposit metal on the overall outer surface of the semiconductor nanowire prototype with photoresist remaining on the lower outer surface; finally, a lift-off process is used to remove the photoresist and the metal deposited on the outer surface of the photoresist, resulting in a spaced arrangement grown on the detector N + Semiconductor nanowire prototypes with metal masks deposited on multiple upper outer surfaces of the substrate (1); Step 7: Using a semiconductor wet etching process, expose the heavily doped P at the lower end of the semiconductor nanowire prototypes with metal masks deposited on their upper outer surfaces obtained in Step 6. + Layer (33) and the corresponding undoped type I layer (32) inside it are removed to prevent heavy doping of P. + Layer (33) and undoped type I layer (32), with detector N + The substrate (1) generates electrical connections to eliminate leakage paths; then, a wet metal etching process is used to remove the metal mask deposited on the outer surface of each semiconductor nanowire prototype, resulting in a nanowire array grown on the detector N. + Multiple semiconductor nanowires (3) on the upper surface of substrate (1); Step 8: On the outer surface of each of the semiconductor nanowires (3) obtained in step 7, a porous nanomaterial layer (4) is grown to cover each of the semiconductor nanowires (3); Step 9: On the outer surface of the porous nanomaterial layer (4) corresponding to each of the semiconductor nanowires (3) after the porous nanomaterial layer (4) has been grown on the outer surface in step 8, a quantum dot material layer (5) is coated to cover each of the porous nanomaterial layers (4), resulting in a spaced arrangement of the porous nanomaterial layers (4) on the detector N. + Multiple quantum dot-nanowire units on the upper surface of substrate (1); Step 10: The gap positions between each quantum dot-nanowire unit obtained in step 9 and the outer ring positions surrounding all quantum dot-nanowire units are coated with passivation material and subjected to heat treatment to form a thermosetting polymer, i.e., a passivation layer (6). Step 11: Use an etching process to remove excess passivation material on the passivation layer (6) formed in step 10 to expose the top of each quantum dot-nanowire unit obtained in step 9; then grow a P-type electrode (7) on the outer surface of the protruding portion of the top of each quantum dot-nanowire unit that extends out of the upper surface of the passivation layer (6). Step 12: On the outer surface of the protruding portion of the passivation layer (6) extending from the top of each quantum dot-nanowire unit in step 11, the detector N where the P-type electrode (7) is located is grown. + On the upper surface of the substrate (1), an N-type electrode (2) is grown at the position outside the outer contour of the passivation layer (6) formed in step 10; thus completing the fabrication of the quantum dot-nanowire avalanche diode single-photon detector.

7. The method for fabricating a quantum dot-nanowire avalanche diode single-photon detector according to claim 6, characterized in that: In step 3, the epitaxial growth of heavily doped N + When growing layer (31), when growing undoped type I layer (32) epitaxially in step 4, and when growing heavily doped P layer epitaxially in step 5. + In layer (33), the growth methods are all chemical vapor deposition or molecular beam epitaxy.

8. The method for fabricating a quantum dot-nanowire avalanche diode single-photon detector according to claim 7, characterized in that: In step 8, when growing the porous nanomaterial layer (4), the growth method is pulsed laser deposition, chemical vapor deposition or electrolytic corrosion.

9. The method for fabricating a quantum dot-nanowire avalanche diode single-photon detector according to claim 8, characterized in that: In step 9, when coating the quantum dot material layer (5), the coating is carried out by spin coating or spray coating.

10. The method for fabricating a quantum dot-nanowire avalanche diode single-photon detector according to claim 9, characterized in that: In step 11, when growing the P-type electrode (7), the growth method is magnetron sputtering. In step 12, when growing the N-type electrode (2), the growth method can be magnetron sputtering, electron beam evaporation, or conductive silver paste coating.

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