Dynamic guard band with timing protection and performance protection

Abstract

Embodiments include, in response to monitoring the processor during operation, detecting a first amount of throttling amount in the processor, determining that the first amount of throttling amount satisfies a first condition with respect to a throttling amount threshold, and modifying a voltage level of the processor by a first amount. Embodiments include, in response to modifying the voltage level of the processor by the first amount, detecting a second amount of throttling amount in the processor, determining that the second amount of throttling amount satisfies a second condition with respect to a throttling amount threshold, and modifying the voltage level of the processor by the second amount.

Description

Background Art

[0001] The present invention relates generally to computer systems and, more particularly, to computer-implemented methods, computer systems and computer program products configured and arranged to provide dynamic guard bands with timing protection and / or performance protection.

[0002] In a distributed computing environment, there may be many jobs or queries that arrive as workloads to be processed on processors in the computing environment. A processor core is a processing unit that reads instructions to perform a specific action. The instructions are linked together so that when run in real time on the processor, the processor executes the desired workload formed by the instructions. A multi-core processor is a computer processor on a single integrated circuit with two or more separate processing units, which are cores, and each core reads and executes program instructions. The instructions are ordinary instructions (such as addition, moving data, branches, etc.), but a single processor can run instructions on separate cores at the same time, thereby increasing the overall speed of programs that support multithreading or other parallel computing techniques.

[0003] Problems may occur in the operation of a processor, and the core of the processor is operated to avoid the problem. A technique is needed to improve processor timing and / or performance. Summary of the invention

[0004] Embodiments of the present invention relate to computer-implemented methods for dynamic guard bands with timing protection and / or performance protection. A non-limiting computer-implemented method includes: in response to monitoring a processor during operation, detecting, by a computer, a first amount of throttling in the processor, and determining, by the computer, that the first amount of throttling satisfies a first condition about a throttling threshold. The method includes modifying, by the computer, a voltage level of the processor by a first amount, and in response to modifying the voltage level of the processor by the first amount, detecting, by the computer, a second amount of throttling in the processor. Additionally, the method includes determining, by the computer, that the second amount of throttling satisfies a second condition about the throttling threshold, and modifying, by the computer, the voltage level of the processor by the second amount.

[0005] This may provide an improvement over known methods of using static guard bands, which reduce performance degradation of a workload on a processor core by increasing the supply voltage of the processor core of the processor when the processing instructions of the workload become intensive or highly variable (noisy), thereby preventing the workload from having multiple (or subsequent) cycles with pending execution. Once the number of cycles with pending execution cycles decreases (or is zero), this indicates that the intensive or noisy phase of the workload is complete and the supply voltage can be reduced.

[0006] In addition to or as an alternative to one or more features described above or below, other embodiments of the present invention disclose that modifying the voltage level of the processor by a first amount includes increasing the voltage level of the processor by a first amount. This advantageously improves the instruction flow of the workload by increasing the supply voltage, which allows the processor core to avoid having cycles of suspended execution; this can also reduce circuit errors, resulting in a reduced rate of resume events, and can reduce the likelihood that the processor core will experience an unrecoverable error or an error detection shutdown that causes a service interruption.

[0007] In addition to or in lieu of one or more of the features described above or below, other embodiments of the invention disclose that modifying the voltage level of the processor by a second amount includes reducing the voltage level of the processor by a second amount. This advantageously reduces the power used by the processor core when the intensity or variability of the workload decreases.

[0008] In addition to or in lieu of one or more of the features described above or below, other embodiments of the invention disclose confirming that power usage is less than a power usage threshold before modifying a voltage level of a processor by a first amount. This advantageously confirms and ensures that power usage of a processor chip or processor is within tolerance before increasing the power supply voltage.

[0009] In addition to or in lieu of one or more of the features described above or below, other embodiments of the invention disclose checking whether power usage is greater than a power usage threshold, and in response to power usage being greater than the power usage threshold, denying a request to modify a voltage level by a first amount and maintaining the current voltage level. This advantageously prevents the power supply voltage from increasing when the power supply voltage has already increased to its maximum value and / or the processor chip / processor is approaching its maximum current or power usage.

[0010] In addition to or in lieu of one or more of the features described above or below, other embodiments of the present invention disclose providing a condition for reverting a voltage level to a default voltage level in response to determining that power usage is greater than a maximum power usage threshold. This advantageously prevents failure of a processor core and / or processor when its power usage is greater than a maximum value, thereby preventing power supply, voltage regulator, or chip failure that may cause service interruption or permanent damage to one or more system components.

[0011] Other embodiments of the present invention implement the features of the above-described methods in computer systems and computer program products.

[0012] Additional technical features and benefits are achieved through the technology of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered to be part of the claimed subject matter. For a better understanding, reference is made to the specific embodiments and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The details of the proprietary rights described herein are particularly pointed out and distinctly claimed in the claims at the end of the specification. The foregoing and other features and advantages of the embodiments of the present invention will become clear from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 depicts a block diagram of an example computer system for use in conjunction with one or more embodiments of the present invention;

[0015] Figure 2 depicts a block diagram of an example computer system configured to provide dynamic guard bands with timing protection and / or dynamic guard bands with performance protection for processor cores on a processor in accordance with one or more embodiments of the present invention;

[0016] Figure 3 is a flow chart of a process for using dynamic guard bands with timing protection for a processor according to one or more embodiments of the present invention;

[0017] Figure 4 is a flow chart of a process for using dynamic guard bands with timing protection for a processor according to one or more embodiments of the present invention;

[0018] Figure 5 is a flow chart of a process for using dynamic guard bands with performance protection for a processor according to one or more embodiments of the present invention;

[0019] Figure 6 is a flow chart of a process for using dynamic guard bands with performance protection for a processor according to one or more embodiments of the present invention;

[0020] Fig. 7A depicts a graph of voltage over time for a core executing a workload in accordance with one or more embodiments of the present invention;

[0021] Figure 7B depicts a graph of voltage over time for a core executing a workload in accordance with one or more embodiments of the present invention, wherein a voltage set point has been increased to a new voltage set point of a digital droop sensor trip point;

[0022] Fig. 8A depicts a graph of voltage over time for a core executing a workload in accordance with one or more embodiments of the present invention;

[0023] Figure 8B depicts a graph of voltage over time for a core executing a workload according to one or more embodiments of the present invention, wherein the supply voltage has been increased;

[0024] Fig. 9 is a flow chart of a computer-implemented method for dynamic guard bands with timing protection for a processor core of a processor according to one or more embodiments;

[0025] Fig.10 is a flow chart of a computer-implemented method for dynamic guard bands with performance protection for a processor core of a processor according to one or more embodiments;

[0026] Fig.11 depicts an example digital droop sensor according to one or more embodiments;

[0027] Fig.12 depicts a cloud computing environment according to one or more embodiments of the present invention; and

[0028] Fig.13 Abstract model layers in accordance with one or more embodiments of the invention are depicted. DETAILED DESCRIPTION

[0029] One or more embodiments of the present invention describe computer-implemented methods, computer systems, and computer program products configured and arranged to provide dynamic guard bands with timing protection and / or dynamic guard bands with performance protection for processor cores on a processor. The terms processor core, core, or core unit may be used interchangeably. The terms processor, chip, processor chip, and integrated circuit may be used interchangeably. Timing guard band protection allows the timing guard band to be reduced sometimes, which provides improved benefits, improved power dissipation, and / or improved timing margins for the core. Although timing margins may be discussed herein, it should be noted that one or more embodiments are equally applicable to timing and / or voltage margins. The digital droop sensor may be digital or analog, and may be a timing sensor or a voltage sensor. In one or more embodiments, the dynamic guard band with timing protection allows the processor to operate at its nominal voltage under normal conditions such as steady-state workloads, nominal temperatures, etc., with almost no voltage droop. Specifically, since power supply noise is minimal and there is no large voltage drop, the processor operates with a reduced guard band (i.e., with a reduced voltage margin and / or a reduced timing margin). This change in activity manifests as a worst-case voltage drop in situations where the workload switches directly from an idle state to a high activity workload (as discussed further in this article).

[0030] There are usually multiple critical circuit paths in the core that will fail and cause errors when the voltage at the circuit drops to a critical value. In cores designed for high robustness, there are error checking circuits that detect these errors. When an error is detected, the system can return to the checkpoint state before the error for a retry attempt. The result is that most errors are recoverable. Even though most circuit errors are recoverable, a high error recovery rate can affect performance. In addition, if there are errors during the error recovery process itself, this can result in unrecoverable errors, which can cause more serious system outages.

[0031] Without the technical benefit of one or more embodiments of the present invention, the way to address this is to (always) run at a constant voltage regulator set point voltage that is high enough to account for the worst-case voltage drop. The voltage set point required for each desired operating frequency is set during manufacturing testing of each chip and stored in a non-volatile memory called VPD (vital product data). Even if the voltage set point is kept constant, it is impossible to keep the voltage constant at the circuit level due to voltage regulator limitations as well as parasitic board, socket, and package resistances and inductances. When the VDD current increases rapidly over time (also known as di / dt), the power supply droops at the on-chip circuit locations. The voltage difference (i.e., Δ) from the voltage set point that causes the error to the actual voltage set point is called as discussed herein. Fig. 7A and Figure 7B The voltage margin depicted in .

[0032] Typically, critical paths speed up as voltage increases, so increasing voltage increases timing margin. During manufacturing testing, it was found that the Vmin workload worked without any circuit errors when the VDD set point was at or above the minimum value Vmin. In order to add margin during manufacturing testing to account for different workloads, temperature variations, device degradation at the end of life, etc., the VDD set point was increased by N% to Vmin + N * 0.01V, thereby generating a timing margin of N% (in V%) for the Vmin workload in the manufacturing environment of the Vmin workload. Next, each droop sensor was calibrated while running this Vmin workload so that the minimum output value of each droop sensor was calibrated to the expected value corresponding to the margin of N%. Next, a worst-case droop workload (with large di / dt events that cause worst-case droop) was run, and the droop sensors were tuned to mitigate these worst-case droops so that the minimum droop sensor output never dropped below the expected calibration value, thereby maintaining a margin of N% at each droop sensor location during the droop workload. The droop sensing tuning is tuned to provide a desired N% margin over a range of VDD set point values. At lower VDD set points, when running higher current workloads with larger di / dt events, the droop sensor will detect droop more often, and droop relief will be required more often to maintain the desired N% timing margin at each sensor location. Each droop relief event or period of constant droop relief typically results in a clock frequency reduction or instruction throttling, which may degrade performance. Therefore, after the droop sensor calibration and tuning, the next step is to select a VDD set point that is high enough so that droop relief events rarely occur, so that unacceptable performance loss does not occur for the selected performance workload. The calibration and tuning parameters of each droop sensor and the VDD set point that results in acceptable performance are stored in the VPD. If the Vmin workload, droop workload, and performance workload accurately reflect the customer environment, and if the power delivery network (PDN) and thermal environment in the manufacturing test environment accurately match the customer environment, there will also be N% timing margin in the customer application. Unfortunately, during manufacturing testing, it is difficult to predict and account for the characteristics of all customer workloads, PDNs, and thermal environments. Therefore, in order to ensure system reliability, the timing margin is typically increased by N%. This results in higher voltage and higher power. Voltage is typically limited due to device and dielectric long-term reliability considerations, and power is also limited by cooling capacity constraints. Therefore, increasing N% to increase the timing margin typically reduces chip efficiency and achievable system performance. One or more embodiments are configured to provide a reduction in timing margin, which is beneficial for static and dynamic power consumption and chip efficiency.In other words, the reduced timing margin allows the processor to run at a higher clock frequency, or alternatively, more cores or processors can be configured while remaining within voltage and power constraints, thereby improving the functionality of the computer system. Specifically, one or more embodiments use dynamic protection bands to address idle workloads (or small workloads) that require little or no processing, as well as extreme workloads that require intensive processing. The dynamic protection band uses a droop sensor trip point to address any changes in the devices on the chip, the chip itself, the power delivery network, the chip thermal environment, or the workload running on the chip, so that the dynamic protection band can be automatically changed (continuously) while running in a computing environment.

[0033] The droop sensors may be digital or analog and may sense voltage directly, or they may sense circuit delays that are sensitive to voltage as well as cycle time. In one or more embodiments, digital droop sensors that are sensitive to both voltage and cycle time are used. The digital delay sensor is calibrated by adding or subtracting delay elements from the delay line. Any type of analog or digital droop sensor may be used to calibrate and tune the droop sensor. In one embodiment, the droop sensor is calibrated using the Vmin workload, and then a separate tuning process is used to select a threshold to trigger a droop mitigation reaction in the event of a large and rapid droop in the worst case. In other embodiments, different methods and sequences may be used to calibrate and / or tune the droop sensor to provide the desired droop mitigation behavior. In addition, the droop sensor may be any kind of margin sensor, such as an analog timing sensor, a digital voltage sensor, or an analog voltage sensor. In general, any type of margin sensor may be utilized in one or more embodiments. Since the digital droop sensor is a timing margin sensor, the system may adjust the threshold of the timing margin sensor by adjusting / calibrating the delay of the digital droop sensor. It should be understood that other margin sensors with various thresholds may be used in one or more embodiments. In one or more embodiments, it may be found that timing or voltage margins are sensitive to temperature. Therefore, the system may adjust margin thresholds as a function of temperature to avoid recoverable errors even before they occur at high temperatures.

[0034] According to one or more embodiments, a dynamic guard band with performance protection prevents and / or reduces performance degradation of a core. A chip (e.g., a processor) has a given digital droop sensor trip point. Whenever a workload on the core causes a voltage level to cross the digital droop sensor trip point, a given performance degradation occurs. According to one or more embodiments, by increasing the voltage of the core, and under the configuration / assumption that the digital droop sensor trip point is (accurately) maintained at its voltage level, the distance between the new voltage set point of the chip and the digital droop sensor trip point is increased, such as Fig. 8A and Figure 8B This means then that for a workload that previously crossed the digital droop sensor trip point and therefore had an earlier performance hit, with the new voltage set point, the same workload will no longer cross the digital droop sensor trip point and therefore will no longer see performance degradation (e.g., performance hit). In this way, a dynamic guard band with performance protection can dynamically change the voltage set point (also referred to as VDD voltage, drain voltage, positive supply voltage) to provide dynamic performance protection.

[0035] In one or more embodiments, a dynamic guard band with timing protection that dynamically increases / decreases the calibration and tuning of the digital droop sensor within each core can be integrated with a dynamic guard band with performance protection that dynamically increases / decreases the voltage set point (e.g., VDD voltage) of the core. For the purpose of explanation and ease of understanding, the dynamic guard band with timing protection and the dynamic guard band with performance protection can be discussed separately, but it is conceivable that the functions of both are integrated for improving computer systems.

[0036] One or more embodiments of the present invention provide improvements to processors, and in particular, improvements to cores on processors. Optimized timing guard bands reduce the probability or rate of margin-related circuit errors while minimizing voltage and power for greater efficiency, while performance guard bands prevent performance degradation on processor cores due to excessive droop mitigation actions. By fine-tuning the operation of the cores on the processor during runtime, such operation of the cores results in improvements to the computer system itself, runtime being when the processor cores are executing instructions. Additionally, dynamic guard bands with timing protection and / or dynamic guard bands with performance protection are configured to operate the processor aggressively at a high level while reducing the probability or rate of recoverable or unrecoverable circuit errors.

[0037] Now go to Figure 1, generally illustrates a computer system 100 according to one or more embodiments of the present invention. The computer system 100 may be an electronic computer framework that includes and / or employs any number of computing devices and networks utilizing various communication technologies and combinations thereof, as described herein. The computer system 100 may be easily scalable, extensible, and modular, with the ability to change to different services or reconfigure some features independently of other features. The computer system 100 may be, for example, a server, a desktop computer, a laptop computer, a tablet computer, or a smart phone. In some examples, the computer system 100 may be a cloud computing node. The computer system 100 may be described in the general context of computer system executable instructions, such as program modules executed by the computer system. Typically, a program module may include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. The computer system 100 may be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

[0038] like Figure 1 As shown, the computer system 100 has one or more central processing units (CPUs) 101a, 101b, 101c, etc. (collectively or generally referred to as processors 101). Processor 101 may be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. Processor 101, also referred to as a processing circuit, is coupled to system memory 103 and various other components via system bus 102. System memory 103 may include read-only memory (ROM) 104 and random access memory (RAM) 105. ROM 104 is coupled to system bus 102 and may include a basic input / output system (BIOS) or its successor system, such as a unified extensible firmware interface (UEFI), which controls certain basic functions of computer system 100. RAM is a read-write memory coupled to system bus 102 for use by processor 101. System memory 103 provides temporary memory space for the operation of the instructions during operation. System memory 103 may include random access memory (RAM), read-only memory, flash memory, or any other suitable memory system.

[0039] Computer system 100 includes an input / output (I / O) adapter 106 and a communications adapter 107 coupled to system bus 102. I / O adapter 106 may be a small computer system interface (SCSI) adapter and / or any other similar component that communicates with hard disk 108. I / O adapter 106 and hard disk 108 are collectively referred to herein as mass storage 110.

[0040] Software 111 for execution on computer system 100 may be stored in mass storage 110. Mass storage 110 is an example of a tangible storage medium readable by processor 101 in which software 111 is stored as instructions executed by processor 101 to cause computer system 100 to operate, such as described herein below with respect to the various figures. Examples of computer program products and execution of such instructions are discussed in greater detail herein. Communications adapter 107 interconnects system bus 102 with network 112, which may be an external network, enabling computer system 100 to communicate with other such systems. In one embodiment, system memory 103 and a portion of mass storage 110 together store an operating system, which may be a coordinating Figure 1 The functionality of the various components shown in any suitable operating system.

[0041] Additional input / output devices are shown connected to system bus 102 via display adapter 115 and interface adapter 116. In one embodiment, adapters 106, 107, 115, and 116 may be connected to one or more I / O buses that are connected to system bus 102 via an intermediate bus bridge (not shown). Display 119 (e.g., a screen or display monitor) is connected to system bus 102 via display adapter 115, which may include a graphics controller to improve performance of graphics-intensive applications, as well as a video controller. Keyboard 121, mouse 122, speakers 123, etc. may be interconnected to system bus 102 via interface adapter 116, which may include, for example, a super I / O chip that integrates multiple device adapters into a single integrated circuit. Suitable I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols such as Peripheral Component Interconnect (PCI) and Peripheral Component Interconnect Express (PCIe). Thus, as shown in FIG. Figure 1 As configured, computer system 100 includes processing capabilities in the form of processor 101, as well as storage capabilities including system memory 103 and mass storage 110, input devices such as keyboard 121 and mouse 122, and output capabilities including speakers 123 and display 119.

[0042] In some embodiments, the communication adapter 107 can use any suitable interface or protocol to transmit data, such as an Internet Small Computer System Interface, etc. The network 112 can be a cellular network, a radio network, a wide area network (WAN), a local area network (LAN), or the Internet, etc. An external computing device can be connected to the computer system 100 through the network 112. In some examples, the external computing device can be an external network server or a cloud computing node.

[0043] It should be understood that Figure 1The block diagram is not intended to indicate that the computer system 100 will include Figure 1 Instead, computer system 100 may include Figure 1 Any suitable fewer or additional components not shown in the computer system 100 (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.) may be omitted. In addition, the embodiments described herein with respect to the computer system 100 may be implemented with any suitable logic, wherein the logic as mentioned herein may include any suitable hardware (e.g., a processor, an embedded controller or an application-specific integrated circuit, etc.), software (e.g., an application, etc.), firmware, or any suitable combination of hardware, software, and firmware in various embodiments.

[0044] Figure 2 A block diagram of an example computer system 202 is depicted, which is configured to provide dynamic guard bands with timing protection and / or dynamic guard bands with performance protection for processor cores on a processor according to one or more embodiments of the present invention. There may be multiple connected processors 204 forming a drawer, and there may be multiple drawers connected to each other. A computer system 202 with multiple processors 204 may be considered a drawer. Many features of the computer system 100 including hardware and software may be integrated in the computer system 202. The computer system 202 includes a processor 204, in which the details of an example processor are illustrated, and the processor 204 has multiple cores 220A-220N, where N represents the last number of the above elements. The processor cores 220A-220N may generally be referred to as processor cores 220. The processor cores 220A-220N each have their own digital droop sensors (DDS) 222A-22N, throttle meters 224A-224N, and firmware (FW) 226A-226N. The digital droop sensors 222A-222N may be generally referred to as digital droop sensors 222. The throttle meters 224A-224N may be generally referred to as throttle meters 224. Similarly, the firmware 226A-226N may be generally referred to as firmware 226.

[0045] One or more power circuits 230 are controlled by controller 232 to provide power to the various cores 220A-220N on processor 204. Firmware 236 can be used to control one or more operations of power circuit 230 and / or controller 232. In one or more embodiments, any one or more of firmware 226A-226N and firmware 236 can be configured as a (separate) state machine. For example, firmware 226A-226N and firmware 236 can be implemented as an on-chip state machine. Circuits that operate according to a specific sequence of events are called state machines or sequential circuits. The state machine requires memory to store information about past actions, and it uses this memory to help determine what action to take next.

[0046] Computer system 202 may include and / or represent various software applications, such as software 111, which may be executed as instructions on one or more processors 101 to perform according to one or more embodiments of the present invention. Although not shown, processor 204 includes all hardware and software elements that function as understood by those of ordinary skill in the art, including logic units, caches, registers, fetch circuits, decoding circuits, execution circuits, clocks, buses, etc. Computer system 202 may represent Fig.12 One or more portions of the cloud computing environment 50 depicted in FIG. Dynamic guard bands with timing protection and / or dynamic guard bands with performance protection may be incorporated and / or integrated in Fig.13 The hardware and software layers 60 are depicted in FIG. Fig.12 and Fig.13 Discussed further in this article.

[0047] For ease of understanding and not limitation, the example scenario will use core 220A to illustrate the use of dynamic guard bands with timing protection and / or with performance protection. By analogy, it should be understood that according to one or more embodiments, dynamic guard bands with timing protection and / or with performance protection can be executed concurrently in cores 220A-220N. Similarly, dynamic guard bands with timing protection and / or with performance protection can be executed concurrently in processor 204.

[0048] Figure 3 is a flow chart of a process 300 of using dynamic guard bands with timing protection for processor 204 according to one or more embodiments. Reference may be made to any of the figures discussed herein.

[0049] At block 302 of process 300, firmware 226A of core 220A is configured to monitor the operation of core 220. Firmware 226A may communicate with digital droop sensor 222A to monitor voltage droop (or drop) at core 220A as core 220A processes instructions of a workload. Firmware 226A may communicate with throttle meter 224A to monitor performance degradation of core 220A as the core processes the workload. Fig. 7A A graph of the voltage of core 220 executing a workload over time is depicted. Fig. 7AAs can be seen in FIG. 1 , the core 220 has a default digital droop trip point at a set voltage level (e.g., VPD). In one or more embodiments, each core 220A-220N may have the same digital droop trip point in their respective digital droop sensors 222A-220N. In one or more embodiments, one or more cores 220A-220N may be set to have different digital droop trip points, and / or the digital droop trip point of one or more cores may vary over time depending on their operation. When the core 220 operates above the digital droop trip point, there is no performance hit and no action is taken. In other words, the voltage level of the core has not yet dropped to the digital droop trip point. However, when the processor (or core 220) reaches or drops below the digital droop trip point, a suspend execution event is inserted into some cores 220. When the execution event of the core 220 is suspended, the effect is that those cores 220 no longer execute on every clock cycle, but pause for a given cycle. This alleviates voltage droop, but also affects performance. In other words, the execution of the instruction is delayed by a given clock cycle, thereby being identified as a suspended execution event.

[0050] exist Fig. 7A In the embodiment of the present invention, the core 220 may be allowed to have a predetermined number of voltage drops (drops) into the core recovery (region), but the core 220 is (never) allowed and / or prevented from dropping (dropping) into an error detection shutdown or an unrecoverable error (region). Core recovery is the process of resetting the core to the last known good architectural state (checkpoint state) on the processor 202. Core recovery may include clearing the cache (i.e., array built-in self-test (ABIST)), resetting the state machine, and restoring any shadow copies of the architectural registers to the last known good state. In other words, the processor 204 is configured to store the architectural state of a given register. When completed, the processor 204 is configured to reset a given core 220. In this way, the processor 204 is configured to clear the cache (which is done by ABIST), reset a given state machine to idle (IDLE), reload the architectural state to a given register, and then continue execution from there. All of this occurs when the core 220 remains in the running state.

[0051] If the core recovery is unsuccessful, a core unrecoverable error occurs. An unrecoverable error causes a bug check halt, which then stops the clock to that core 220, and the core 220 cannot progress forward. For some processors 204, there is a process of evacuating the workload still running on that core to a spare core, or if no spare core is available, adding that workload to an already running core 220.

[0052] Return to reference Figure 3, at block 304, the firmware 226A of the core 220A is configured to detect a core resume event. A core resume event occurs when instructions of a workload are being processed and the intensity or demand of the workload causes the voltage of the core 220 to sag to and / or below a core resume voltage threshold for core resume. Under normal conditions, such as steady state workload, nominal temperature, etc., the core 220 operates at its nominal voltage (e.g., at or near the supply voltage) with little to no voltage sag at all. In this case, when the workload switches from an idle state to a fully executed state (immediately), this change in activity manifests itself as a worst-case voltage sag, such as Fig. 7A The DDS trip point must be set above the error detection shutdown threshold because the DDS sensing time plus the droop mitigation reaction time allows the voltage to continue to droop after the voltage passes the DDS trip point.

[0053] In response to detecting a core recovery event, the firmware 226A of the core 220A is configured to run core recovery. The processor 204 is configured to run core recovery as discussed herein. In addition, the processor 204 can perform any core recovery process understood by a person of ordinary skill in the art.

[0054] At block 306, if the number of core recovery events within the set time period has reached or exceeded the core recovery event threshold, the process proceeds to block 308. If the number of core recovery events within the set time period has not reached or exceeded the core recovery event threshold, the process proceeds to block 302.

[0055] At block 308, the firmware 226A of the core 220A is configured to check whether the values ​​of one or more droop sensor calibration or tuning parameters in the digital droop sensor 222A have reached their maximum values. In other words, the firmware 226A may check whether the droop sensor calibration or tuning parameters are already at the maximum delay, which means that no further delay is expected. In one or more embodiments, block 308 may not be triggered until a predetermined number of core recovery events have occurred for the core. For example, 2 core recovery events may be used to trigger block 308 because the first recovery event may be an exception, but the second recovery event is an indication that further action is required for the core. In one or more embodiments, the predetermined number of core recovery events required to trigger block 308 may range from approximately 1 to 5 core recovery events.

[0056] For the droop sensor delay parameter, there can be a range of delay units. For example, the delay units can range from 0 to 255, where each delay unit can be 5 picoseconds (ps) of delay and / or where each delay unit corresponds to adding a delay element. For purposes of explanation, when the core has a cycle time of 4 GHz, the nominal value of the droop sensor delay parameter can be 100 delay units or 500 ps, ​​corresponding to two clock cycles of 250 ps each. Although example values ​​have been discussed, larger or smaller values ​​can be used for the delays of the delay units and the cycle time of the core. For purposes of illustration, Fig.11 An exemplary digital droop sensor in accordance with one or more embodiments is depicted. As discussed herein, a programmable delay can be increased (or decreased), wherein an increase in the programmable delay causes instructions of the workload to be delayed in their execution, and a decrease in the programmable delay causes instructions of the workload to not be delayed (or delayed less) in their execution. The programmable delay has a maximum value. The maximum delay can also be set to a delay to limit the voltage, current, and power increases that may result when the droop sensor delay is increased. When both timing protection and voltage protection are active, increasing timing protection as the droop sensor delay increases may result in more performance loss, and therefore may subsequently result in an increase in dynamic margin with performance protection VDD. In the absence of a limit on the DDS delay, this may result in exceeding voltage, current, or power limits, and may contribute to thermal runaway. Additionally, the larger the programmable delay setting, the more likely the signal will be lost through Fig.11 The edge detector circuit depicted in FIG. 1 propagates less (and detects lower edge values). Lower edge detection values ​​are associated with voltage sag events, and thus they trigger throttling of instruction execution. Thus, the programmable delay can be used to indirectly set a threshold for the voltage level that will trigger throttling.

[0057] At block 310, if (NO) the maximum value of the parameter has not been reached, the firmware 226A of the core 220A is configured to increase the delay value for the droop sensor calibration or tuning parameter in the digital droop sensor 220A. The digital droop sensor 222 (circuitry) has a delay element. To increase the digital droop trip point to Figure 7B, firmware 226A causes digital droop sensor 222 to increase the droop sensor delay and / or trigger threshold at the higher voltage set point depicted in . Increasing the DDS delay indirectly increases the voltage level of the trip point, or threshold that will trigger instruction execution throttling. An example nominal delay value is 100. Then, to increase the digital droop sensor trip point sensitivity, firmware 226A causes the value (of the digital droop sensor) to increase from 100 to 101, 102, 103, 104, etc., as required to control the rate of circuit errors and recovery events. When firmware 226A increases the digital droop sensor trip point, this causes the droop mitigation reaction to trigger execution throttling at a higher voltage. This throttling causes the voltage to stop drooping, and often to increase, which gives core 220 more timing margin during voltage droop or during high current operation under large workloads. In addition, firmware 226A is configured to dynamically reduce the timing margin when the rate of recovery events drops below a threshold, as shown below in Figure 4 This reduces the performance caused by droop mitigation command throttling. Since the performance loss is reduced, this can also create dynamic margin for performance conservation control loops with reduced voltage, thereby reducing current and power to improve efficiency.

[0058] like Figure 7B As further shown in FIG. 1 , a graph of the voltage of core 220 executing a workload over time is depicted, wherein the voltage set point, which is the digital droop sensor trip point, has been increased to a new digital droop sensor trip point. The new voltage set point corresponds to increasing the delay amount of core 220. Figure 7B As shown in , there is a maximum voltage that the digital droop sensor trip point can move from the original DDS sensor input corresponding to the original DDS delay stored in VPD. In one or more embodiments, the maximum voltage change in the voltage set point can be 10 millivolts (mV), 15mV, 20mV, 25mV, 30mV, etc. The firmware 226A can have a preset step size / increment to move the DDS delay and the resulting DDS sensor trip point until it stops at the maximum DDS delay. Note that when the clock frequency changes, the relationship between the DDS delay and the trip point voltage changes, so these figures represent operation at a single frequency. For example, for each restore event (or a preset number of restore events), the firmware 226A can move the DDS trip point up by a voltage level "J" mV, where J is the step size / increment, and where J can be 5mV, 10mV, etc., until the maximum voltage change has been reached for the digital droop sensor trip point.

[0059] Figure 4 is a flow chart of a process 400 for using dynamic guard bands with timing protection for processor 204 according to one or more embodiments. Figure 4 You can continue Figure 3At block 402 of process 400, firmware 226A of core 220A is configured to monitor the operation of core 220. Firmware 226A may communicate with digital droop sensor 222A to monitor voltage droop (or drop) at core 220A as core 220A processes a workload.

[0060] At block 404, the firmware 226A of the core 220A is configured to determine / check the number of core resume events within a predetermined time after an increase to a new / updated voltage level of the voltage set point. The predetermined time after the last increase in the voltage set point of the digital droop sensor trip point may range from about 3 minutes to about 50 minutes. As described herein, a core resume event may occur when instructions of a workload are being processed and the intensity or demand of the workload causes the voltage of the core 220 to droop to and / or below a core resume voltage threshold for core resume.

[0061] At block 406, the firmware 226A of the core 220A is configured to check whether the number of core resume events within a predetermined time has reached and / or dropped below a reduced latency core resume event threshold. In one or more embodiments, the reduced latency resume event threshold may be zero resume events within the predetermined time. In one or more embodiments, the reduced latency resume event threshold may be a number of core resume events that is less than the number of core resume events that caused the voltage set point of the digital droop sensor trip point to increase. In one or more embodiments, the reduced latency resume event threshold may be less than the number of core resume events that caused the voltage set point of the digital droop sensor trip point to increase. Figure 3 The predetermined number of core resume events required by block 308 in the predetermined time. If (No) the number of core resume events in the predetermined time does not reach and / or drop below the reduced latency core resume event threshold, the process returns to block 402 and monitoring of the processor 204 continues.

[0062] At block 408, if (is) the number of core resume events in a predetermined time has reached and / or dropped below the reduced latency core resume event threshold, the firmware 226A of the core 220A is configured to check whether the values ​​of one or more digital droop sensor delay parameters have reached their minimum values. The delay units may range from 0 to 255, such that the minimum value (or lowest value) of the digital droop sensor delay parameter is 0 and the maximum value is 255. It should be understood that different ranges may be utilized. If (is) the minimum value of the digital droop sensor delay parameter has been reached, the process returns to block 402.

[0063] At block 410, if (NO) the value of the digital droop sensor delay parameter has not reached its minimum value, the firmware 226A of the core 220A is configured to decrease the value of one or more digital droop sensor delay parameters by a predetermined amount, thereby decreasing the voltage set point of the digital droop sensor trip point. In one or more embodiments, the sensor trip point of the digital droop sensor trip point can be decremented in the same step size / unit that the DDS sensor point can be increased. The firmware 226A can have a preset step size / decrement to move the digital droop sensor trip point until it stops at the minimum digital droop sensor trip point. For example, the firmware 226A can move the digital droop sensor trip point down by a voltage level "J" mV, where J as a step size can be 5mV, 10mV, etc., until the amount of the maximum voltage change of the digital droop sensor trip point has been reached. In one or more embodiments, the firmware 226A can decrement the voltage set point of the digital droop sensor trip point by the amount of the entire maximum voltage change at one time. In one or more embodiments, the maximum voltage change may be 10 millivolts (mV), 15 mV, 20 mV, 25 mV, 30 mV, or the like.

[0064] In one or more embodiments, the firmware 226 of the core 220 is configured to run a digital droop sensor delay test on the digital droop sensor 222 as a manufacturing test or in the field, identify one or more digital droop sensor delay parameter sets, evaluate one or more digital droop sensor delay parameter sets, and load a preferred digital droop sensor delay parameter set. Evaluating one or more digital droop sensor delay parameter sets also includes the firmware 226 of the core 220 comparing one or more digital droop sensor delay parameter sets, identifying specific digital droop sensor delay parameters, and selecting the digital droop sensor delay parameter set with the lowest specific digital droop sensor delay parameter as the preferred digital droop sensor delay parameter set. The firmware 226 of the core 220 is configured to detect a first number of core resume events and a second number of core resume events using a timing check. The digital droop sensor delay parameters of the processor are selected from the group consisting of efficiency and power.

[0065] Figure 5 is a flow chart of a process 500 for using dynamic guard bands with performance protection for processor 204 according to one or more embodiments. Reference may be made to any of the figures discussed herein. Figure 5 and Figure 6In the example scenario of core 220A, for ease of understanding and consistency, it is possible to continue to use the example scenario of core 220A. Likewise, it should be understood that all cores 220A-220N of processor 204 simultaneously execute dynamic guard bands with performance protection and dynamic guard bands with timing protection, as discussed herein. Similarly, dynamic guard bands with performance protection and dynamic guard bands with timing protection can be executed simultaneously for processor 204 in computer system 202.

[0066] At block 502 of process 500, firmware 226A of core 220A is configured to monitor the operation of core 220. Firmware 226A may communicate with digital droop sensor 222A to monitor voltage droop (or drop) at core 220A when core 220A processes workload. Firmware 226A may communicate with throttle meter 224A to monitor performance degradation of core 220A when core processes workload. In one or more embodiments, droop mitigation may be achieved using frequency reduction instead of instruction throttling. In this case, performance loss is caused by core frequency reduction instead of instruction throttling. In this embodiment, a droop event causes frequency reduction instead of instruction throttling. In this embodiment, instead of monitoring instruction throttling to determine performance loss, firmware monitors frequency reduction to determine performance loss. In one or more embodiments, both instruction throttling and frequency reduction may be used concurrently to mitigate droop. In this way, firmware monitors both instruction throttling and frequency reduction to determine performance loss.

[0067] At block 504, firmware 226A of core 220A is configured to detect a first amount of throttling within a predetermined time to measure throttling. Throttling meter 224A measures the number of cycles of throttling metering activity within the predetermined time. In this case, the first throttling threshold may range from 1 to millions. In one or more embodiments, the throttling meter measures the number of throttling amounts within the predetermined time.

[0068] The throttle meter 224 is a circuit (which may include and / or be coupled to a counter) that provides an indication of how many suspended execution cycles are asserted to a corresponding core in the processor. Each throttle meter reading corresponds to a (single) suspended execution cycle. This number of suspended execution cycles scales with performance degradation. Thus, the degree of performance degradation of the core 220 directly corresponds to the predetermined number of suspended execution cycles that the core 220 is experiencing.

[0069] In one or more embodiments, the predetermined time for checking the throttle amount may range from microseconds to minutes or hours. In one or more embodiments, the predetermined time for checking the throttle amount may range from about 1 minute to about 1 hour. In one or more embodiments, the predetermined time for checking the throttle amount may move from a lower number, such as 1 minute, to a higher number, such as 5 minutes, when less throttle amount or no throttle amount is detected from a previous check.

[0070] At block 506, the firmware 226A of the core 220A is configured to check whether the first amount of throttling within the predetermined time for checking throttling has an associated performance degradation greater than a first performance degradation threshold. The first performance degradation threshold may be set to 1% performance degradation of the core 220A. In one or more embodiments, the first performance degradation threshold may range from about 0.1% performance degradation to about 3% performance degradation of the core 220A. The performance degradation of the first amount of throttling may correspond to a specific number of suspended execution cycles, and the firmware 226A may convert the number of suspended execution cycles of the core 220A into a percentage performance degradation, for example using a table in the firmware or elsewhere. The firmware 226A is configured to check whether the (percentage) performance degradation for the first amount of throttling or the number of suspended execution cycles is greater than the first performance degradation threshold, for example, greater than 1% performance degradation.

[0071] In one or more embodiments, the first performance degradation threshold may correspond to a suspended execution cycle threshold. In one or more embodiments, the firmware 226A may check whether a first amount of throttling with a number of suspended execution cycles (which may be no suspended execution cycles in one case) is greater than a first performance degradation threshold, which is the number of suspended execution cycles as a threshold.

[0072] At block 514, if (NO) the first amount of throttling within the predetermined time for checking the amount of throttling has an associated performance degradation that is not greater than the first performance degradation threshold, then the firmware 226A of the core 220A is configured to maintain the supply voltage at its current voltage level (i.e., its current voltage setting). For purposes of illustration, Fig. 8A A graph of the voltage of core 220 executing a workload over time is depicted. It can be seen that the workload has its peak or top value at the original / current supply voltage before the voltage drops to the core recovery (region). Based on blocks 506, 514, it is assumed that no changes are made to the supply voltage supplied to core 220A.

[0073] At block 508 , if (is) the first amount of throttling within the predetermined time for checking the throttling amount has an associated performance degradation greater than a first performance degradation threshold, firmware 226A of core 220A is configured to check whether power usage conditions are met to increase the supply voltage.

[0074] Core 220A is on processor (chip) 204. There can be multiple processor chips 204 in a drawer (or computer system 202). Drawers are interconnected to other drawers using known methods understood by those of ordinary skill in the art. The power usage (PSU) condition is that the PSU of the drawer containing core 220A is less than the power usage threshold (i.e., the drawer's PSU < PSU threshold). In one or more embodiments, the PSU threshold can be in a range from about 3000 watts (W) to about 3900W. If the power usage condition is not met (i.e., the drawer's PSU > PSU threshold), the process proceeds to box 514 without increasing the supply voltage of core 220A.

[0075] As an additional check for power usage conditions that may be optionally added to block 508, power usage may also include confirming that the PSU of the drawer (computer system 202) containing core 220A is not greater than the maximum power usage of the drawer. If not, then this portion of the condition is met or satisfied to increase the supply voltage of core 220A. On the other hand, if the PSU of the drawer (computer system 202) containing core 220A is greater than the maximum power usage of the drawer, the firmware 226A of core 220A is configured to cause the firmware 236 of the power circuit 230 to revert to the default settings for powering all cores 220A-220N in processor 204.

[0076] Furthermore, it is noted that firmware 236 may be integrated with controller 232 to control the supply voltages supplied to cores 220A-220N, respectively, on processor 204. In one or more embodiments, firmware 226 is in operative communication with firmware 236 of power circuit 240 to provide and change the supply voltages provided to cores 220A-220N.

[0077] At block 510, if the power usage conditions are met to increase the supply voltage (i.e., the drawer's PSU < PSU threshold) (and optionally including that the PSU of the drawer containing the core 220A is not greater than the maximum power usage of the drawer), the firmware 226A of the core 220A is configured to check whether the supply voltage supplied to the core 220A has been increased to the maximum supply voltage of the core 220A. As described herein, there are Fig. 8A and Figure 8BThe firmware 226A of the core 220A checks whether the supply voltage has been increased to the maximum supply voltage allowed. If (yes) the supply voltage supplied to the core 220A has been increased to the maximum supply voltage of the core 220A, the flow proceeds to block 514.

[0078] At block 512 , if (NO) the supply voltage supplied to core 220A has not yet increased to the maximum supply voltage of core 220A, the firmware 226A of core 220A is configured to increase the supply voltage supplied to core 220A by a predetermined amount / step size. Figure 8B 2 depicts a graph of voltage over time for a core 220 executing a workload in which the supply voltage has been increased. Figure 8B Increasing the supply voltage shifts the entire graph of the workload vertically upward by the increased voltage set point increment without requiring droop relief. Figure 8B In FIG. 1 , the dashed curve is an illustration of the old position of the workload graph, while the solid curve is the new position of the workload graph, showing that the peak is now at the new supply voltage (new VDD). Figure 8B , the digital droop sensor trip point remains at the voltage set point. Therefore, the voltage at the DDS sensor crosses the DDS trip point later in time, and the droop mitigation stops drooping at approximately the same minimum voltage. As mentioned herein, by increasing the supply voltage of the core 220, and under the assumption that the digital droop sensor trip point is accurately maintained at a fixed voltage level, the distance between the new supply voltage of the core 220 and the digital droop sensor trip point has increased, as shown in FIG. Figure 8B This in turn means that workloads that previously crossed the digital droop sensor trip point (and therefore took a performance hit) may now (with the new supply voltage setting) no longer cross the digital droop sensor trip point, and therefore will no longer see a performance hit / degradation. In general, the performance penalty will be reduced by increasing the VDD set point.

[0079] In one or more embodiments, the maximum change range of increasing the supply voltage to the core 220 can be from about 10mV-30mV. In one or more embodiments, there is a predetermined number of steps to increase the supply voltage to the core 220. In one or more embodiments, the predetermined amount / step to increase the supply voltage to the core 220 can be 4 steps, each step is 5mV for a maximum change of 20mV. In one or more embodiments, the processors 204 can collectively have a total maximum change of approximately 20mV (for all cores 220). In one or more embodiments, a drawer (or computer system 202) with multiple processors 204 can have a maximum number of predetermined amounts / steps. For example, if there are 20 predetermined steps for the drawer, each step is 5mV, then the drawer can increase a total of 100mV.

[0080] Figure 6 is a flow chart of a process 600 of using dynamic guard bands with performance protection for processor 204 according to one or more embodiments. Figure 6 You can continue Figure 5 600. Reference may be made to any of the figures discussed herein. At block 602 of process 600, firmware 226A of core 220A is configured to monitor the operation of core 220A. Firmware 226A may communicate with digital droop sensor 222A to monitor voltage droop (or drop) at core 220A as core 220A processes a workload. Firmware 226A may communicate with throttle meter 224A to monitor performance degradation of core 220A as the core processes a workload.

[0081] At block 604, the firmware 226A of the core 220A is configured to detect a second amount of throttling within a predetermined range. The second amount of throttling will be equal to or less than the first amount of throttling measured by the throttling meter 224A. The second amount of throttling may be 1, 2, 3, 4, 5, 6 to 10 times smaller than the first amount of throttling. As described herein, the predetermined time for checking the throttling amount may be approximately every 2 minutes. In one or more embodiments, the predetermined time for checking the throttling amount may range from approximately (a few) microseconds to 24 hours. In one or more embodiments, the predetermined time for checking the throttling amount may be moved from a lower number such as 2 minutes to a higher number such as 5 minutes when less throttling or no throttling is detected from a previous check.

[0082] At block 606, the firmware 226A of the core 220A is configured to check whether the second amount of throttling within the predetermined time for checking the throttling amount has an associated performance degradation that is less than a second performance degradation threshold. The second performance degradation threshold may be set to 0.1% performance degradation of the core 220A. In one or more embodiments, the second performance degradation threshold may be a range from about 0.00% performance degradation to about 1.0% performance degradation of the core 220A. Similar to the above discussion, the second amount of performance degradation of throttling may identify a specific number of suspended execution cycles, and the firmware 226A may convert the number of suspended execution cycles of the core 220A into a percentage performance degradation, for example, using a table in the firmware or elsewhere. The firmware 226A is configured to check whether the (percentage) performance degradation of the second amount of throttling or the number of suspended execution cycles is less than the second performance degradation threshold, for example, less than 0.1% performance degradation.

[0083] In one or more embodiments, the second performance degradation threshold may correspond to a suspended execution cycle threshold. In one or more embodiments, the firmware 226A may check whether the second amount of throttling with the number of suspended execution cycles (which may be no suspended execution cycles in one case) is less than the second performance degradation threshold, which is the number of suspended execution cycles (as a threshold).

[0084] At block 608, if (is) the second amount of throttling within the predetermined time for checking the throttling amount has an associated performance degradation less than a second performance degradation threshold, the firmware 226A of the core 220A is configured to reduce the supply voltage. Figure 5 The maximum change in the supply voltage to the core 220 and the predetermined amount / step for each increase discussed in , the same can be applied to reducing the supply voltage to the core. In one or more embodiments, the maximum change in the supply voltage to the core 220 can range from about 10mV-30mV. In one or more embodiments, there is a predetermined number of predetermined amounts / steps to reduce the supply voltage to the core 220. In one or more embodiments, the predetermined amount / step to reduce the supply voltage to the core 220 can be 4 steps, each step is 5mV for a maximum change of 20mV. In one or more embodiments, the processor 204 can collectively have a total maximum change (for all cores 220) of approximately 20mV.

[0085] In one or more embodiments, the supply voltage may be reduced to a default supply voltage setting. In one case, the default supply voltage setting may be Figure 8B The original supply voltage setting depicted in .

[0086] At block 610 , if (NO) the second amount of throttling within the predetermined time for checking the throttling amount has an associated performance degradation greater than a second performance degradation threshold, the firmware 226A of the core 220A is configured to maintain the supply voltage at the current setting.

[0087] Fig. 9 is a flow chart of a computer-implemented method 900 for dynamic guard bands with timing protection for a processor core 220 of a processor 204, according to one or more embodiments. Reference may be made to any of the figures discussed herein. At block 902, firmware 226 of a core 220 (of a computer system 202) is configured to detect a first number of core resume events in the processor 204 in response to monitoring the processor 204 during operation. The first number of core resume events is for a core 220, such as core 220A. In one or more embodiments, the first number (and the second number below) may be for cores 220A-220N collectively.

[0088] At block 904, the firmware 226 of the core 220 (of the computer system 202) is configured to determine that a first number of core resume events satisfies a first condition of a first core resume event threshold. For example, a predetermined number of core resume events may occur such that the first condition of the first core resume event threshold is satisfied, such as Figure 3 As described in box 308 in.

[0089] At block 906, the firmware 226 of the core 220 (of the computer system 202) is configured to modify the value of at least one digital droop sensor delay parameter (of the digital droop sensor 222) of the processor 204 by a first amount, the at least one digital droop sensor delay parameter affecting the execution of one or more instructions on the processor 204. For example, reference may be made to Figure 3 310 in the discussion. As a technical solution / benefit, the firmware 226 is configured to adjust the droop threshold (e.g., by increasing the delay in the digital droop sensor 222), which in turn increases the sensitivity to voltage droop and low voltage, thereby reducing the probability or rate of recovery events. Although the digital droop sensor 222 has a delay adjustment to adjust the droop threshold, one or more embodiments may utilize other kinds of droop sensors with voltage adjustment knobs (or parameters), or some other methods of adjusting (one or more) droop thresholds. For example, there may be an analog droop sensor that triggers a droop reaction for droop mitigation. Thus, according to one or more embodiments, the digital droop sensor parameters may be implemented as voltage adjustments (increases / decreases) that increase and decrease similarly to the delays in the digital droop sensor 222.

[0090] At block 908 , firmware 226 of core 220 (of computer system 202 ) is configured to detect a second number of core resume events in processor 204 in response to modifying the value of at least one digital droop sensor delay parameter (of digital droop sensor 222 ) by the first amount.

[0091] At block 910, the firmware 226 of the core 220 (of the computer system 202) is configured to determine that the second number of core resume events satisfies a second condition for a second core resume event threshold. For example, the second condition for the second core resume event threshold is satisfied (e.g., the delayed core resume event threshold is lowered), such as Figure 4 As discussed in block 406 of .

[0092] At block 912, the firmware 226 of the core 220 (of the computer system 202) is configured to modify the value of at least one digital droop sensor delay parameter of the processor by a second amount. Figure 4 Frame 410.

[0093] Modifying the value of at least one digital droop sensor delay parameter of processor 204 by a first amount includes increasing the value of at least one digital droop sensor delay parameter of the processor by a first amount. For example, firmware 226A may instruct digital droop sensor 222A to increase the value of at least one digital droop sensor delay parameter. Modifying the value of at least one digital droop sensor delay parameter of processor 204 by a second amount includes decreasing the value of at least one digital droop sensor delay parameter of the processor by a second amount. For example, firmware 226A may instruct digital droop sensor 222A to decrease the value of at least one digital droop sensor delay parameter.

[0094] The first condition for satisfying the first core resume event threshold includes a first number of core resume events being greater than the first core resume event threshold. For example, the firmware 226 may determine that a predetermined number of core resume events is greater than the first core resume event threshold, as discussed in block 308. The second condition for satisfying the second core resume event threshold includes a second number of core resume events being less than the second core resume event threshold. For example, the firmware 226 may determine that the number of core resume events within a predetermined time has dropped below a reduced latency core resume event threshold.

[0095] Modifying the value of at least one digital droop sensor delay parameter of processor 204 by a second amount includes reverting to a baseline value of at least one digital droop sensor delay parameter. Firmware 226 may instruct digital droop sensor 222 to revert to a baseline value of at least one digital droop sensor delay parameter. The baseline value may be 0 delays. The baseline value may be 100 delay elements. The second amount by which the value of at least one digital droop sensor delay parameter is reduced may be greater than the first amount, equal to the first amount, or less than the first amount. During operation of the processor, the control loop discussed herein may continue indefinitely. Moreover, although the recovery event may be for a core, it should be understood that the recovery event may be triggered by a recovery event in a circuit that is smaller or larger than a "core".

[0096] Fig.10 is a flow diagram of a computer-implemented method 1000 for dynamic guard bands with performance protection for a processor core 220 of a processor 204, according to one or more embodiments. Reference may be made to any of the figures discussed herein.

[0097] At block 1002, firmware 226 of core 220 (of computer system 202) is configured to detect a first amount of throttling in processor 204 in response to monitoring processor 204 during operation. The first amount of throttling is a predetermined amount of throttling meter reading of throttling meter 224. Figure 5 An example is discussed in block 504 of .

[0098] At block 1004, the firmware 226 of the core 220 (of the computer system 202) is configured to determine that the first amount of throttling satisfies a first condition regarding a throttling amount threshold. The first amount of throttling has an associated performance degradation. The first condition is satisfied because the associated performance degradation of the first amount of throttling is greater than a first performance degradation threshold, e.g., Figure 5 The first performance degradation threshold may be set to 1%, 2%, 3%, etc., performance degradation of core 220. The throttled first amount of performance degradation may correspond to a particular number of suspended execution cycles.

[0099] At block 1006, firmware 226 of core 220 (of computer system 202) is configured to modify a voltage level of processor 204 by a first amount. Firmware 226 may instruct and / or communicate with firmware 236 of power circuit 230 to modify the voltage level. Figure 5 An example of modifying the voltage level is depicted in block 512 of FIG.

[0100] At block 1008, firmware 226 of core 220 (of computer system 202) is configured to detect a second amount of throttling in processor 204 in response to modifying the voltage level of processor 204 by the first amount. The second amount of throttling is a predetermined threshold of throttling meter 224 after modifying (e.g., increasing) the voltage level.

[0101] At block 1010 , the firmware 226 of the core 220 (of the computer system 202 ) is configured to determine that a second amount of throttling satisfies a second condition regarding a throttling amount threshold.

[0102] The second amount of throttling has an associated performance degradation. The second condition is satisfied because the associated performance degradation of the second amount of throttling is less than a second performance degradation threshold, e.g. Figure 6 As discussed in block 606 of . As an example, the second performance degradation threshold may be set to 0.1% performance degradation of the core 220, or the second performance degradation threshold may be any number in the range from about 0.0% performance degradation to about 1.0% performance degradation of the core 220.

[0103] At block 1012 , the firmware 226 of the core 220 (of the computer system 202 ) is configured to modify the voltage level of the processor 204 by a second amount.

[0104] The firmware 226 may instruct and / or communicate with the firmware 236 of the power circuit 230 to modify the voltage level. Figure 6 An example of modifying the voltage level is depicted in block 608 of FIG.

[0105] Modifying the voltage level of processor 204 by a first amount may include increasing the voltage level of the processor by a first amount, e.g., Figure 5 Modifying the voltage level of processor 204 by a second amount includes decreasing the voltage level of the processor by a second amount, e.g., Figure 6 As depicted in box 608 of .

[0106] The firmware 226 of the core 220 is configured to confirm that the power usage is less than the power usage threshold before modifying the voltage level of the processor by a first amount. The firmware 226 of the core 220 is configured to check whether the power usage (PSU) is greater than the power usage threshold (e.g., block 508), and in response to the power usage being greater than the power usage threshold, deny (e.g., by the firmware 236 and / or the firmware 226) the request to modify the voltage level by the first amount, and maintain the current voltage level (e.g., block 514). The firmware 226 of the core 220 is configured to provide a condition for reverting the voltage level to a default voltage level in response to determining that the power usage is greater than the maximum power usage threshold. The first amount ranges from approximately 5 millivolts (mV) to 10 mV for modifying the voltage level of the processor 204.

[0107] It should be understood that although the present disclosure includes detailed descriptions about cloud computing, the implementation of the teachings recorded herein is not limited to cloud computing environments. Instead, embodiments of the present invention can be implemented in conjunction with any other type of computing environment now known or later developed.

[0108] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be quickly provisioned and released with minimal management effort or interaction with the provider of the service. The cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0109] Features are as follows:

[0110] On-demand self-service: Cloud consumers can unilaterally and automatically provision computing capacity (such as server time and network storage) as needed without manual interaction with the service provider.

[0111] Broad Network Access: Capabilities are available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0112] Resource pooling: The computing resources of a provider are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically allocated and reallocated based on demand. There is a sense of location independence, as consumers generally do not control or know the exact location of the provided resources, but are able to specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0113] Rapid elasticity: Capacity can be quickly and elastically provisioned (in some cases automatically) to quickly scale out and quickly released to quickly scale in. To the consumer, the capacity available for provisioning often appears to be unlimited and can be purchased in any quantity at any time.

[0114] Metered Services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the utilized services.

[0115] The service model is as follows:

[0116] Software as a Service (SaaS): The capability provided to the consumer is to use the provider's applications running on the cloud infrastructure. The applications are accessible from a variety of client devices through a thin client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure including the network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0117] Platform as a Service (PaaS): The capability provided to consumers is to deploy applications created or acquired by consumers using programming languages ​​and tools supported by the provider onto the cloud infrastructure. Consumers do not manage or control the underlying cloud infrastructure including networks, servers, operating systems and / or storage, but have control over deployed applications and possible configuration of the application hosting environment.

[0118] Infrastructure as a Service (IaaS): The capabilities provided to consumers are processing, storage, networking, and other basic computing resources on which consumers can deploy and run arbitrary software, which may include operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but have control over the operating system, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls).

[0119] The deployment model is as follows:

[0120] Private Cloud: The cloud infrastructure is operated only for the organization. It can be managed by the organization or a third party and can exist on-premises or off-premises.

[0121] Community cloud: The cloud infrastructure is shared by several organizations and supports a specific community with shared concerns (e.g., mission, security requirements, policies, and compliance considerations). It can be managed by the organization or a third party and can exist on-premises or off-premises.

[0122] Public cloud: Cloud infrastructure is available to the general public or large industrial groups and is owned by an organization that sells cloud services.

[0123] Hybrid cloud: A cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds).

[0124] Cloud computing environments are service-oriented, with an emphasis on statelessness, low coupling, modularity, and semantic interoperability. At the core of cloud computing is an infrastructure consisting of a network of interconnected nodes.

[0125] Reference now Fig.12, depicts an illustrative cloud computing environment 50. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 10, with which local computing devices used by cloud consumers, such as personal digital assistants (PDAs) or cellular phones 54A, desktop computers 54B, laptop computers 54C, and / or automotive computer systems 54N can communicate. The nodes 10 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks, such as the private clouds, community clouds, public clouds, or hybrid clouds described above in this document, or a combination thereof. This allows the cloud computing environment 50 to provide infrastructure, platforms, and / or software as a service for which cloud consumers do not need to maintain resources on local computing devices. It should be understood that Fig.12 The types of computing devices 54A-N shown in are intended to be illustrative only, and computing node 10 and cloud computing environment 50 may communicate with any type of computerized device over any type of network and / or network addressable connection (eg, using a web browser).

[0126] Reference now Fig.13 , showing the cloud computing environment 50 ( Fig.12 ) provides a set of functional abstraction layers. It should be understood in advance that Fig.13 The components, layers, and functions shown in are intended to be illustrative only, and embodiments of the present invention are not limited thereto. As depicted, the following layers and corresponding functions are provided:

[0127] The hardware and software layer 60 includes hardware and software components. Examples of hardware components include: host 61; server 62 based on RISC (Reduced Instruction Set Computer) architecture; server 63; blade server 64; storage device 65; and network and networking components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0128] Virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual servers 71 ; virtual storage 72 ; virtual networks 73 , including virtual private networks; virtual applications and operating systems 74 ; and virtual clients 75 .

[0129] In one example, the management layer 80 may provide the functionality described below. Resource provisioning 81 provides dynamic procurement of computing resources and other resources for performing tasks within a cloud computing environment. Metering and pricing 82 provides cost tracking when resources are utilized within a cloud computing environment, as well as billing or invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks, as well as protection for data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management so that the required service levels are met. Service level agreement (SLA) planning and fulfillment 85 provides pre-scheduling and procurement of cloud computing resources, where future demand for cloud computing resources is anticipated based on the SLA.

[0130] Workload layer 90 provides examples of functionality that can take advantage of a cloud computing environment. Examples of workloads and functionality that can be provided from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analytics processing 94; transaction processing 95; and workloads and functionality 96.

[0131] Various embodiments of the present invention are described herein with reference to the relevant drawings. Without departing from the scope of the present invention, alternative embodiments may be designed. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are described in the following description and drawings, it will be appreciated by those skilled in the art that many positional relationships described herein are independent of orientation when the described functions are maintained even when the orientation is changed. Unless otherwise indicated, these connections and / or positional relationships may be direct or indirect, and the present invention is not intended to be limited in this regard. Therefore, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect positional relationship. As an example of an indirect positional relationship, it is mentioned in this specification that forming layer "A" on layer "B" includes such a situation, wherein one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", as long as the relevant characteristics and functions of layer "A" and layer "B" are not substantially changed by the intermediate layer.

[0132] For the sake of brevity, conventional techniques related to making and using aspects of the present invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs for implementing the various technical features described herein are well known. Therefore, for the sake of brevity, many conventional implementation details are only briefly mentioned or omitted entirely herein without providing well-known system and / or process details.

[0133] In some embodiments, various functions or actions can occur at a given location and / or in conjunction with the operation of one or more devices or systems. In some embodiments, a portion of a given function or action can be performed at a first device or location, and the remainder of the function or action can be performed at one or more additional devices or locations.

[0134] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, element components, and / or groups thereof.

[0135] The corresponding structures, materials, actions, and equivalents of all means or step-plus-function elements in the following claims are intended to include any structure, material, or action for performing a function in combination with other claimed elements as specifically claimed. The present disclosure is presented for the purpose of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. The embodiments are selected and described in order to best explain the principles and practical applications of the present disclosure, and to enable other persons of ordinary skill in the art to understand the present disclosure of various embodiments with various modifications that are suitable for the specific purposes contemplated.

[0136] The figures described herein are illustrative. Without departing from the spirit of the present disclosure, there may be many variations of the figures or steps (or operations) described therein. For example, actions may be performed in different orders, or actions may be added, deleted or modified. In addition, the term "coupling" describes a signal path between two elements, and does not imply a direct connection between elements, without an intermediate element / connection therebetween. All of these variations are considered to be a part of the present disclosure.

[0137] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms "comprises," "comprising," "including," "containing," "having," "containing," or "having" or any other variation thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0138] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" is understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include both indirect "connections" and direct "connections."

[0139] The terms "about", "substantially", "approximately" and variations thereof are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time of filing this application. For example, "about" may include a range of ±8% or 5% or 2% of a given value.

[0140] The present invention may be a system, method and / or computer program product of any possible level of technical detail of the collection. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, and the computer-readable program instructions are used to cause a processor to perform various aspects of the present invention.

[0141] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove on which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be interpreted as a temporary signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0142] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0143] The computer-readable program instructions for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(e.g., Smalltalk, C++, etc.) and procedural programming languages ​​(e.g., "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform various aspects of the present invention, an electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit.

[0144] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It will be understood that each block of the flowchart illustrations and / or block diagrams and the combination of blocks in the flowchart illustrations and / or block diagrams can be implemented by computer-readable program instructions.

[0145] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0146] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0147] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention. In this regard, each frame in the flow chart or block diagram can represent a module, segment or part of an instruction, which includes one or more executable instructions for realizing the specified (one or more) logical functions. In some alternative embodiments, the function noted in the frame may not occur in the order noted in the figure. For example, the two frames shown in succession can actually be performed substantially simultaneously, or these frames can sometimes be performed in reverse order, depending on the functions involved. It will also be noted that each frame of the block diagram and / or flow chart illustration and the combination of frames in the block diagram and / or flow chart illustration can be implemented by a dedicated hardware-based system that performs a specified function or action or performs a combination of special hardware and computer instructions.

[0148] The description of various embodiments of the present invention has been shown for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over existing technologies on the market, or to enable other persons of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A computer-implemented method comprising: detecting, by a computer, a first amount of throttling in the processor in response to monitoring the processor during operation; Determining, by the computer, that a first amount of the throttling amount satisfies a first condition regarding a throttling amount threshold; modifying, by the computer, a voltage level of the processor by a first amount; detecting, by the computer, a second amount of throttling in the processor in response to modifying the voltage level of the processor by the first amount; Determining, by the computer, that a second amount of the throttling amount satisfies a second condition regarding the throttling amount threshold; as well as The voltage level of the processor is modified by the computer by a second amount. 2 . The computer-implemented method of claim 1 , wherein modifying the voltage level of the processor by the first amount comprises increasing the voltage level of the processor by the first amount. 3 . The computer-implemented method of claim 1 , wherein modifying the voltage level of the processor by the second amount comprises decreasing the voltage level of the processor by the second amount.

4. The computer-implemented method of any preceding claim, further comprising, before modifying the voltage level of the processor by the first amount, confirming that power usage is less than a power usage threshold.

5. The computer-implemented method of any preceding claim, further comprising checking whether power usage is greater than a power usage threshold; and In response to the power usage being greater than the power usage threshold, the request to modify the voltage level by the first amount is denied and a current voltage level is maintained.

6. The computer-implemented method of any preceding claim, further comprising providing a condition for reverting the voltage level to a default voltage level in response to determining that power usage is greater than a maximum power usage threshold.

7. The computer-implemented method of any one of the preceding claims, wherein the first quantity ranges from approximately 5 millivolts (mV) to 10 mV.

8. A system comprising: a memory having computer readable instructions; as well as A computer for executing the computer-readable instructions, the computer-readable instructions controlling the computer to perform operations comprising: responsive to monitoring a processor during operation, detecting a first amount of throttling in the processor; Determining that the first amount of the throttling amount satisfies a first condition regarding a throttling amount threshold; modifying a voltage level of the processor by a first amount; detecting a second amount of throttling in the processor in response to modifying the voltage level of the processor by the first amount; determining that a second amount of the throttling amount satisfies a second condition regarding the throttling amount threshold; and The voltage level of the processor is modified by a second amount. 9 . The system of claim 8 , wherein modifying the voltage level of the processor by the first amount comprises increasing the voltage level of the processor by the first amount.

10. The system of any preceding claim 8 to 9, wherein modifying the voltage level of the processor by the second amount comprises decreasing the voltage level of the processor by the second amount.

11. The system of any preceding claim 8 to 10, further comprising, before modifying the voltage level of the processor by the first amount, confirming that power usage is less than a power usage threshold.

12. The system of any one of the preceding claims 8 to 11, further comprising checking whether the power usage is greater than a power usage threshold; and In response to the power usage being greater than the power usage threshold, the request to modify the voltage level by the first amount is denied and a current voltage level is maintained.

13. The system of any preceding claim 8 to 12, further comprising providing a condition for reverting the voltage level to a default voltage level in response to determining that power usage is greater than a maximum power usage threshold.

14. The system of any of the preceding claims 8 to 13, wherein the first quantity ranges from about 5 millivolts (mV) to 10 mV.

15. A computer program product comprising a computer-readable storage medium having program instructions embodied therewith, the program instructions being executable by a computer to cause the computer to perform operations comprising: detecting, by the computer, a first amount of throttling in the processor in response to monitoring the processor during operation; Determining, by the computer, that a first amount of the throttling amount satisfies a first condition regarding a throttling amount threshold; modifying, by the computer, a voltage level of the processor by a first amount; detecting, by the computer, a second amount of throttling in the processor in response to modifying the voltage level of the processor by the first amount; Determining, by the computer, that a second amount of the throttling amount satisfies a second condition regarding the throttling amount threshold; as well as The voltage level of the processor is modified by the computer by a second amount.

16. The computer program product of claim 15, wherein modifying the voltage level of the processor by the first amount comprises increasing the voltage level of the processor by the first amount.

17. The computer program product of any of the preceding claims 15 to 16, wherein modifying the voltage level of the processor by the second amount comprises decreasing the voltage level of the processor by the second amount.

18. The computer program product of any preceding claim 15 to 17, further comprising, before modifying the voltage level of the processor by the first amount, confirming that power usage is less than a power usage threshold.

19. The computer program product of any preceding claim 15 to 18, further comprising checking whether power usage is greater than a power usage threshold; and In response to the power usage being greater than the power usage threshold, the request to modify the voltage level by the first amount is denied and a current voltage level is maintained.

20. The computer program product of any preceding claim 15 to 19, further comprising providing a condition for reverting the voltage level to a default voltage level in response to determining that power usage is greater than a maximum power usage threshold.

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