Method for forming semiconductor device using metal hard mask

Abstract

A method for forming a semiconductor device is disclosed. The method includes forming a first metal layer on top of an amorphous mask layer disposed on a substrate. The method includes forming a second metal layer extending along vertical sidewalls of the opening in the amorphous mask layer. The method includes forming a first recess extending partially into the substrate using the first metal layer and the second metal layer as a first etch mask. The method includes forming a third metal layer extending along a vertical sidewall of the first recess. The method includes forming a second recess below the first recess using the first to third metal layers as a second etch mask.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Non-Provisional Application No. 17 / 901,727, filed on September 1, 2022, and entitled “Method for Forming a Semiconductor Device Using a Metal Hard Mask,” the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates generally to hard masks for semiconductor processing, and in particular to metal hard masks for fabricating high aspect ratio geometries. Background Art

[0004] Semiconductor circuits continue to shrink to smaller areas. To increase the number of transistors and other semiconductor devices per unit area, manufacturers are now taking advantage of another dimension, i.e., the vertical third dimension (3D). For example, in a 3D NAND memory array, charge trapping flash transistors are stacked vertically on top of each other on the sidewalls of high aspect ratio openings. In a DRAM memory array, high aspect ratio DRAM trench capacitor openings are etched deeper and deeper into the semiconductor substrate to increase capacitance. Through silicon vias (TSVs) used to stack integrated circuit chips are made by etching high aspect ratio holes that pass completely through the substrate.

[0005] Etch masks used to etch high aspect ratio openings such as trenches and holes require high mask-to-substrate etch selectivity to maintain pattern integrity throughout the extended high aspect ratio opening etch. Because the etch selectivity of photoresist may be insufficient, the photoresist pattern is etched into a hard mask, and the hard mask pattern is used as an etch mask when etching high aspect ratio features. Summary of the invention

[0006] At least one aspect of the present disclosure relates to a method for forming a semiconductor device. The method includes forming a first metal layer on top of an amorphous mask layer disposed on a substrate. The method includes forming a second metal layer extending along a vertical sidewall of an opening in the amorphous mask layer. The method includes using the first metal layer and the second metal layer as a first etching mask to form a first recess extending partially into the substrate. The method includes forming a third metal layer extending along the vertical sidewall of the first recess. The method includes forming a second recess below the first recess using the first to third metal layers as a second etching mask.

[0007] The first to third metal layers may each include a refractory metal.

[0008] The second and third metal layers may each include a metal material selected from the group consisting of tungsten, titanium, tantalum, molybdenum, chromium, hafnium, ruthenium, and combinations thereof. In one embodiment, the second and third metal layers each include titanium and tungsten.

[0009] The first to third metal layers may each include tungsten or tungsten nitride.

[0010] In some embodiments, the first to third metal layers are made of the same metal material.

[0011] The amorphous mask layer may include amorphous carbon or amorphous silicon.

[0012] According to the technology, the first recess has a first aspect ratio of its depth to its width, and the second recess has a second aspect ratio of its depth to its width, and wherein the second aspect ratio is substantially greater than the first aspect ratio.

[0013] The substrate may consist of a single dielectric layer having silicon oxide.

[0014] Additionally or alternatively, the substrate is composed of a plurality of alternately stacked first and second dielectric layers, the first dielectric layers each having silicon dioxide and the second dielectric layers each having silicon nitride or silicon oxynitride.

[0015] The method further includes filling the first and second recesses with a semiconductor material or a metal material.

[0016] At least another aspect of the present disclosure relates to a method for forming a semiconductor device. The method includes forming a low stress mask layer on a substrate. The method includes forming a first metal layer including a first metal on the low stress mask layer. The method includes forming an opening in the first metal layer and the low stress mask layer. The method includes forming a first portion of a metal spacer including a second metal along a sidewall of the opening. The method includes etching the substrate using the first metal layer and the first portion of the metal spacer as a first etching mask to form a first recess. The method includes forming a second portion of the metal spacer including a third metal along the sidewall of the first recess. The method includes again etching the substrate using the first metal layer and both the first and second portions of the metal spacer as a second etching mask to form a second recess below the first recess.

[0017] The method further includes: depositing a second metal layer; and etching a horizontally extending portion of the second metal layer to form the first portion of the metal spacer.

[0018] The method further includes: depositing a third metal layer; and etching a horizontally extending portion of the third metal layer to form the second portion of the metal spacer.

[0019] In some embodiments, the first through third metals each comprise a refractory metal.

[0020] The method further includes filling the first and second recesses with a semiconductor material or a metal material. The method further includes forming features of a three-dimensional (3D) memory cell based on the semiconductor material or the metal material filling the first and second recesses.

[0021] The first recess has a first aspect ratio of its depth to its width, and the second recess has a second aspect ratio of its depth to its width, and wherein the second aspect ratio is substantially greater than the first aspect ratio.

[0022] Yet another aspect of the present disclosure relates to an apparatus for forming a semiconductor device. The apparatus includes: a first chamber configured to accommodate a substrate overlaid by a mask layer and to deposit a first metal layer on the mask layer; a second chamber configured to form an opening through the first metal layer and the mask layer; a third chamber configured to deposit a second metal layer to extend along a vertical sidewall of the opening; a fourth chamber configured to etch a horizontal portion of the second metal layer; a fifth chamber configured to form a first recess extending into the substrate based at least on a remaining vertical portion of the second metal layer; a sixth chamber configured to deposit a third metal layer to extend along a vertical sidewall of the first recess; a seventh chamber configured to etch a horizontal portion of the third metal layer; and an eighth chamber configured to form a second recess further extending into the substrate based at least on a remaining vertical portion of the third metal layer.

[0023] The first chamber, the third chamber and the sixth chamber may be the same chamber.

[0024] These and other aspects and implementations are discussed in detail below. The above information and the following detailed description include illustrative examples of various aspects and implementations, and provide an overview or framework for understanding the nature and characteristics of the claimed aspects and implementations. The accompanying drawings provide an explanation and further understanding of the various aspects and embodiments, and are incorporated into and constitute a part of this specification. Various aspects can be combined, and it will be readily understood that the features described in the context of one aspect of the present invention can be combined with other aspects. Various aspects can be implemented in any convenient form. As used in the specification and claims, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" include plural references. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Non-limiting embodiments of the present disclosure are described by way of example with reference to the accompanying drawings, which are schematic and are not intended to be drawn to scale. Unless indicated as representing prior art, the drawings represent aspects of the present disclosure. For purposes of clarity, not every element may be labeled in every drawing. In the drawings:

[0026] Figure 1 A flow chart of a method for forming a semiconductor device using a metal shell hard mask according to various embodiments is presented.

[0027] Figure 2-13 Demonstrates various embodiments of Figure 1 sectional views of a semiconductor device manufactured by the method shown in during various manufacturing stages. DETAILED DESCRIPTION

[0028] Reference will now be made to the illustrative embodiments depicted in the accompanying drawings, and specific language will be used herein to describe these embodiments. However, it will be understood that it is not intended to limit the scope of the claims or the present disclosure. Changes and further modifications to the inventive features shown herein that would occur to those skilled in the relevant art and to those skilled in the art who have access to the present disclosure, as well as additional applications of the principles of the subject matter shown herein, will be considered to be within the scope of the subject matter disclosed herein. Other embodiments may be used and / or other changes may be made without departing from the spirit or scope of the present disclosure. The illustrative embodiments described in the detailed description are not meant to limit the subject matter presented.

[0029] Hard masks for etching high aspect ratio grooves and holes can be formed relatively thick to allow only vertically oriented atoms and ions from the etching gas to impact on the surface of the substrate. Although hard masks made of metals such as tungsten (W), titanium-tungsten (TiW) or titanium nitride (TiN) can provide the desired selectivity, the stress generated by the thick metal layer may be excessive. Hard masks made of thick low stress materials such as amorphous carbon and amorphous silicon can provide acceptable stress, but have low selectivity when etching deep high aspect ratio grooves and holes. Due to the lower selectivity, a very thick layer of amorphous material must be deposited, which may still not be enough to protect the underlying material.

[0030] Gas mixtures such as Ar and O2 and fluorinated hydrocarbons such as C4F8, C4F6 and C3F8 are commonly used to etch high aspect ratio features in dielectrics such as silicon dioxide. Fluorinated hydrocarbons such as CHF3, CH3F and CH2F2 are commonly used to etch high aspect ratio features into dielectrics such as silicon nitride (SiN). Features such as openings with a depth-to-width ratio greater than 20 are generally considered to be high aspect ratio features. Because the selectivity of the hard mask relative to the substrate is low, fluorocarbons with a higher carbon content can be added to the etching chemistry to improve the selectivity between the mask material (e.g., amorphous hard mask) and the material being etched. Fluorocarbon gases with a higher carbon content increase the hard mask selectivity by increasing polymer deposition on the surface of the amorphous hard mask. Unfortunately, during the etching of high aspect ratio features, polymers may also be deposited on the sidewalls of these high aspect ratio features, resulting in a gradual narrowing on the sidewalls, which results in a reduction in the bottom dimension and deformation of the feature. For example, the bottom critical dimension (CD) of the opening formed may be much smaller than the top CD of the opening.

[0031] The present disclosure provides various embodiments of methods for forming (e.g., etching) high aspect ratio geometries using a metal shell hard mask. In various embodiments, the metal shell hard mask does not induce significant stress and can use a low polymer forming fluorocarbon gas to provide high hard mask selectivity relative to the substrate. As disclosed herein, the metal shell hard mask is first formed by covering the surface of a low stress mask material with a first thin metal shell. Based on the first thin metal shell (which forms a first portion of a metal spacer), a first recess can be formed in the underlying dielectric layer. The disclosed metal shell hard mask can then be formed by forming a second portion of a metal spacer. Using the first and second portions of the metal spacer together, a second recess having a high aspect ratio (of its depth and width) can be formed in the dielectric layer below the first recess.

[0032] Figure 1 A flow chart of an example method 100 for forming a metal shell hard mask and fabricating a semiconductor device according to various embodiments is presented. Figure 2-13 is a cross-sectional view of such a semiconductor device 200, describing Figure 1 Some of the main operations described in method 100 of . For example, features (e.g., openings) with high aspect ratios are formed (e.g., etched) into one or more dielectric layers disposed on a semiconductor substrate. Such high aspect ratio openings can be rectangular, square, circular (such as in contacts), or any other regular or irregular shape. In various embodiments, the high aspect ratio openings can be trenches or holes.

[0033] refer to Figure 1 Operation 102 and Figure 2, a plurality of metal shell hard mask layers 202 are deposited on a substrate 200. The substrate 200 may include a semiconductor substrate 206 having an overlying dielectric layer 208. Although the dielectric layer 208 is shown as a single layer, it should be understood that the dielectric layer 208 may include multiple layers stacked on top of each other.

[0034] In various embodiments, semiconductor substrate 206 may be a single crystal semiconductor substrate such as a single crystal silicon wafer or a silicon-on-insulator substrate. As described above, in some embodiments, dielectric layer 208 may be a single dielectric layer having silicon oxide. In some other embodiments, dielectric layer 208 may include a plurality of alternating stacked first dielectric layers and second dielectric layers, wherein each of the first dielectric layers has silicon dioxide and each of the second dielectric layers has silicon nitride or silicon oxynitride. For such embodiments, the nitride-based second dielectric layer may be later replaced by a metal layer, and the oxide-based first dielectric layer may be used as an isolation layer between these metal layers.

[0035] In various embodiments, the metal shell hard mask layer 202 includes an amorphous mask layer 210, such as amorphous carbon or amorphous silicon, covered with a thin first metal shell layer 212. The amorphous mask layer 210 can be deposited using a spin coating process and can include, for example, spin-coated carbon. In various embodiments, the amorphous mask layer 210 can be formed as a low stress mask material, which has a relatively low intrinsic stress due to the relaxation of the amorphous material. For example, the intrinsic stress of the low stress mask material (as measured, for example, by a wafer bow test) can be less than + / -20MPa, and preferably close to zero. The first metal shell layer 212 can include refractory metals, such as tungsten, molybdenum, niobium, tantalum, titanium, chromium, hafnium, ruthenium and zirconium, including oxides, nitrides, and oxynitrides of refractory metals. In one embodiment, the first metal shell layer 212 can include tungsten (W), tungsten nitride (WN), titanium tungsten (TiW), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum, and carbides such as tungsten carbide. In various embodiments, the first metal shell layer 212 may be deposited using various thin film deposition techniques (eg, physical vapor deposition, chemical vapor deposition, atomic layer deposition) and other techniques (eg, sputtering, evaporation, etc.).

[0036] The thickness of the amorphous mask layer 210 is generally determined by the depth of the high aspect ratio openings (e.g., trenches or holes) to be etched into the dielectric layer 208. The thickness of the first metal shell layer 212 can be in the range of about 2 nanometers (nm) to 500 nm or more. Generally, the thickness of the first metal shell layer 212 can depend on the stress of the amorphous mask layer 210 and the size of the openings formed.

[0037] exist Figure 1 Operation 104 and Figure 3In the cross-sectional view in FIG. 2 , a metal etching hard mask layer 214 is deposited on the first metal shell layer 212. The metal etching hard mask layer 214 is a hard mask layer that is mainly used as an etching mask when etching the first metal shell layer 212. The metal etching hard mask layer 214 can be a dielectric layer, such as SiO2, SiON or SiN and is deposited by known deposition techniques, including vapor deposition techniques such as physical vapor deposition, chemical vapor deposition, plasma enhanced vapor deposition and atomic layer deposition.

[0038] Next reference Figure 1 Operation 106 and Figure 4 , a photomask layer 204 is deposited on a metal etch hard mask layer 214. The photomask layer 204 may be a three-layer photomask (eg, Figure 4 ). However, it should be understood that the photomask layer 204 may include any suitable single layer or any number of stacked layers while still within the scope of the present disclosure. After forming the topmost layer of the photomask layer 204 (e.g., the photoresist layer 220), an opening 222 is formed in the photoresist layer 220 using a suitable photolithography technique.

[0039] Next reference Figure 1 Operation 108 and Figure 5 , an opening 222 is etched through the anti-reflective coating 218, through the bottom organic layer 216, and through the metal etch hard mask layer 214. In some embodiments, the opening 222 may stop at the first metal shell layer 212. The opening 222 may be etched using any suitable anisotropic etching process such as reactive ion etching.

[0040] Next reference Figure 1 Operation 110 and Figure 6 , after the pattern is transferred to the metal etch hard mask layer 214 (e.g., by extending the opening 222 in operation 108), the photomask layer 204 can be removed from the metal etch hard mask layer 214. Next, an anisotropic etching process using the metal etch hard mask layer 214 as an etching mask can further extend the opening 222 through the metal shell hard mask layer 202 including the first metal shell layer 212 and the amorphous mask layer 210, as shown in FIG. Figure 6 In some embodiments, the opening 222 may stop at the dielectric layer 208 .

[0041] Next reference Figure 1 Operation 112 and Figure 7, after transferring the pattern to the metal shell hard mask layer 202 (e.g., by extending the opening 222 in operation 110), the metal etch hard mask layer 214 may be removed using a dry plasma etch or a wet etch. In some embodiments, a wet etch with high selectivity may be used to remove the metal etch hard mask layer 214 relative to the dielectric layer 208. For example, when the dielectric layer 208 is SiO2 and the metal etch hard mask layer 214 is SiN, hot phosphoric acid may be used to remove the SiN without significant loss of the underlying SiO2 layer.

[0042] Next reference Figure 1 Operation 114 and Figure 8 In the cross-sectional view in FIG. 2 , the second metal shell layer 230 is conformally deposited on the horizontal and vertical surfaces of the metal shell hard mask layer 202. The second metal shell layer 230 may include refractory metals such as tungsten, molybdenum, niobium, tantalum, titanium, chromium, hafnium, ruthenium and zirconium. In one embodiment, the second metal shell layer 230 may be a material such as tungsten (W), tungsten nitride (WN), titanium tungsten (TiW), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), molybdenum and carbides such as tungsten carbide. In various embodiments, the second metal shell layer 230 may be deposited using various thin film deposition techniques (such as physical vapor deposition, chemical vapor deposition, atomic layer deposition) and other techniques (such as sputtering, evaporation, etc.). The thickness of the second metal shell layer 230 may be about 2 nm or thicker, for example, 1 nm to 10 nm in one embodiment.

[0043] Next reference Figure 1 Operation 116 and Fig. 9 , anisotropic etching removes the second metal shell 230 from the horizontal surface, forming a first portion 232 of the metal spacer in the opening 222. Specifically, the second metal shell 230 is removed from the top surface of the substrate 200 to expose the dielectric layer 208 and from the top surface of the first metal shell 212 to expose its top surface. In anisotropic etching, a bias is applied to accelerate ions in the etching gas plasma toward the substrate. The vertical trajectory of the ions causes the horizontal surface to be etched much faster than the vertical surface.

[0044] In various embodiments, the second metal shell layer 230 may be the same material as the first metal shell layer 212. Using the same metal shell material for the first metal shell layer 212 and the second metal shell layer 230 may advantageously reduce production costs by using the same metal deposition tool, which may reduce cycle time and capital costs. In these embodiments, the anisotropic etching process must be carefully controlled to prevent the first metal shell layer 212 from being completely removed from the horizontal surface. In other embodiments, the first metal shell layer 212 material and the second metal shell layer 230 material may be different. These embodiments may increase equipment costs due to the need to deposit two different metals, but the process control is relaxed. The anisotropic etching process window is significantly increased because the first metal shell layer 212 can be selected to have a high selectivity so as not to be removed when etching the second metal shell layer 230. This can ensure that no portion of the dielectric layer 208 is covered by any remaining second metal shell layer 230.

[0045] Next reference Figure 1 Operation 118 and Fig.10 , after forming the first portion 232 of the metal spacer, the first recess 238 can be formed to partially extend into the dielectric layer 208 based on the metal shell hard mask layer 202, which includes the amorphous mask layer 210, the first metal shell layer 212 and the first portion 232 of the metal spacer. For example, using the metal shell hard mask layer 202 as an etching mask, anisotropic etching removes the upper portion of the dielectric layer 208 through the opening 222, thereby forming the first recess 238 below the opening 222. In anisotropic etching, a bias is applied to accelerate ions in the etching gas plasma toward the substrate. The vertical trajectory of the ions causes the horizontal surface to etch much faster than the vertical surface. As a non-limiting example, the first recess 238 can have a depth D1 in the range of about 1 μm to about 2 μm.

[0046] Next reference Figure 1 Operation 120 and Fig.11In the cross-sectional view in FIG. 1 , the third metal shell layer 240 is conformally deposited on the workpiece, for example, on the horizontal and vertical surfaces of the metal shell hard mask layer 202 and further on the sidewalls and bottom surfaces of the first recess 238. The third metal shell layer 240 and the second metal shell layer 230 may have the same metal material. The third metal shell layer 240 may contain refractory metals such as tungsten, molybdenum, niobium, tantalum, titanium, chromium, hafnium, ruthenium and zirconium. In one embodiment, the third metal shell layer 240 may be a material such as tungsten (W), tungsten nitride (WN), titanium tungsten (TiW), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), molybdenum and carbides such as tungsten carbide. In various embodiments, the third metal shell layer 240 may be deposited using various thin film deposition techniques (such as physical vapor deposition, chemical vapor deposition, atomic layer deposition) and other techniques (such as sputtering, evaporation, etc.). The thickness of the third metal shell layer 240 may be about 2nm or thicker, for example, 1nm to 10nm in one embodiment.

[0047] Next reference Figure 1 Operation 122 and Fig.12 In the cross-sectional view in FIG. 1 , the anisotropic etching removes the third metal shell layer 240 from the horizontal surface, forming the second portion 242 of the metal spacer in the opening 222 and the first recess 238. Specifically, the third metal shell layer 240 is removed from the horizontal surface of the first recess 238 to expose the dielectric layer 208 again, as shown in FIG. Fig.12 As shown. Alternatively, the second portion 242 of the metal spacer can be formed to extend at least along the sidewall of the first recess 238. In anisotropic etching, a bias voltage is applied to accelerate ions in the etching gas plasma toward the substrate. The vertical trajectory of the ions causes horizontal surfaces to etch much faster than vertical surfaces.

[0048] In some embodiments, after forming the second portion 242 of the metal spacer, the manufacture of the metal shell hard mask 250 is completed. Such a metal shell hard mask 250 includes an amorphous mask layer 210, a first metal shell layer 212, a first portion 232 of the metal spacer, and a second portion 242 of the metal spacer. As shown, the first portion 232 of the metal spacer can extend along the sidewalls of both the amorphous mask layer 210 and the first metal shell layer 212, and the second portion 242 of the metal spacer can extend along the (inner) sidewall of the first portion 232 of the metal spacer and further extend along the sidewall of the first recess 238. The amorphous mask layer 210 is capable of forming a thick hard mask with low stress. The thin first metal shell layer 212 and the metal spacers 232 and 242 provide high selectivity with almost no additional stress. The steps for forming the metal shell hard mask 250 are for illustrative purposes and not limiting. Those skilled in the art can use different but similar processes to manufacture the embodiment metal shell hard mask 250.

[0049] Next reference Figure 1 Operation 124 and Fig.13 , the metal shell hard mask 250 is used as an etching mask to etch a high aspect ratio second recess 258 extending through the dielectric layer 208 and ending at the semiconductor substrate 206. In various embodiments, such a high aspect ratio recess can be rectangular, square, circular (as in a contact), or any other regular or irregular shape, and can be formed like a trench or a hole. As a non-limiting example, the second recess 258 can have a depth D2 that is substantially greater than the depth (D1) of the first recess 238, for example, in the range of about 5 μm to about 100 μm. Thus, considering that the first and second recesses can share a substantially similar width, the second recess 258 can have an aspect ratio (depth to width) that is substantially greater than the first recess 238.

[0050] In some embodiments, operations 120 to 124 may be repeated until a desired depth and / or profile has been achieved. For example, after forming second recess 258, a fourth metal shell layer may be formed (operation 120), followed by etching a horizontal portion of the fourth metal shell layer (operation 122). Next, a third recess may be formed to further extend second recess 258 (operation 124).

[0051] In various embodiments, operations 102, 108, 114, 116, 118, 120, 122, and 124 may be performed in the first, second, third, fourth, fifth, sixth, seventh, and eighth chambers, respectively. Each of the first to eighth chambers may contain a workpiece (e.g., a semiconductor device 200 formed at any of the above manufacturing stages) in a specific environment (e.g., a specific pressure, a specific temperature, a specific gas flow rate, etc.), which allows a specific process to be performed on the semiconductor device 200. For example, the first, third, and sixth chambers may each be configured to perform a deposition process (e.g., atomic layer deposition, chemical vapor deposition, physical vapor deposition, metal-organic chemical vapor deposition, molecular beam epitaxy, electron beam physical vapor deposition, etc.), and the second, fourth, fifth, seventh, and eighth chambers may each be configured to perform an etching process (e.g., plasma etching, wet etching, anisotropic wet etching, etc.). In addition, in some embodiments, the first, third, and sixth chambers may be the same chamber, and the second, fourth, fifth, seventh, and eighth chambers may be the same chamber.

[0052] Advantageously, because the etching process removes less of the metal shell hard mask 250, specifically, the first metal shell layer 212, there is no need to increase the thickness of the amorphous mask layer to compensate for mask erosion during etching. In addition, the metal spacers 232 and 242 on the mask sidewalls prevent lateral erosion during long etching times, which may cause sidewall bowing in the etched high aspect ratio openings. Using a metal shell hard mask (e.g., 250), the depth of the etched high aspect ratio features is not limited by the mask. For example, using a metal shell hard mask, high aspect ratio features (e.g., 258) can be etched deeper and with greater fidelity than using an amorphous material hard mask. In one or more embodiments, the depth (D1 and D2) etched in the dielectric layer 208, i.e., the depth of the high aspect ratio features, can be 2 to 100 times the total thickness of the amorphous mask layer 210 and the first metal shell layer 212.

[0053] In various embodiments, after forming such high aspect ratio features (e.g., 238 and 258, which are hereinafter "features 260") in dielectric layer 208, semiconductor materials or metal materials may be deposited to partially or completely fill feature 260 (and opening 222). In one example, the semiconductor material may be selected from the group consisting of silicon, silicon germanium, conductive oxide materials, two-dimensional (2D) semiconductor materials, and combinations thereof, which may form respective channels of a plurality of memory cells vertically spaced apart from one another of a three-dimensional (3D) memory array. In another example, the metal material may be selected from the group consisting of copper, aluminum, tungsten, gold, and combinations thereof, which may form control lines (e.g., word lines, source lines, bit lines) shared by a plurality of memory cells vertically spaced apart from one another of a three-dimensional (3D) memory array.

[0054] After filling the features 260 with a suitable material, a majority of the metal shell hard mask 250 may be removed by a polishing process (e.g., a chemical mechanical polishing (CMP) process) and / or one or more (e.g., dry and / or wet) etching processes. For example, the polishing process may remove the amorphous mask layer 210 and the first metal shell layer 212 (and corresponding portions of other features above the top surface of the dielectric layer 208). In this way, a lower portion of the second portion 242 of the metal spacer (disposed below the top surface of the dielectric layer 208) may remain. In another example, the polishing process may remove the amorphous mask layer 210 and the first metal shell layer 212 (and the first portion 232 and the second portion 242 of the metal spacer) until the lower portion of the second portion 242 of the metal spacer extending into the dielectric layer 208 is also removed. In yet another example, the first metal shell layer 212 may be removed by a wet etching process, and the amorphous mask layer 210 may be removed by a dry etching process using an oxygen plasma.

[0055] In the foregoing description, specific details have been set forth, such as the specific geometry of the processing system and the description of the various components and processes used therein. However, it should be understood that the technology herein can be practiced in other embodiments that are separated from these specific details, and such details are for the purpose of explanation rather than limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numbers, materials and configurations have been set forth in order to provide a thorough understanding. However, embodiments can be practiced without such specific details. Components having substantially the same functional configuration are represented by similar reference characters, and therefore any redundant descriptions can be omitted.

[0056] Various techniques have been described as multiple discrete operations to assist in understanding various embodiments. The order of description should not be interpreted as implying that these operations are necessarily dependent on the order. In fact, these operations do not need to be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0057] As used herein, "substrate" or "target substrate" generally refers to an object to be processed according to the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure (e.g., a semiconductor wafer, a mask), or a layer on a base substrate structure or a layer covering a base substrate structure (e.g., a thin film). Thus, a substrate is not limited to any particular base structure, underlying layer, or covering layer, patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. The description may refer to a specific type of substrate, but this is for illustrative purposes only.

[0058] Those skilled in the art will also appreciate that many changes may be made to the operation of the techniques explained above while still achieving the same objectives of the present invention. Such changes are intended to be encompassed by the scope of this disclosure. Thus, the foregoing description of the embodiments of the present invention is not intended to be limiting. On the contrary, any limitations to the embodiments of the present invention are presented in the following claims.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a first metal layer on top of an amorphous mask layer disposed on a substrate; forming a second metal layer extending along vertical sidewalls of the opening in the amorphous mask layer; forming a first recess extending partially into the substrate using the first metal layer and the second metal layer as a first etching mask; forming a third metal layer extending along the vertical sidewalls of the first recess; as well as A second recess is formed below the first recess using the first to third metal layers as a second etching mask.

2. The method of claim 1, wherein: The first to third metal layers each include a refractory metal.

3. The method of claim 1, wherein: The second and third metal layers each include a metal material selected from the group consisting of tungsten, titanium, tantalum, molybdenum, chromium, hafnium, ruthenium, and combinations thereof.

4. The method of claim 3, wherein: The second and third metal layers include titanium and tungsten, respectively.

5. The method of claim 1, wherein: The first to third metal layers each include tungsten or tungsten nitride.

6. The method of claim 1, wherein: The first to third metal layers are made of the same metal material.

7. The method of claim 1, wherein: The amorphous mask layer includes amorphous carbon, spin-on carbon or amorphous silicon.

8. The method of claim 1, further comprising: forming a fourth metal layer extending at least along the vertical sidewall of the second recess; A third recess is formed below the second recess using the first to fourth metal layers as a third etching mask.

9. The method of claim 1, wherein: The substrate consists of a single dielectric layer with silicon oxide.

10. The method of claim 1, wherein: The substrate is composed of a plurality of alternately stacked first dielectric layers and second dielectric layers, each of the first dielectric layers having silicon dioxide and each of the second dielectric layers having silicon nitride or silicon oxynitride.

11. The method of claim 1, further comprising filling the first and second recesses with a semiconductor material or a metal material.

12. A method for forming a semiconductor device, the method comprising: forming a mask layer on the substrate; forming a first metal layer including a first metal on the mask layer; forming openings in the first metal layer and the mask layer; forming a first portion of a metal spacer including a second metal along a sidewall of the opening; etching the substrate using the first metal layer and the first portion of the metal spacer as a first etching mask to form a first recess; forming a second portion of the metal spacer including a third metal along a sidewall of the first recess; as well as The substrate is etched using both the first metal layer and the first and second portions of the metal spacer as a second etch mask to form a second recess below the first recess.

13. The method of claim 12, wherein: The step of forming the first portion of the metal spacer further comprises: depositing a second metal layer; and The horizontally extending portion of the second metal layer is etched to form the first portion of the metal spacer.

14. The method of claim 12, wherein: The step of forming the second portion of the metal spacer further comprises: depositing a third metal layer; and The horizontally extending portion of the third metal layer is etched to form the second portion of the metal spacer.

15. The method of claim 12, wherein: The first to third metals each include a refractory metal. 16 . The method of claim 12 , further comprising filling the first and second recesses with a semiconductor material or a metal material. 17 . The method of claim 16 , further comprising forming features of a three-dimensional (3D) memory cell based on the semiconductor material or the metal material filling the first and second recesses.

18. The method of claim 12, wherein: The first recess has a first aspect ratio of its depth to its width, and the second recess has a second aspect ratio of its depth to its width, and wherein the second aspect ratio is substantially greater than the first aspect ratio.

19. An apparatus comprising: a first chamber configured to receive a substrate overlying a mask layer and to deposit a first metal layer on the mask layer; a second chamber configured to form an opening through the first metal layer and the mask layer; a third chamber configured to perform deposition of a second metal layer to extend along a vertical sidewall of the opening; a fourth chamber configured to etch a horizontal portion of the second metal layer; a fifth chamber configured to form a first recess extending into the substrate based at least on a remaining vertical portion of the second metal layer; a sixth chamber configured to deposit a third metal layer to extend along a vertical sidewall of the first recess; a seventh chamber configured to etch a horizontal portion of the third metal layer; as well as An eighth chamber is configured to form a second recess further extending into the substrate based on at least a remaining vertical portion of the third metal layer.

20. The apparatus of claim 19, wherein: The first chamber, the third chamber and the sixth chamber are the same chamber.

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