Isolation pillar structures for stacked device structures

Abstract

A microelectronic structure includes: a first stacked device structure including a first upper device and a first lower device; a second stacked device structure including a second upper device and a second lower device; and an isolation pillar structure (236) between the first and second stacked device structures. The isolation pillar structure has an upper section contacting the first and second upper devices and a lower section contacting the first and second lower devices. An upper section of the isolation pillar structure has a first width and a lower section of the isolation pillar structure has a second width different from the first width.

Description

Background Art

[0001] The present application relates to semiconductors, and more specifically, to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips have become ubiquitous in many products, particularly as they continue to decrease in cost and size. There is a continuous need to reduce the size of structural features and / or provide a greater amount of structural features for a given chip size. Typically, miniaturization allows for improved performance at lower power levels and lower costs. Current technology is at or near the atomic scale of some micro devices, such as logic gates, field effect transistors (FETs) and capacitors.

[0002] A field effect transistor (FET) is a transistor having a source, a gate and a drain, and having an action that depends on the flow of carriers (electrons or holes) along a channel extending between the source and the drain. The current through the channel between the source and the drain can be controlled by the lateral electric field under the gate.

[0003] FETs are widely used for switching, amplification, filtering, and other tasks. FETs include metal oxide semiconductor (MOS) FETs (MOSFETs). Complementary MOS (CMOS) devices are widely used, where both n-type and p-type transistors (nFETs and pFETs) are used to make logic and other circuits. The source and drain regions of a FET are typically formed by adding dopants to targeted areas of a semiconductor body on either side of a channel, with a gate formed over the channel. The gate includes a gate dielectric over the channel and a gate conductor over the gate dielectric. The gate dielectric is an insulator material that prevents large leakage currents from flowing into the channel when a voltage is applied to the gate conductor, while allowing the applied gate voltage to generate a lateral electric field in the channel.

[0004] Various techniques can be used to reduce the size of FETs. One technique is by using a fin-shaped channel in a FinFET device. Prior to the advent of the FinFET arrangement, CMOS devices were typically substantially planar along the surface of the semiconductor substrate, except for the FET gate, which was disposed on top of the channel. FinFETs utilize a vertical channel structure, increasing the surface area of ​​the channel exposed to the gate. Therefore, in a FinFET structure, the gate can more effectively control the channel because the gate extends over more than one side or surface of the channel. In some FinFET configurations, the gate surrounds three surfaces of the three-dimensional channel, rather than being disposed only on the top surface of a traditional planar channel.

[0005] Another technique for reducing the size of FETs is by using stacked nanosheet channels formed on a semiconductor substrate. Stacked nanosheets can be two-dimensional nanostructures, such as thin sheets with a thickness ranging from about 1 to 100 nanometers (nm). Nanosheets and nanowires are viable options for scaling to 7nm and below. The general process flow for forming a nanosheet stack involves removing a sacrificial layer between thin sheets of channel material, which can be formed of silicon germanium (SiGe), and the thin sheets of channel material can be formed of silicon (Si).

[0006] For continued scaling down (e.g., to 2.5nm and below), next generation complementary FET (CFET) devices may be used. CFET devices provide a complex all-around gate (GAA) structure. Conventional GAA FETs, such as nanosheet FETs, may stack multiple p-type nanowires or nanosheets on top of each other in one device, and may stack multiple n-type nanowires or nanosheets on top of each other in another device. The CFET structure provides improved track height scaling, resulting in structural gain (e.g., 30-40% structural gain for different types of devices, such as logic devices, static random access memory (SRAM) devices, etc.). In the CFET structure, n-type and p-type nanowires or nanosheets are stacked on top of each other, eliminating the n-to-p separation bottleneck and reducing the device area footprint. However, there is still a need for further scaling and reducing the size of the FET. Summary of the invention

[0007] Embodiments of the present invention provide techniques for forming isolation pillar structures with varying widths to separate and control channel widths of devices in a stacked device structure.

[0008] In one embodiment, a microelectronic structure includes a first stacked device structure, a second stacked device structure, and an isolation column structure, wherein the first stacked device structure includes a first upper device and a first lower device, the second stacked device structure includes a second upper device and a second lower device, and the isolation column structure is located between the first and second stacked device structures. The isolation column structure has an upper section that contacts the first and second upper devices and a lower section that contacts the first and second lower devices. The upper section of the isolation column structure has a first width, and the lower section of the isolation column structure has a second width that is different from the first width. The isolation column structure advantageously enables the first and second stacked device structures to be formed closer to each other, and the varying width of the isolation column structure advantageously enables the width of the devices in the first and second stacked device structures separated by the isolation column structure to be controlled.

[0009] One of the first upper device and the first lower device in the first stacked device structure may include an nFET device, and the other of the first upper device and the second lower device in the first stacked device structure may include a pFET device. The first width of the upper section of the isolation pillar and the second width of the lower section of the isolation pillar control the ratio of the size of the n-type active area of ​​the nFET device to the size of the p-type active area of ​​the pFET device.

[0010] In another embodiment, a microelectronic structure includes a first stacked field effect transistor structure, a second stacked field effect transistor structure, and an isolation pillar structure, the first stacked field effect transistor structure including a first lower field effect transistor device and a first upper field effect transistor device, the second stacked field effect transistor structure including a second lower field effect transistor device and a second upper field effect transistor device, the isolation pillar structure between the first stacked field effect transistor structure and the second stacked field effect transistor structure, the isolation pillar structure having an upper section with a first width and a lower section with a second width different from the first width. The isolation pillar structure advantageously enables the first and second stacked field effect transistor structures to be formed closer to each other, and the varying width of the isolation pillar structure advantageously enables the width of the channels of the upper and lower field effect transistor devices in the first and second stacked field effect transistor structures separated by the isolation pillar structure to be controlled.

[0011] The upper section of the isolation column structure can contact the channels of the first and second upper FET devices in the first and second stacked FET structures, and the lower section of the isolation column structure can contact the channels of the first and second lower FET devices in the first and second stacked FET structures. The isolation column structure can separate the channels, gates, and source / drain regions of the first and second upper and lower FET devices in the first and second stacked FET structures.

[0012] A first width of an upper section of the isolation pillar structure may be greater than a second width of a lower section of the isolation pillar structure.

[0013] The isolation pillar structure may also include an extension section extending outwardly from the lower section toward the recesses in the channels of the first and second lower FET devices in the first and second stacked FET structures.

[0014] In another embodiment, an integrated circuit includes a complementary field effect transistor structure, the complementary field effect transistor structure including a first stacked field effect transistor structure, a second stacked field effect transistor structure, and an isolation column structure, the first stacked field effect transistor structure including a first lower field effect transistor device and a first upper field effect transistor device, the second stacked field effect transistor structure including a second lower field effect transistor device and a second upper field effect transistor device, the isolation column structure between the first stacked field effect transistor structure and the second stacked field effect transistor structure, the isolation column structure having an upper section with a first width and a lower section with a second width different from the first width. The isolation column structure advantageously enables the first and second stacked field effect transistor structures in the complementary field effect transistor structure to be formed closer to each other, and the varying width of the isolation column structure advantageously enables the width of the channel of the upper and lower field effect transistor devices in the first and second stacked field effect transistor structures separated by the isolation column structure to be controlled.

[0015] The upper section of the isolation column structure may contact the channels of the first and second upper FET devices in the first and second stacked FET structures, and the lower section of the isolation column structure may contact the channels of the first and second lower FET devices in the first and second stacked FET structures.

[0016] In another embodiment, a microelectronic structure includes two or more stacked field effect transistor structures and an isolation column structure, each of the two or more stacked field effect transistor structures includes two or more field effect transistor devices stacked on each other, and the isolation column structure separates the first and second field effect transistor structures in the two or more stacked field effect transistor structures. The isolation column structure includes a first section and a second section, the first section contacts the channel of at least the first field effect transistor device in the two or more first and second stacked field effect transistor structures of the two or more stacked field effect transistor structures, and the second section contacts the channel of at least the second field effect transistor device in the two or more first and second stacked field effect transistor structures of the two or more stacked field effect transistor structures. The first section of the isolation column structure has a first width, and the second section of the isolation column structure has a second width different from the first width. The isolation column structure advantageously enables the first and second stacked field effect transistor structures in the two or more stacked field effect transistor structures to be formed closer to each other, and the varying width of the isolation column structure advantageously enables control of the width of the channels of the upper and lower field effect transistor devices in the first and second stacked field effect transistor structures in the two or more stacked field effect transistor structures separated by the isolation column structure.

[0017] A first FET device of the two or more FET devices may include an nFET device, and a second FET device of the two or more FET devices may include a pFET device. A first width of the isolation pillar structure may define a first active area region of the nFET device, and a second width of the isolation pillar may define a second active area region of the pFET device.

[0018] The microelectronic structure may also include an additional isolation column structure separating a third and a fourth FET structure in two or more stacked FET structures, wherein the additional isolation column structure includes a first segment and a second segment, the first segment contacts a channel of at least a first FET device in two or more FET devices in the third and fourth stacked FET structures, the second segment contacts a channel of at least a second FET device in two or more FET devices in the third and fourth stacked FET structures, wherein the first segment of the additional isolation column structure has a third width, and the second segment of the isolation column structure has a fourth width different from the third width, and wherein the third width is different from the first width and the fourth width is different from at least one of the second width.

[0019] In another embodiment, a method includes forming first and second stacked field effect transistor device structures, each of the first and second stacked field effect transistor device structures including an upper field effect transistor device and a lower field effect transistor device, wherein the upper field effect transistor device of the first and second stacked field effect transistor device structures has a merged channel, and wherein the lower field effect transistor device of the first and second stacked field effect transistor device structures has a merged channel. The method also includes forming an isolation column structure between the first and second stacked field effect transistor structures, the isolation column structure including an upper section having a first width and a lower section having a second width different from the first width, the upper section separating the merged channels of the upper field effect transistor device of the first and second stacked field effect transistor device structures, and the lower section separating the merged channels of the lower field effect transistor device of the first and second stacked field effect transistor device structures. The isolation column structure advantageously enables the first and second stacked field effect transistor structures to be formed closer to each other, and the varying width of the isolation column structure advantageously enables the width of the channels of the upper and lower field effect transistor devices in the first and second stacked field effect transistor structures separated by the isolation column structure to be controlled.

[0020] Forming the isolation column structure may include performing a first cutting process to etch through a merged channel of an upper FET device of the first and second stacked FET device structures, the first cutting process stopping on an intermediate dielectric isolation layer disposed between the upper FET device and the lower FET device of the first and second stacked FET device structures, forming a protective spacer on an exposed sidewall of the channel of the upper FET device of the first and second stacked FET device structures, and performing a second cutting process to etch through a merged channel of a lower FET device of the first and second stacked FET device structures, the second cutting process stopping on a bottom dielectric isolation layer disposed below the lower FET device of the first and second stacked FET device structures.

[0021] Forming the spacer structure may also include performing a recess etch that removes a portion of the channel of the lower FET device.

[0022] Forming the isolation column structure may also include removing the protection spacer and filling the dielectric material in the space exposed by the first cutting process, the second cutting process and the groove etching. The groove etching controls the ratio of the lower active area area of ​​the lower FET device to the upper active area area of ​​the upper FET device. The lower FET device may include one of an nFET device and a pFET device, and the upper FET device may include the other of the nFET device and the pFET device.

[0023] These and other features and advantages of the embodiments described herein will become more apparent from the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A A side cross-sectional view of a complementary field effect transistor structure is shown in accordance with an embodiment of the present invention.

[0025] Figure 1B A side cross-sectional view of another complementary field effect transistor structure according to an embodiment of the present invention is shown.

[0026] Figure 2A A first side cross-sectional view of the structure after forming a nanosheet channel on a substrate according to an embodiment of the present invention is shown.

[0027] Figure 2B A second side cross-sectional view of the structure after forming a nanosheet channel on the substrate according to an embodiment of the present invention is shown.

[0028] Figure 2C A top view of a structure after a nanosheet channel is formed on a substrate according to an embodiment of the present invention is shown.

[0029] Figure 3A Figure 2 shows the structure of a nanosheet after patterning and shallow trench isolation region formation according to an embodiment of the present invention. Figure 2A-2CA first side cross-sectional view of a structure.

[0030] Figure 3B Figure 2 shows the structure of a nanosheet after patterning and shallow trench isolation region formation according to an embodiment of the present invention. Figure 2A-2C A second side cross-sectional view of the structure.

[0031] Figure 3C Figure 2 shows the structure of a nanosheet after patterning and shallow trench isolation region formation according to an embodiment of the present invention. Figure 2A-2C Top view of the structure.

[0032] Figure 4A FIG. 1 shows a structure of a gate electrode after forming source / drain regions and gate structures according to an embodiment of the present invention. Figures 3A-3C A first side cross-sectional view of a structure.

[0033] Figure 4B FIG. 1 shows a structure of a gate electrode after forming source / drain regions and gate structures according to an embodiment of the present invention. Figures 3A-3C A second side cross-sectional view of the structure.

[0034] Figure 4C FIG. 1 shows a structure of a gate electrode after forming source / drain regions and gate structures according to an embodiment of the present invention. Figures 3A-3C Top view of the structure.

[0035] Figure 5A FIG. 2 shows a schematic diagram of a hard mask layer after patterning and cutting of a first set of nanosheets according to an embodiment of the present invention. Figures 4A-4C A first side cross-sectional view of a structure.

[0036] Figure 5B FIG. 4 shows a schematic diagram of a hard mask layer after patterning and cutting of a first set of nanosheets according to an embodiment of the present invention. Figures 4A-4C A second side cross-sectional view of the structure.

[0037] Figure 5C FIG. 4 shows a schematic diagram of a hard mask layer after patterning and cutting of a first set of nanosheets according to an embodiment of the present invention. Figures 4A-4C Top view of the structure.

[0038] Figure 5D FIG. 2 shows a schematic diagram of a first set of nanosheets after patterning of a hard mask layer and performing alternative cutting according to an embodiment of the present invention. Figures 4A-4C A third side cross-sectional view of the structure.

[0039] Figure 5E FIG. 2 shows a first set of nanosheets after patterning of the hard mask layer and performing another alternative cutting according to an embodiment of the present invention. Figures 4A-4C A fourth side cross-sectional view of the structure.

[0040] Fig. 6AFIG. 2 shows a structure of a first group of nanosheets after forming a guard spacer for the first group of nanosheets according to an embodiment of the present invention. Figures 5A-5E A first side cross-sectional view of a structure.

[0041] Figure 6B FIG. 2 shows a structure of a first group of nanosheets after forming a guard spacer for the first group of nanosheets according to an embodiment of the present invention. Figures 5A-5E A second side cross-sectional view of the structure.

[0042] Figure 6C FIG. 2 shows a structure of a first group of nanosheets after forming a guard spacer for the first group of nanosheets according to an embodiment of the present invention. Figures 5A-5E Top view of the structure.

[0043] Fig.6D FIG. 2 shows a structure of a first group of nanosheets after forming a guard spacer for the first group of nanosheets according to an embodiment of the present invention. Figures 5A-5E A third side cross-sectional view of the structure.

[0044] Fig. 6E FIG. 2 shows a structure of a first group of nanosheets after forming a guard spacer for the first group of nanosheets according to an embodiment of the present invention. Figures 5A-5E A fourth side cross-sectional view of the structure.

[0045] Fig. 7A FIG. 2 shows a structure of a nanosheet after etching the intermediate dielectric isolation layer and the second group of nanosheets according to an embodiment of the present invention. Figures 6A-6E A first side cross-sectional view of a structure.

[0046] Figure 7B FIG. 2 shows a structure of a nanosheet after etching the intermediate dielectric isolation layer and the second group of nanosheets according to an embodiment of the present invention. Figures 6A-6E A second side cross-sectional view of the structure.

[0047] Figure 7C FIG. 2 shows a structure of a nanosheet after etching the intermediate dielectric isolation layer and the second group of nanosheets according to an embodiment of the present invention. Figures 6A-6E Top view of the structure.

[0048] Fig.7D FIG. 2 shows a structure of a nanosheet after etching the intermediate dielectric isolation layer and the second group of nanosheets according to an embodiment of the present invention. Figures 6A-6E A third side cross-sectional view of the structure.

[0049] Fig. 7E FIG. 2 shows a structure of a nanosheet after etching the intermediate dielectric isolation layer and the second group of nanosheets according to an embodiment of the present invention. Figures 6A-6E A fourth side cross-sectional view of the structure.

[0050] Fig. 8A FIG. 2 shows the second group of nanosheets after the depression according to an embodiment of the present invention. Figures 7A-7E A first side cross-sectional view of a structure.

[0051] Figure 8B FIG. 2 shows the second group of nanosheets after the depression according to an embodiment of the present invention. Figures 7A-7E A second side cross-sectional view of the structure.

[0052] Figure 8C FIG. 2 shows the second group of nanosheets after the depression according to an embodiment of the present invention. Figures 7A-7E Top view of the structure.

[0053] Fig.8D Figure 2 shows the patterning of the protective layer on the second group of nanosheets according to an embodiment of the present invention. Figures 7A-7E A third side cross-sectional view of the structure.

[0054] Fig. 8E FIG. 2 shows the second group of nanosheets after the depression according to an embodiment of the present invention. Figures 7A-7E A fourth side cross-sectional view of the structure.

[0055] Fig. 9A FIG. 2 shows the second group of nanosheets after further recessing according to an embodiment of the present invention. Figures 8A-8E A first side cross-sectional view of a structure.

[0056] Fig. 9B FIG. 2 shows the second group of nanosheets after further recessing according to an embodiment of the present invention. Figures 8A-8E A second side cross-sectional view of the structure.

[0057] Fig. 9C FIG. 2 shows the second group of nanosheets after further recessing according to an embodiment of the present invention. Figures 8A-8E Top view of the structure.

[0058] Fig.9D Figure 2 shows the patterning of the protective layer on the second group of nanosheets according to an embodiment of the present invention. Figures 8A-8E A third side cross-sectional view of the structure.

[0059] Fig.9E Figure 2 shows the patterning of the protective layer on the second group of nanosheets according to an embodiment of the present invention. Figures 8A-8E A fourth side cross-sectional view of the structure.

[0060] Fig. 10A FIG. 1 shows a structure after removing the protective layer and the protective spacer according to an embodiment of the present invention. Figures 9A-9E A first side cross-sectional view of a structure.

[0061] Fig. 10B FIG. 1 shows a structure after removing the protective layer and the protective spacer according to an embodiment of the present invention. Figures 9A-9E A second side cross-sectional view of the structure.

[0062] Fig. 10C FIG. 1 shows a structure after removing the protective layer and the protective spacer according to an embodiment of the present invention. Figures 9A-9E Top view of the structure.

[0063] Fig. 10D FIG. 1 shows a structure after removing the protective layer and the protective spacer according to an embodiment of the present invention. Figures 9A-9E A third side cross-sectional view of the structure.

[0064] Fig.10E FIG. 1 shows a structure after removing the protective layer and the protective spacer according to an embodiment of the present invention. Figures 9A-9E A fourth side cross-sectional view of the structure.

[0065] Fig.11A FIG. 1 shows a structure of a dielectric column after forming the dielectric column according to an embodiment of the present invention. Figures 10A-10E A first side cross-sectional view of a structure.

[0066] Fig. 11B FIG. 1 shows a structure of a dielectric column after forming the dielectric column according to an embodiment of the present invention. Figures 10A-10E A second side cross-sectional view of the structure.

[0067] Fig. 11C FIG. 1 shows a structure of a dielectric column after forming the dielectric column according to an embodiment of the present invention. Figures 10A-10E Top view of the structure.

[0068] Fig.11D FIG. 1 shows a structure of a dielectric column after forming the dielectric column according to an embodiment of the present invention. Figures 10A-10E A third side cross-sectional view of the structure.

[0069] Fig.11E FIG. 1 shows a structure of a dielectric column after forming the dielectric column according to an embodiment of the present invention. Figures 10A-10E A fourth side cross-sectional view of the structure.

[0070] Fig. 12A FIG. 1 shows a schematic diagram of a wafer after forming mid-process contacts and back-end-of-process interconnects and after bonding the structure to a carrier wafer according to an embodiment of the present invention. Figures 11A-11E A first side cross-sectional view of a structure.

[0071] Fig. 12B FIG. 1 shows a schematic diagram of a wafer after forming mid-process contacts and back-end-of-process interconnects and after bonding the structure to a carrier wafer according to an embodiment of the present invention. Figures 11A-11E A second side cross-sectional view of the structure.

[0072] Fig. 12C FIG. 1 shows a schematic diagram of a wafer after forming mid-process contacts and back-end-of-process interconnects and after bonding the structure to a carrier wafer according to an embodiment of the present invention. Figures 11A-11E Top view of the structure.

[0073] Fig.12D FIG. 1 shows a schematic diagram of a wafer after forming mid-process contacts and back-end-of-process interconnects and after bonding the structure to a carrier wafer according to an embodiment of the present invention. Figures 11A-11E A third side cross-sectional view of the structure.

[0074] Fig.12E FIG. 1 shows a schematic diagram of a structure after forming mid-process contacts and back-end process interconnects and after bonding the structure to a carrier wafer according to an embodiment of the present invention. Figures 11A-11E A fourth side cross-sectional view of the structure.

[0075] Fig.13A FIG. 1 shows a structure after removing the substrate from the back side of the structure and stopping on the etch stop layer according to an embodiment of the present invention. Figures 12A-12E A first side cross-sectional view of a structure.

[0076] Fig. 13B FIG. 1 shows a structure after removing the substrate from the back side of the structure and stopping on the etch stop layer according to an embodiment of the present invention. Figures 12A-12E A second side cross-sectional view of the structure.

[0077] Fig. 13C FIG. 1 shows a structure after removing the substrate from the back side of the structure and stopping on the etch stop layer according to an embodiment of the present invention. Figures 12A-12E Top view of the structure.

[0078] Fig.13D Figure 2 shows the structure after removing the substrate from the back side of the structure and stopping on the etch stop layer according to an embodiment of the present invention. Figures 12A-12E A third side cross-sectional view of the structure.

[0079] Fig.13E Figure 2 shows the structure after removing the substrate from the back side of the structure and stopping on the etch stop layer according to an embodiment of the present invention. Figures 12A-12E A fourth side cross-sectional view of the structure.

[0080] Fig.14A FIG. 1 shows a schematic diagram of a substrate after removing the etch stop layer and the remaining exposed portion of the substrate according to an embodiment of the present invention. Figures 13A-13E A first side cross-sectional view of a structure.

[0081] Fig. 14B FIG. 1 shows a schematic diagram of a substrate after removing the etch stop layer and the remaining exposed portion of the substrate according to an embodiment of the present invention. Figures 13A-13E A second side cross-sectional view of the structure.

[0082] Fig. 14C FIG. 1 shows a schematic diagram of a substrate after removing the etch stop layer and the remaining exposed portion of the substrate according to an embodiment of the present invention. Figures 13A-13E Top view of the structure.

[0083] Fig.14DFIG. 1 shows a schematic diagram of a substrate after removing the etch stop layer and the remaining exposed portion of the substrate according to an embodiment of the present invention. Figures 13A-13E A third side cross-sectional view of the structure.

[0084] Fig.14E FIG. 1 shows a schematic diagram of a substrate after removing the etch stop layer and the remaining exposed portion of the substrate according to an embodiment of the present invention. Figures 13A-13E A fourth side cross-sectional view of the structure.

[0085] Fig.15A FIG. 1 shows an example of a structure after depositing and planarizing an interlayer dielectric on the back side of the structure according to an embodiment of the present invention. Figures 14A-14E A first side cross-sectional view of a structure.

[0086] Fig. 15B FIG. 1 shows an example of a structure after depositing and planarizing an interlayer dielectric on the back side of the structure according to an embodiment of the present invention. Figures 14A-14E A second side cross-sectional view of the structure.

[0087] Fig. 15C FIG. 1 shows an example of a structure after depositing and planarizing an interlayer dielectric on the back side of the structure according to an embodiment of the present invention. Figures 14A-14E Top view of the structure.

[0088] Fig.15D FIG. 1 shows an example of a structure after depositing and planarizing an interlayer dielectric on the back side of the structure according to an embodiment of the present invention. Figures 14A-14E A third side cross-sectional view of the structure.

[0089] Fig.15E FIG. 1 shows an example of a structure after depositing and planarizing an interlayer dielectric on the back side of the structure according to an embodiment of the present invention. Figures 14A-14E A fourth side cross-sectional view of the structure.

[0090] Fig.16A FIG. 1 shows a structure after removing the sacrificial placeholder from the back side of the structure according to an embodiment of the present invention. Figures 15A-15E A first side cross-sectional view of a structure.

[0091] Fig. 16B FIG. 1 shows a structure after removing the sacrificial placeholder from the back side of the structure according to an embodiment of the present invention. Figures 15A-15E A second side cross-sectional view of the structure.

[0092] Fig. 16C FIG. 1 shows a structure after removing the sacrificial placeholder from the back side of the structure according to an embodiment of the present invention. Figures 15A-15E Top view of the structure.

[0093] Fig.16D FIG. 1 shows a structure after removing the sacrificial placeholder from the back side of the structure according to an embodiment of the present invention. Figures 15A-15E A third side cross-sectional view of the structure.

[0094] Fig.16E FIG. 1 shows a structure after removing the sacrificial placeholder from the back side of the structure according to an embodiment of the present invention. Figures 15A-15E A fourth side cross-sectional view of the structure.

[0095] Fig.17A FIG. 1 shows a schematic diagram of a backside contact metallization and interconnect formation according to an embodiment of the present invention. Figures 16A-16E A first side cross-sectional view of a structure.

[0096] Fig. 17B FIG. 1 shows a schematic diagram of a backside contact metallization and interconnect formation according to an embodiment of the present invention. Figures 16A-16E A second side cross-sectional view of the structure.

[0097] Fig. 17C FIG. 1 shows a schematic diagram of a backside contact metallization and interconnect formation according to an embodiment of the present invention. Figures 16A-16E Top view of the structure.

[0098] Fig.17D FIG. 1 shows a schematic diagram of a backside contact metallization and interconnect formation according to an embodiment of the present invention. Figures 16A-16E A third side cross-sectional view of the structure.

[0099] Fig.17E FIG. 1 shows a schematic diagram of a backside contact metallization and interconnect formation according to an embodiment of the present invention. Figures 16A-16E A fourth side cross-sectional view of the structure.

[0100] Fig.18 An integrated circuit including a complementary field effect transistor device structure having an isolation pillar structure with varying widths is shown according to an embodiment of the present invention. DETAILED DESCRIPTION

[0101] Illustrative embodiments of the present invention may be described herein in the context of illustrative methods for forming isolation pillar structures with varying widths to separate and control the channel widths of devices in a stacked device structure, and illustrative devices, systems, and devices formed using such methods. However, it should be understood that embodiments of the present invention are not limited to the illustrative methods, devices, systems, and apparatuses, but rather may be more broadly applied to other suitable methods, devices, systems, and apparatuses.

[0102] It should be understood that the various features shown in the drawings are schematic diagrams and are not necessarily drawn to scale. In addition, the same or similar reference numerals are used in all drawings to represent the same or similar features, elements or structures, and therefore, a detailed explanation of the same or similar features, elements or structures will not be repeated for each drawing. In addition, the terms "exemplary" and "illustrative" as used herein mean "used as an example, instance or illustration". Any embodiment or design described herein as "exemplary" or "illustrative" should not be construed as being more preferred or advantageous than other embodiments or designs.

[0103] As described above, various techniques can be used to reduce the size of FETs, including by using fin-shaped channels in FinFET devices, by using stacked nanosheet channels formed on a semiconductor substrate, and next generation CFET devices.

[0104] Figure 1A A cross-sectional view 100 of a set of conventional CFET cells 101-1, 101-2, 101-3, and 101-4 (collectively referred to as CFET cells 101) is shown. Figure 1B A cross-sectional view 150 of a set of proportional CFET cells 151-1, 151-2, 151-3, and 151-4 (collectively referred to as proportional CFET 151) is shown, wherein a gate extension is removed from one of the two nanosheet tips, wherein proportional CFET 151 may also be referred to as CFET 2 Unit 151). Figure 1A and 1B The structure of the CFET includes a substrate 102, a shallow trench isolation (STI) region 112, a bottom dielectric insulator (BDI) layer 116-1, a bottom nanosheet channel 108-1, a middle dielectric insulator (MDI) layer 116-2, a top nanosheet channel 108-2, a gate 114, an interlayer dielectric (ILD) layer 138, a gate cut 143, a gate contact 144, and a top side back-end of line (BEOL) interconnect 146. As shown in the figure, the CFET 2 Cell 151 provides improved overall scaling over CFET cell 101 by removing one gate extension per CMOS cell.

[0105] The illustrative embodiments provide novel methods and structures for controlling the 2 The widths of the n-type and p-type nanosheet channels stacked on top of each other in the cell make the CFET 2 The cell has a flexible n to p ratio. Microelectronic and semiconductor structures are provided that include stacked FETs (e.g., one FET on top of another FET, such as a pFET on top of an nFET, or an nFET on top of a pFET). Stacked cell pairs are positioned close to each other (e.g., providing a CFET 2A cell) wherein the nanosheet channel, gate, and source / drain regions (e.g., source / drain epitaxial layers) are separated by dielectric pillars. In stacked FETs, flexible ratios are provided, including: a top active area size smaller than a bottom active area size (e.g., the top nanosheet channel is wider than the bottom nanosheet channel); a top active area size larger than the bottom active area size (e.g., the bottom nanosheet channel is wider than the top nanosheet channel), or equal-sized top and bottom active area sizes (e.g., the top and bottom nanosheet channels have the same width). For configurations where the top active area size is larger than the bottom active area size, the dielectric pillars can include a forked bottom shape.

[0106] Microelectronic and other semiconductor structures with flexible n / p ratios can be formed using the following process. Two CFET stacked cells (e.g., CFET 2 The cell) is formed close to each other, where the channel, gate, and source / drain regions are merged at the beginning. The first cutting process is used to etch through the top channel, top gate, and top source / drain region, stopping on the MDI layer. The top channel protection spacer is then formed, followed by a second cutting process to etch through the MDI layer, bottom channel, bottom gate, and bottom source / drain region, stopping on the BDI layer. Optionally, additional recessing of the bottom channel is performed (for example, to adjust the relative sizes of the top and bottom active areas). The top channel protection spacer is then removed, and the first and second cutting areas (and any optional recessing of the bottom channel) are then filled with dielectric material or dielectric pillars.

[0107] Figure 2A-17E Shown is the formation of a CFET with a flexible n / p ratio having n-type and p-type nanosheet channels 2 The process flow of the unit.

[0108] Figure 2A A first side cross-sectional view 200 of the structure is shown after nanosheet channel layers 208 - 1 and 208 - 2 are formed on substrate 202 . Figure 2B A second side cross-sectional view 265 of the structure is shown, Figure 2C A top view 275 of the structure is shown. Figure 2C The top view 275 of EMBODIMENT 2 shows the active area 201 where the gate structures 203 - 1 , 203 - 2 , and 203 - 3 will be formed. Figure 2A The first side cross-sectional view 200 is taken along line AA in the top view 275 (eg, across gate structures 203-1, 203-2, and 203-3), and Figure 2B The second side cross-sectional view 265 is taken along line BB in the top view 275 (eg, along the gate structure 203 - 2 ).

[0109] The substrate 202 may be formed of any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multilayers thereof. Although silicon is the primary semiconductor material used in wafer fabrication, alternative semiconductor materials may be used as additional layers, such as but not limited to germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like.

[0110] An etch stop layer 204 is formed in the substrate 202. The etch stop layer 204 may include a buried oxide (BOX) layer or silicon germanium (SiGe), or another suitable material, such as a III-V semiconductor epitaxial layer. The etch stop layer 204 may have a height (in the Z-Z' direction) in the range of 10 to 30 nm.

[0111] A nanosheet is formed over substrate 202 , wherein the nanosheet includes sacrificial layers 206 - 1 and 206 - 2 (collectively referred to as sacrificial layers 206 ), nanosheet channel layers 208 - 1 and 208 - 2 (collectively referred to as nanosheet channel layers 208 ), and sacrificial layers 210 - 1 and 210 - 2 (collectively referred to as sacrificial layers 210 ).

[0112] Sacrificial layer 206 and sacrificial layer 210 are illustratively formed of different sacrificial materials so that they can be selectively etched or otherwise removed relative to each other. In some embodiments, sacrificial layer 206 and sacrificial layer 210 are both formed of SiGe, but have different percentages of Ge. For example, sacrificial layer 206 may have a relatively high percentage of Ge (e.g., 55% Ge) and sacrificial layer 210 may have a relatively low percentage of Ge (e.g., 25% Ge). Other combinations of different sacrificial materials may be used in other embodiments. Sacrificial layers 206 and 210 may each have a thickness (in the Z-Z' direction) in the range of 6-15 nm.

[0113] The nanosheet channel layers 208 may be formed of Si or another suitable material (eg, a material similar to that used for the substrate 202). Each of the nanosheet channel layers 208 may have a thickness (in the ZZ' direction) in the range of 4-10 nm.

[0114] Figure 3A shows the nanosheets after patterning and STI region 212 formation. Figure 2A-2C A first side cross-sectional view 300 of a structure. Figure 3B shows the nanosheets after patterning and STI region 212 formation. Figure 2A-2C A second side cross-sectional view 365 of the structure. Figure 3C shows the nanosheets after patterning and STI region 212 formation. Figure 2A-2CA top view of the structure 375. Figure 3A The first side cross-sectional view 300 is taken along line AA in the top view 375, and Figure 3B The second side cross-sectional view 365 is taken along line BB in the top view 375 .

[0115] The STI region 212 may be formed by Figure 2A-2C The structure of the present invention is formed by patterning a mask layer on the structure of the present invention, then etching the sacrificial layer 210, the exposed portion of the nanosheet channel layer 208, and passing through a portion of the substrate 202, as shown in FIG. Figure 3A and 3B The STI region 212 may be formed of a dielectric material such as silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon oxynitride (SiON), etc. The STI region 212 may have a height (in the Z-Z' direction) in the range of 20 to 100 nm.

[0116] Figure 4A shows the stacked FET structure after forming Figures 3A-3C A first side cross-sectional view 400 of a structure. Figure 4B shows the stacked FET structure after forming Figures 3A-3C A second side cross-sectional view 465 of the structure. Figure 4C shows the stacked FET structure after forming Figures 3A-3C A top view of the structure 475. Figure 4A The first side cross-sectional view 400 is taken along line AA in the top view 475, and Figure 4B The second side cross-sectional view 465 is taken along line BB in the top view 475 .

[0117] The stacked FET structure includes a gate stack layer 214, a BDI layer 216-1, an MDI layer 216-2, an ILD layer 218, a sacrificial placeholder layer 220, a bottom source / drain region 222, a top source / drain region 224, an inner spacer 226, and a sidewall spacer 228. Figure 4A and 4B, a dummy gate is first formed on the nanosheet. Next, the sacrificial layers 206-1 and 206-2 are selectively removed, followed by forming sidewall spacers 228, MDI layer 216-2, and BDI layer 216-1 by conformal dielectric liner deposition and anisotropic dielectric liner etching. Thereafter, the exposed nanosheet stack and the portion of the MDI layer 216-2 not covered by the dummy gate or sidewall spacer 228 are recessed, followed by recessing the sacrificial layers 210-1 and 210-2 and forming the internal spacer 226. Next, backside contact patterning is used to form a trench through the BDI layer 216-1 into the substrate 202, and the trench is then filled with a sacrificial material to form the bottom of the sacrificial placeholder layer 220. Thereafter, a bottom source / drain region 222, a top source / drain region 224, and an ILD layer 218 are formed, followed by polysilicon opening CMP to expose the dummy gate. The dummy gate and sacrificial layers 210 - 1 and 210 - 2 are removed, and then a gate stack layer 214 is formed (eg, using a replacement HKMG process).

[0118] The gate stack layer 214 may include a gate dielectric layer and a gate conductor layer. The gate dielectric layer may be formed of a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. High-k materials may also include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate dielectric layer may have a uniform thickness in the range of 1 nm to 3 nm.

[0119] The gate conductor layer may include a metal gate or a work function metal (WFM). The WFM used for the gate conductor layer may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), a combination of Ti and Al alloys, a stack including a barrier layer (e.g., TiN, TaN, etc.) followed by one or more of the above WFM materials, etc. It should be understood that various other materials may be used for the gate conductor layer as desired.

[0120] The BDI layer 216-1 and the MDI layer 216-2 (collectively referred to as dielectric insulator layers 216) may be formed of any suitable insulator, such as SiN, silicon boron carbide nitride (SiBCN), silicon oxycarbonitride (SiOCN), etc. The BDI layer 216-1 is formed in the area previously occupied by the sacrificial layer 206-1, and the MDI layer 216-2 is formed in the area previously occupied by the sacrificial layer 206-2, and may have similar dimensions as the sacrificial layers 206-1 and 206-2.

[0121] The ILD layer 218 is formed between the bottom source / drain region 222 and the top source / drain region 224 and on top of the top source / drain region 224. The ILD layer 218 may be formed of any suitable isolation material, such as SiO2, SiOC, SiON, etc. The ILD layer 218 has a width (in the XX' direction) that matches the width of the bottom source / drain region 222 and the top source / drain region 224. The sacrificial placeholder layer 220 is formed below the bottom source / drain region 222 and may be formed of one or more sacrificial materials, such as SiGe, titanium oxide (TiO x ), aluminum oxide (AlO x ), silicon carbide (SiC), etc. The sacrificial placeholder layer has a width (in the XX' direction) that also matches the width of the bottom source / drain region 222 and the top source / drain region 224. A mask layer may be patterned over the structure, followed by etching through the underlying layers into the substrate 202. The sacrificial placeholder layer 220 may then be deposited, followed by epitaxial growth of the bottom source / drain region 222, deposition and planarization of a portion of the ILD layer 218 between the bottom source / drain region 222 and the top source / drain region 224, followed by epitaxial growth of the top source / drain region 224, and deposition and planarization of a portion of the ILD layer 218 above the top source / drain region 224.

[0122] As described above, the bottom source / drain region 222 and the top source / drain region 224 can be formed using an epitaxial growth process, and therefore can also be referred to as a bottom epitaxial layer 222 and a top epitaxial layer 224. The bottom source / drain region 222 and the top source / drain region 224 can be appropriately doped, such as using ion implantation, gas phase doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid phase doping, solid phase doping, etc. The n-type dopant can be selected from the group of phosphorus (P), arsenic (As) and antimony (Sb), and the p-type dopant can be selected from the group of boron (B), boron fluoride (BF2), gallium (Ga), indium (In) and thallium (Tl). The bottom source / drain region 222 and the top source / drain region 224 can be formed using an epitaxial growth process. In some embodiments, the epitaxial process includes in-situ doping (dopants are incorporated into the epitaxial material during epitaxy). The epitaxial material can be grown from a gaseous or liquid precursor. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), ultra high vacuum chemical vapor deposition (UHVCVD), low pressure chemical vapor deposition (LPCVD), limited reaction process CVD (LRPCVD), or other suitable processes. Depending on the type of transistor to be formed, epitaxial silicon, silicon germanium (SiGe), germanium (Ge), and / or carbon doped silicon (Si:C) silicon can be doped (in situ doped) during deposition by adding dopants such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium). The dopant concentration in the source / drain can range from 1×10 19 cm -3 Up to 3×10 21 cm -3 , or preferably between 2×10 20 cm -3 Up to 3×10 21 cm -3 The bottom source / drain region 222 and the top source / drain region 224 may have a width (in the XX′ direction) in the range of 10 to 30 nm.

[0123] The internal spacer 226 may be formed to fill the recessed space (e.g., produced by recess etching of the sacrificial layer 210 before its removal). The internal spacer 226 may be formed of silicon nitride (SiN) or other suitable materials such as SiBCN, silicon carbide oxide (SiCO), SiOCN, etc. The width of the internal spacer 226 (along the XX' direction) may be in the range of 2-10 nm, and its height (along the ZZ' direction) may match the height of the sacrificial layer 210.

[0124] The sidewall spacers 228 may be formed of a material similar to the dielectric insulator layer 216. The sidewall spacers 228 may have a width similar to that of the inner spacers 226 (in the XX' direction).

[0125] Figure 5A 2 shows the hard mask (HM) layer 230 after patterning and cutting patterning of the nanosheet channel layer 208-2. Figures 4A-4C A first side cross-sectional view 500 of a structure. Figure 5B 2 shows the HM layer 230 patterning and the nanosheet channel layer 208-2 after cutting patterning. Figures 4A-4C A second side cross-sectional view 565 of the structure. Figure 5C shows the HM layer 230 patterning and the cutting patterning of the nanosheet channel layer 208-2. Figures 4A-4C A top view of the structure 575. Figure 5D 2 shows the HM layer 230 patterning and the nanosheet channel layer 208-2 after alternative cutting patterning. Figures 4A-4C A third side cross-sectional view 585 of the structure. Figure 5E 2 shows the HM layer 230 patterned and another alternative cut patterning of the nanosheet channel layer 208-2. Figures 4A-4C A fourth side cross-sectional view 595 of the structure. Figure 5A The first side cross-sectional view 500 is taken along the line AA in the top view 575, and Figure 5B , 5D The second, third and fourth side cross-sectional views 565 , 585 and 595 of FIGS. 5E are taken along lines B / D / EB / D / E in the top view 575 .

[0126] As described above, exemplary embodiments achieve flexibility in the n / p ratio by controlling the widths of nanosheet channel layers 208-1 and 208-2, wherein (i) nanosheet channel layer 208-1 may be narrower than nanosheet channel layer 208-2, (ii) nanosheet channel layer 208-1 may be wider than nanosheet channel layer 208-2, or (iii) nanosheet channel layer 208-1 may have substantially the same width as nanosheet channel layer 208-2. Figure 5B , 5D These three situations are illustrated in the different treatments shown in 5E and 5E (and subsequent similarly lettered B, D, and E figures). More specifically, Figure 5B (and subsequently in Figure 6B , 7B , 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, and 17B) illustrate the process for case (i) in which nanosheet channel layer 208-1 is formed to be narrower than nanosheet channel layer 208-2. Figure 5D(and subsequently in Fig.6D , 7D , 8D, 9D, 10D, 11D, 12D, 13D, 14D, 15D, 16D, and 17D) illustrate the process for case (ii), where nanosheet channel layer 208-1 is formed to be wider than nanosheet channel layer 208-2. Figure 5E (and subsequently in Fig. 6E , 7E , 8E, 9E, 10E, 11E, 12E, 13E, 14E, 15E, 16E, and 17E) illustrate the process for case (iii), where nanosheet channel layer 208-1 is formed to have substantially the same width as nanosheet channel layer 208-2.

[0127] It should be understood that Figure 5B , 5D The processing shown in Figures 5E and 5E (and subsequent similarly lettered Figures B, D, and E) can be performed on the same structure, for example, where Figure 5B , 5D and 5E (and subsequent similarly lettered Figures B, D, and E) are used for different parts of the structure. Although for clarity of illustration, Figure 5C In the top view 575 of Figure 6C , 7C , 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C and 17C) only show one B / D / EB / D / E line along the gate structure 203-2, but Figure 5B , 5D Different treatments of 5E (and subsequent similarly lettered Figures B, D, and E) can be used for different gate structures among gate structures 203-1, 203-2, and 203-3, or even for different portions of the length (in the Y-Y' direction) along a particular gate structure among gate structures 203-1, 203-2, and 203-3 in any desired combination.

[0128] The material of the HM layer 230 may be blanket deposited on the structure and then processed by photolithography to produce Figures 5A-5E The patterned HM layer 230 is shown. The material of the HM layer 230 may include SiN, a multilayer of SiN and SiO2, or other suitable materials. The HM layer 230 may have a height (in the Z-Z' direction) in the range of 20 to 100 nm.

[0129] Once the HM layer 230 is patterned, as Figure 5B-5E Nanosheet cutting was performed as shown. Figure 5B and 5CAn opening 501 - 1 formed by nanosheet cutting of the nanosheet channel layer 208 - 2 for case (i) is shown, terminating at the MDI layer 216 - 2 . Figure 5D An opening 501 - 2 formed by an alternative nanosheet cut of the nanosheet channel layer 208 - 2 for case (ii) is shown, which also terminates at the MDI layer 216 - 2 . Figure 5E An opening 501-3 formed by another alternative nanosheet cut of the nanosheet channel layer 208-2 for case (iii) is shown, which also terminates at the MDI layer 216-2. The widths (in the Y-Y' direction) of the openings 501-1, 501-2, and 501-3 may be in the range of 10 to 40 nm. Here, the width (in the Y-Y' direction) of the opening 501-1 is smaller than the width (in the Y-Y' direction) of the opening 501-3, and the width of the opening 501-3 is smaller than the width (in the Y-Y' direction) of the opening 501-2.

[0130] Fig. 6A After forming the protection spacer layer 232, Figures 5A-5E A first side cross-sectional view 600 of a structure. Figure 6B After forming the protection spacer layer 232, Figures 5A-5E A second side cross-sectional view 665 of the structure. Figure 6C After forming the protection spacer layer 232, Figures 5A-5E A top view of the structure 675. Fig.6D After forming the protection spacer layer 232, Figures 5A-5E A third side cross-sectional view 685 of the structure. Fig. 6E After forming the protection spacer layer 232, Figures 5A-5E A fourth side cross-sectional view 695 of the structure. Fig. 6A The first side cross-sectional view 600 is taken along the line AA in the top view 675, and Figure 6B , 6D The second, third and fourth side cross-sectional views 665 , 685 and 695 of FIGS. 6E are taken along lines B / D / EB / D / E in the top view 675 .

[0131] The protection spacer layer 232 may be formed using a conformal deposition process followed by a directional etch to remove portions of the material of the protection spacer layer on top of the HM layer 230 and the MDI layer 216-2. The protection spacer layer 232 may be made of a material such as SiC, SiO2, TiO x , aluminum nitride (AlN), etc., which can be selectively etched relative to the material of the MDI layer 216-2. The protection spacer layer 232 may have a thickness in the range of 1 to 5 nm. The protection spacer layer 232 protects the nanosheet channel layer 208-2 during subsequent processing.

[0132] Fig. 7A 2 shows the structure of the MDI layer 216-2 and the nanosheet channel layer 208-1 after etching. Figures 6A-6E A first side cross-sectional view 700 of a structure. Figure 7B 2 shows the structure of the MDI layer 216-2 and the nanosheet channel layer 208-1 after etching. Figures 6A-6E A second side cross-sectional view 765 of the structure. Figure 7C 2 shows the structure of the MDI layer 216-2 and the nanosheet channel layer 208-1 after etching. Figures 6A-6E A top view of the structure 775. Fig.7D 2 shows the structure of the MDI layer 216-2 and the nanosheet channel layer 208-1 after etching. Figures 6A-6E A third side cross-sectional view 785 of the structure. Fig. 7E 2 shows the structure of the MDI layer 216-2 and the nanosheet channel layer 208-1 after etching. Figures 6A-6E A fourth side cross-sectional view 795 of the structure. Fig. 7A The first side cross-sectional view 700 is taken along the line AA in the top view 775, and Figure 7B , 7D The second, third and fourth side cross-sectional views 765 , 785 and 795 of FIGS. 7E are taken along lines B / D / EB / D / E in the top view 775 .

[0133] A first etching process (e.g., RIE, wet etching process, etc.) is used to remove the exposed portion of the MDI layer 216-2, and then a second etching process (e.g., RIE, wet etching process, etc.) is used to remove the exposed portion of the nanosheet channel layer 208-1, stopping at the BDI layer 216-1. This produces a Figure 7B , 7D 7E and 7E. The widths of the openings 701-1, 701-2, and 701-3 (in the Y-Y' direction) may be in the range of 8 to 38 nm. Here, the width of the opening 701-1 (in the Y-Y' direction) is smaller than the width of the opening 701-3 (in the Y-Y' direction), and the width of the opening 701-3 is smaller than the width of the opening 701-2 (in the Y-Y' direction).

[0134] Fig. 8A FIG. 2 shows a nanosheet channel layer 208-1 after recessing the nanosheet channel layer 208-1 that is not covered by a patterned mask layer (eg, OPL layer 234) using a photolithography and etching process. Figures 7A-7E A first side cross-sectional view 800 of a structure. Figure 8B FIG. 2 shows the nanosheet channel layer 208 - 1 not covered by the OPL layer 234 after the recessing. Figures 7A-7E A second side cross-sectional view 865 of the structure. Figure 8CFIG. 2 shows the nanosheet channel layer 208 - 1 not covered by the OPL layer 234 after the recessing. Figures 7A-7E A top view of the structure 875. Fig.8D FIG. 2 shows the nanosheet channel layer 208 - 1 not covered by the OPL layer 234 after the recessing. Figures 7A-7E A third side cross-sectional view 885 of the structure. Fig. 8E FIG. 2 shows the nanosheet channel layer 208 - 1 not covered by the OPL layer 234 after the recessing. Figures 7A-7E A fourth side cross-sectional view 895 of the structure. Fig. 8A The first side cross-sectional view 800 is taken along line AA in the top view 875, and Figure 8B , 8D The second, third and fourth side cross-sectional views 865 , 885 and 895 of FIGS. 8E are taken along lines B / D / EB / D / E in the top view 875 .

[0135] like Fig.8D As shown, the OPL layer 234 covers the nanosheet channel layer 208-1 in the opening 701-2. The openings 701-1 and 701-3 are exposed by the OPL layer 234, and recess etching is performed to form recesses 801-1 and 801-3 in the nanosheet channel layer 208-1, respectively, as shown in FIG. Figure 8B and 8E shown.

[0136] Fig. 9A FIG. 2 shows the nanosheet channel layer 208-1 after further recessing the nanosheet channel layer 208-1 not covered by the patterned mask layer (eg, OPL layer 234) using photolithography and etching processes. Figures 8A-8E A first side cross-sectional view 900 of a structure. Fig. 9B FIG. 2 shows the nanosheet channel layer 208 - 1 after further recessing that is not covered by the OPL layer 234 . Figures 8A-8E A second side cross-sectional view of the structure 965 . Fig. 9C FIG. 2 shows the nanosheet channel layer 208 - 1 after further recessing that is not covered by the OPL layer 234 . Figures 8A-8E A top view of the structure 975. Fig.9D FIG. 2 shows the nanosheet channel layer 208 - 1 after further recessing that is not covered by the OPL layer 234 . Figures 8A-8E A third side cross-sectional view of the structure 985 . Fig.9E FIG. 2 shows the nanosheet channel layer 208 - 1 after further recessing that is not covered by the OPL layer 234 . Figures 8A-8E A fourth side cross-sectional view of the structure 995 . Fig. 9A The first side cross-sectional view 900 is taken along line AA in the top view 975, and Fig. 9B , 9DThe second, third and fourth side cross-sectional views 965 , 985 and 995 of FIGS. 9E are taken along lines B / D / EB / D / E in the top view 975 .

[0137] like Fig.9D and 9E As shown, the OPL layer 234 is now formed to cover the nanosheet channel layer 208-1 in the openings 701-2 and 701-3. The opening 701-1 is exposed by the OPL layer 234, and an additional groove etch is performed to form an additional groove 901 in the nanosheet channel layer 208-1, as shown in FIG. Fig. 9B Therefore, the width of the groove 901 (in the XX' direction) exceeds the width of the groove 801-3 (in the XX' direction).

[0138] Fig. 10A The OPL layer 234 and the protection spacer layer 232 are shown after removal. Figures 9A-9E A first side cross-sectional view 1000 of a structure. Fig. 10B The OPL layer 234 and the protection spacer layer 232 are shown after removal. Figures 9A-9E A second side cross-sectional view 1065 of the structure. Fig. 10C The OPL layer 234 and the protection spacer layer 232 are shown after removal. Figures 9A-9E A top view of the structure 1075. Fig. 10D The OPL layer 234 and the protection spacer layer 232 are shown after removal. Figures 9A-9E A third side cross-sectional view 1085 of the structure. Fig.10E The OPL layer 234 and the protection spacer layer 232 are shown after removal. Figures 9A-9E A fourth side cross-sectional view 1095 of the structure. Fig. 10A The first side cross-sectional view 1000 is taken along the line AA in the top view 1075, and Fig. 10B , 10D The second, third and fourth side cross-sectional views 1065 , 1085 and 1095 of 10E are taken along lines B / D / EB / D / E in the top view 1075 .

[0139] The OPL layer 234 and the protective spacer layer 232 may be removed using any suitable etching process that selectively removes material of the OPL layer 234 and the protective spacer layer 232 relative to material of the remaining structure.

[0140] Fig.11A FIG. 2 shows the dielectric pillar layer 236 after it is formed in the openings 701-1, 701-2, and 701-3 and the recesses 801-3 and 901. Figures 10A-10E A first side cross-sectional view 1100 of a structure. Fig. 11BThe structure of the dielectric pillar layer 236 after forming the dielectric pillar layer 236 in the openings 701-1, 701-2, 701-3 and the grooves 801-3, 901 is shown. FIG. 10A to FIG. 10E A second side cross-sectional view 1165 of the structure. Fig. 11C FIG. 2 shows the dielectric pillar layer 236 after it is formed in the openings 701-1, 701-2, and 701-3 and the recesses 801-3 and 901. Figures 10A-10E A top view of the structure 1175. Fig.11D The structure of the dielectric pillar layer 236 after forming the dielectric pillar layer 236 in the openings 701-1, 701-2, 701-3 and the grooves 801-3, 901 is shown. FIG. 10A to FIG. 10E A third side cross-sectional view 1185 of the structure. Fig.11E FIG. 2 shows the dielectric pillar layer 236 after it is formed in the openings 701-1, 701-2, and 701-3 and the recesses 801-3 and 901. Figures 10A-10E A fourth side cross-sectional view 1195 of the structure. Fig.11A The first side cross-sectional view 1100 is taken along line AA in the top view 1175, and Fig. 11B , 11D The second, third and fourth side cross-sectional views 1165 , 1185 and 1195 of FIGS. 11E and 1175 are taken along lines B / D / EB / D / E in the top view 1175 .

[0141] The dielectric pillar layer 236 may be filled with a dielectric material such as SiN, SiO2, SiOC, SiOCN, SiBCN, SiC, etc., and then planarized using CMP or other suitable processes, stopping on the top surface of the HM layer 230. Fig. 11B and 11E As shown, the dielectric pillar layer 236 has a fork-like shape filling the grooves 801 - 3 and 901 .

[0142] Fig. 12A Figure 2 shows the process after forming the middle of the line (MOL) contacts, front side BEOL interconnects and carrier wafer bonding. Figures 11A-11E A first side cross-sectional view 1200 of a structure. Fig. 12B Shown after forming MOL contacts, front-side BEOL interconnects, and carrier wafer bonding Figures 11A-11E A second side cross-sectional view 1265 of the structure. Fig. 12C Shown after forming MOL contacts, front-side BEOL interconnects, and carrier wafer bonding Figures 11A-11E A top view of the structure 1275. Fig.12D Shown after forming MOL contacts, front-side BEOL interconnects, and carrier wafer bonding Figures 11A-11E A third side cross-sectional view 1285 of the structure. Fig.12EShown after forming MOL contacts, front-side BEOL interconnects, and carrier wafer bonding Figures 11A-11E A fourth side cross-sectional view 1295 of the structure. Fig. 12A The first side cross-sectional view 1200 is taken along line AA in the top view 1275, and Fig. 12B , 12D The second, third and fourth side cross-sectional views 1265 , 1285 and 1295 of FIGS. 12E are taken along lines B / D / EB / D / E in the top view 1275 .

[0143] The formation of MOL contacts, front side BEOL interconnects, and carrier wafer bonding includes the formation of the ILD layer 238 , bottom source / drain contacts 240 , top source / drain contacts 242 , gate contacts 244 , front side BEOL interconnects 246 , and bonding of the structure (e.g., front side BEOL interconnects 246 ) to a carrier wafer 248 .

[0144] The ILD layer 238 may be formed of a material similar to that of the ILD layer 218. The ILD layer 238 may have a height (in the ZZ' direction) in the range of 20 to 100 nm.

[0145] The bottom source / drain contact 240, the top source / drain contact 242, and the gate contact 244 may include a silicide layer such as titanium (Ti), nickel (Ni), nickel platinum (NiPt), etc., and a metal adhesion layer (e.g., such as TiN) and a low resistance metal such as ruthenium (Ru), tungsten (W), cobalt (Co), or other suitable materials. Each of the bottom source / drain contact 240, the top source / drain contact 242, and the gate contact 244 may have a width (in the X-X' or Y-Y' direction) in the range of 8 to 50 nm, and a height (in the Z-Z' direction) extending from the bottom surface of the front-side BEOL interconnect 246 to the portion of the structure it contacts (e.g., the bottom source / drain region 222 of the bottom source / drain contact 240, the top source / drain region 224 of the top source / drain contact 242, and the gate stack layer 214 of the gate contact 244).

[0146] Front side BEOL interconnect 246 includes various BEOL interconnect structures. Carrier wafer 248 may be formed of a material similar to substrate 202 and may be formed on front side BEOL interconnect 246 using a wafer bonding process, such as dielectric-to-dielectric bonding.

[0147] Fig.13A 204 after removing a portion of the substrate 202 and stopping on the etch stop layer 204. Figures 12A-12E A first side cross-sectional view 1300 of a structure. Fig. 13B204 after removing a portion of the substrate 202 and stopping on the etch stop layer 204. Figures 12A-12E A second side cross-sectional view 1365 of the structure. Fig. 13C 204 after removing a portion of the substrate 202 and stopping on the etch stop layer 204. Figures 12A-12E A top view of the structure 1375. Fig.13D 204 after removing a portion of the substrate 202 and stopping on the etch stop layer 204. Figures 12A-12E A third side cross-sectional view 1385 of the structure. Fig.13E 204 after removing a portion of the substrate 202 and stopping on the etch stop layer 204. Figures 12A-12E A fourth side cross-sectional view 1395 of the structure. Fig.13A The first side cross-sectional view 1300 is taken along line AA in the top view 1375, and Fig. 13B , 13D The second, third and fourth side cross-sectional views 1365 , 1385 and 1395 of 13E are taken along lines B / D / EB / D / E in the top view 1375 .

[0148] Using carrier wafer 248, the structure can be "flipped" and portions of substrate 202 can be removed from the back side. Figures 13A-13E As shown, removal of a portion of substrate 202 will stop on etch stop layer 204 .

[0149] Fig.14A 2 shows the etching stop layer 204 and the remaining portion of the substrate 202 after removal. Figures 13A-13E A first side cross-sectional view 1400 of a structure. Fig. 14B 2 shows the etching stop layer 204 and the remaining portion of the substrate 202 after removal. Figures 13A-13E A second side cross-sectional view 1465 of the structure. Fig. 14C 2 shows the etching stop layer 204 and the remaining portion of the substrate 202 after removal. Figures 13A-13E A top view of the structure 1475. Fig.14D 2 shows the etching stop layer 204 and the remaining portion of the substrate 202 after removal. Figures 13A-13E A third side cross-sectional view 1485 of the structure. Fig.14E 2 shows the etching stop layer 204 and the remaining portion of the substrate 202 after removal. Figures 13A-13E A fourth side cross-sectional view 1495 of the structure. Fig.14A The first side cross-sectional view 1400 is taken along line AA in the top view 1475, and Fig. 14B , 14D The second, third and fourth side cross-sectional views 1465 , 1485 and 1495 of 14E are taken along lines B / D / EB / D / E in the top view 1475 .

[0150] like Figures 14A-14E As shown, the etch stop layer 204 is removed, followed by removal of the remaining portion of the substrate 202 to expose the BDI layer 216 - 1 and the sacrificial placeholder layer 220 .

[0151] Fig.15A shows the backside ILD layer 250 after it is formed. Figures 14A-14E A first side cross-sectional view 1500 of a structure. Fig. 15B shows the backside ILD layer 250 after it is formed. Figures 14A-14E A second side cross-sectional view 1565 of the structure. Fig. 15C shows the backside ILD layer 250 after it is formed. Figures 14A-14E A top view of the structure 1575. Fig.15D shows the backside ILD layer 250 after it is formed. Figures 14A-14E A third side cross-sectional view 1585 of the structure. Fig.15E shows the backside ILD layer 250 after it is formed. Figures 14A-14E A fourth side cross-sectional view 1595 of the structure. Fig.15A The first side cross-sectional view 1500 is taken along line AA in the top view 1575, and Fig. 15B , 15D The second, third and fourth side cross-sectional views 1565 , 1585 and 1595 of 15E are taken along lines B / D / EB / D / E in the top view 1575 .

[0152] Backside ILD layer 250 may be formed of similar materials as ILD layer 238. The material of backside ILD layer 250 may be initially overfilled, followed by planarization (eg, using CMP), with planarization stopping on sacrificial placeholder layer 220 and STI regions 212 as shown.

[0153] Fig.16A shows the structure after removing the sacrificial placeholder layer 220. Figures 15A-15E 1600. The sacrificial placeholder layer 220 may be removed using any suitable etching process that selectively removes material of the sacrificial placeholder layer 220 relative to the remainder of the structure. Fig. 16B shows the structure after removing the sacrificial placeholder layer 220. Figures 15A-15E A second side cross-sectional view 1665 of the structure. Fig. 16C shows the structure after removing the sacrificial placeholder layer 220. Figures 15A-15E A top view of the structure 1675. Fig.16D shows the structure after removing the sacrificial placeholder layer 220. Figures 15A-15E A third side cross-sectional view 1685 of the structure. Fig.16Eshows the structure after removing the sacrificial placeholder layer 220. Figures 15A-15E A fourth side cross-sectional view 1695 of the structure. Fig.16A The first side cross-sectional view 1600 is taken along line AA of the top view 1675, and Fig. 16B , 16D The second, third and fourth side cross-sectional views 1665 , 1685 and 1695 of 16E are taken along lines B / D / EB / D / E of the top view 1675 .

[0154] Fig.17A shows the backside bottom source / drain contacts 252 and backside interconnects 254 after formation. Figures 16A-16E A first side cross-sectional view 1700 of a structure. Fig. 17B shows the backside bottom source / drain contacts 252 and backside interconnects 254 after formation. Figures 16A-16E A second side cross-sectional view 1765 of the structure. Fig. 17C shows the backside bottom source / drain contacts 252 and backside interconnects 254 after formation. Figures 16A-16E Top view of the structure 1775. Fig.17D shows the backside bottom source / drain contacts 252 and backside interconnects 254 after formation. Figures 16A-16E A third side cross-sectional view 1785 of the structure. Fig.17E 254 after forming the backside bottom source / drain contacts 252 and the backside interconnects 254. Figures 16A-16E A fourth side cross-sectional view 1795 of the structure. Fig.17A The first side cross-sectional view 1700 is taken along line AA in the top view 1775, and Fig. 17B , 17D The second, third and fourth side cross-sectional views 1765 , 1785 and 1795 of 17E are taken along lines B / D / EB / D / E in the top view 1775 .

[0155] The backside bottom source / drain contact 252 may be formed by filling and planarizing the contact material. The contact material of the backside bottom source / drain contact 252 may be similar to the contact material of the top source / drain contact 242, the bottom source / drain contact 240, and the gate contact 244. The backside bottom source / drain contact 252 may have a width (in the XX' direction) that matches the width of the bottom source / drain region 222.

[0156] The backside interconnect 254 may be formed with similar dimensions and composition to the dimensions and composition of the frontside BEOL interconnect 246 .

[0157] Semiconductor devices and methods of forming the same according to the above-mentioned techniques can be used in various applications, hardware and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones and smart phones), solid-state media storage devices, functional circuits, etc. Systems and hardware in conjunction with semiconductor devices are contemplated embodiments of the present invention. Given the teachings provided herein, one of ordinary skill in the art will be able to envision other implementations and applications of embodiments of the present invention.

[0158] In some embodiments, the above techniques are used in conjunction with semiconductor devices that may require or otherwise utilize, for example, complementary metal oxide semiconductors (CMOS), metal oxide semiconductor field effect transistors (MOSFETs), and / or fin field effect transistors (FinFETs). As non-limiting examples, semiconductor devices may include, but are not limited to, CMOS, MOSFET, and FinFET devices, and / or semiconductor devices using CMOS, MOSFET, and / or FinFET technology.

[0159] The various structures described above can be implemented in an integrated circuit. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier with leads that are fixed to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with one or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of any of the following: (a) an intermediate product, such as a motherboard, or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units. Fig.18 An example integrated circuit 1800 is shown that includes one or more CFET device structures 1810 having isolation pillar structures with varying widths.

[0160] In some embodiments, a microelectronic structure includes a first stacked device structure, a second stacked device structure, and an isolation column structure, wherein the first stacked device structure includes a first upper device and a first lower device, the second stacked device structure includes a second upper device and a second lower device, and the isolation column structure is located between the first and second stacked device structures. The isolation column structure has an upper section that contacts the first and second upper devices and a lower section that contacts the first and second lower devices. The upper section of the isolation column structure has a first width, and the lower section of the isolation column structure has a second width different from the first width.

[0161] The first and second upper devices and the first and second lower devices may include respective FET devices.

[0162] The first and second upper devices and the first and second lower devices may include respective nanosheet FET devices.

[0163] The first and second stacked device structures may provide a CFET structure.

[0164] One of the first upper device and the first lower device in the first stacked device structure may include an nFET device, and the other of the first upper device and the second lower device in the first stacked device structure may include a pFET device. The first width of the upper section of the isolation pillar and the second width of the lower section of the isolation pillar control the ratio of the size of the n-type active area of ​​the nFET device to the size of the p-type active area of ​​the pFET device.

[0165] In some embodiments, a microelectronic structure includes: a first stacked FET structure, which includes a first lower FET device and a first upper FET device; a second stacked FET structure, which includes a second lower FET device and a second upper FET device; and an isolation column structure, which is located between the first stacked FET structure and the second stacked FET structure, the isolation column structure having an upper section with a first width and a lower section with a second width different from the first width.

[0166] The upper section of the isolation column structure can contact the channels of the first and second upper FET devices in the first and second stacked FET structures, and the lower section of the isolation column structure can contact the channels of the first and second lower FET devices in the first and second stacked FET structures. The isolation column structure can separate the channels, gates, and source / drain regions of the first and second upper and lower FET devices in the first and second stacked FET structures.

[0167] A first width of an upper section of the isolation pillar structure may be greater than a second width of a lower section of the isolation pillar structure.

[0168] The isolation pillar structure may also include an extension section extending outwardly from the lower section toward the recesses in the channels of the first and second lower FET devices in the first and second stacked FET structures.

[0169] Channels of the first and second upper FET devices in the first and second stacked FET structures may have a greater width than channels of the first and second lower FET devices in the first and second stacked FET structures.

[0170] Channels of the first and second upper FET devices in the first and second stacked FET structures may have a smaller width than channels of the first and second lower FET devices in the first and second stacked FET structures.

[0171] The channels of the first and second upper FET devices in the first and second stacked FET structures may have the same width as the channels of the first and second lower FET devices in the first and second stacked FET structures.

[0172] In some embodiments, an integrated circuit includes a CFET structure, which includes a first stacked FET structure, a second stacked FET structure, and an isolation column structure between the first stacked FET structure and the second stacked FET structure, the first stacked FET structure includes a first lower FET device and a first upper FET device, the second stacked FET structure includes a second lower FET device and a second upper FET device, and the isolation column structure has an upper section with a first width and a lower section with a second width different from the first width.

[0173] The upper section of the isolation column structure may contact the channels of the first and second upper FET devices in the first and second stacked FET structures, and the lower section of the isolation column structure may contact the channels of the first and second lower FET devices in the first and second stacked FET structures.

[0174] In some embodiments, a microelectronic structure includes two or more stacked FET structures, each of the two or more stacked FET structures includes two or more FET devices stacked on each other, and an isolation pillar structure separating a first and a second stacked FET structure in the two or more stacked FET structures. The isolation pillar structure includes a first section and a second section, the first section contacts a channel of at least a first FET device in the two or more FET devices in the first and second stacked FET structures, and the second section contacts a channel of at least a second FET device in the two or more FET devices in the first and second stacked FET structures. The first section of the isolation pillar structure has a first width, and the second section of the isolation pillar structure has a second width different from the first width.

[0175] A first FET device of the two or more FET devices may include an nFET device, and a second FET device of the two or more FET devices may include a pFET device. A first width of the isolation pillar structure may define a first active area region of the nFET device, and a second width of the isolation pillar may define a second active area region of the pFET device.

[0176] The microelectronic structure may also include an additional isolation column structure separating a third and a fourth stacked FET structure in two or more stacked FET structures, wherein the additional isolation column structure includes a first segment and a second segment, the first segment contacts a channel of at least a first FET device in two or more FET devices in the third and fourth stacked FET structures, the second segment contacts a channel of at least a second FET device in two or more FET devices in the third and fourth stacked FET structures, wherein the first segment of the additional isolation column structure has a third width, and the second segment of the isolation column structure has a fourth width different from the third width, and wherein the third width is different from the first width and the fourth width is different from at least one of the second width.

[0177] In some embodiments, a method includes forming first and second stacked FET device structures, each of the first and second stacked FET devices including an upper FET device and a lower FET device, wherein the upper FET device of the first and second stacked FET device structures has a merged channel, and wherein the lower FET device of the first and second stacked FET device structures has a merged channel. The method also includes forming an isolation column structure between the first and second stacked FET structures, the isolation column structure including an upper section having a first width and a lower section having a second width different from the first width, the upper section separating the merged channels of the upper FET devices of the first and second stacked FET device structures, and the lower section separating the merged channels of the lower FET devices of the first and second stacked FET device structures.

[0178] Forming the isolation column structure may include performing a first cutting process to etch through a merged channel of an upper FET device of the first and second stacked FET device structures, the first cutting process stopping on an intermediate dielectric isolation layer disposed between the upper FET device and the lower FET device of the first and second stacked FET device structures, forming a protective spacer on an exposed sidewall of the channel of the upper FET device of the first and second stacked FET device structures, and performing a second cutting process to etch through a merged channel of a lower FET device of the first and second stacked FET device structures, the second cutting process stopping on a bottom dielectric isolation layer disposed below the lower FET device of the first and second stacked FET device structures.

[0179] Forming the spacer structure may also include performing a recess etch that removes a portion of the channel of the lower FET device.

[0180] Forming the isolation column structure may also include removing the protection spacer, and filling the space exposed by the first cutting process, the second cutting process and the groove etching with a dielectric material. The groove etching controls the ratio of the lower active area of ​​the lower FET device to the upper active area of ​​the upper FET device. The lower FET device may include one of an nFET device and a pFET device, and the upper FET device may include the other of the nFET device and the pFET device.

[0181] It should be understood that the layers, structures, and regions shown in the figures are schematic diagrams that are not drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions of the type commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure. This does not mean that any layers, structures, and regions that are not explicitly shown are omitted from the actual semiconductor structure. In addition, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it should be emphasized that the description provided herein is not intended to include all processing steps that may be required to form a functional semiconductor integrated circuit device. On the contrary, for the sake of economy of description, certain processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, are purposefully not described here.

[0182] In addition, the same or similar reference numerals are used in all drawings to represent the same or similar features, elements or structures, and therefore, the detailed explanation of the same or similar features, elements or structures is not repeated for each drawing. It should be understood that the terms "approximately" or "substantially" used herein with respect to thickness, width, percentage, range, temperature, time and other process parameters, etc., are meant to indicate close or approximate, but not exact. For example, as used herein, the term "approximately" or "substantially" implies that there is a small margin of error, such as ±5%, preferably less than 2% or 1% or less than the amount.

[0183] In the above description, various materials, dimensions and processing parameters for different elements are provided. Unless otherwise specified, these materials are given by way of example only, and the embodiments are not limited to the specific examples given. Similarly, unless otherwise specified, all dimensions and processing parameters are given by way of example, and the embodiments are not limited to the specific dimensions or ranges given.

[0184] The description of various embodiments of the present invention has been given for the purpose of illustration, but it is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A microelectronic structure comprising: a first stacked device structure comprising a first upper device and a first lower device; a second stacked device structure including a second upper device and a second lower device; an isolation column structure located between the first and second stacked device structures; wherein the isolation pillar structure has an upper section contacting the first and second upper devices and a lower section contacting the first and second lower devices; and The upper section of the isolation column structure has a first width, and the lower section of the isolation column structure has a second width different from the first width.

2. The microelectronic structure of claim 1 wherein the first and second upper devices and the first and second lower devices comprise respective field effect transistor devices.

3. The microelectronic structure of claim 1, wherein the first and second upper devices and the first and second lower devices comprise respective nanosheet field effect transistor devices.

4. The microelectronic structure of claim 1 wherein the first and second stacked device structures provide complementary field effect transistor structures.

5. The microelectronic structure of claim 1 , wherein one of the first upper device and the first lower device in the first stacked device structure comprises an n-type field effect transistor device, and the other of the first upper device and the second lower device in the first stacked device structure comprises a p-type field effect transistor device.

6. The microelectronic structure of claim 5, wherein the first width of the upper section of the isolation column and the second width of the lower section of the isolation column control a ratio of an n-type active area size of the n-type field effect transistor device to a p-type active area size of the p-type field effect transistor device.

7. A microelectronic structure comprising: a first stacked field effect transistor structure including a first lower field effect transistor device and a first upper field effect transistor device; a second stacked field effect transistor structure including a second lower field effect transistor device and a second upper field effect transistor device; as well as An isolation column structure is between the first stacked field effect transistor structure and the second stacked field effect transistor structure, the isolation column structure having an upper section with a first width and a lower section with a second width different from the first width.

8. A microelectronic structure according to claim 7, wherein the upper section of the isolation column structure contacts the channels of the first and second upper field effect transistor devices in the first and second stacked field effect transistor structures, and wherein the lower section of the isolation column structure contacts the channels of the first and second lower field effect transistor devices in the first and second stacked field effect transistor structures.

9. The microelectronic structure of claim 7, wherein the spacer structure separates channel, gate, and source / drain regions of the first and second upper and lower field effect transistor devices in the first and second stacked field effect transistor structures.

10. The microelectronic structure of claim 7, wherein the first width of the upper section of the spacer structure is greater than the second width of the lower section of the spacer structure.

11. The microelectronic structure of claim 7, wherein the spacer structure further comprises an extension section extending outwardly from the lower section toward recesses in channels of the first and second lower field effect transistor devices in the first and second stacked field effect transistor structures.

12. The microelectronic structure of claim 7, wherein a width of a channel of the first and second upper field effect transistor devices in the first and second stacked field effect transistor structures is greater than a width of a channel of the first and second lower field effect transistor devices in the first and second stacked field effect transistor structures.

13. The microelectronic structure of claim 7, wherein a width of a channel of the first and second upper field effect transistor devices in the first and second stacked field effect transistor structures is smaller than a width of a channel of the first and second lower field effect transistor devices in the first and second stacked field effect transistor structures.

14. The microelectronic structure of claim 7, wherein channels of the first and second upper field effect transistor devices in the first and second stacked field effect transistor structures have the same width as channels of the first and second lower field effect transistor devices in the first and second stacked field effect transistor structures.

15. An integrated circuit comprising: Complementary field effect transistor structure, comprising: a first stacked field effect transistor structure including a first lower field effect transistor device and a first upper field effect transistor device; a second stacked field effect transistor structure including a second lower field effect transistor device and a second upper field effect transistor device; and An isolation column structure is between the first stacked field effect transistor structure and the second stacked field effect transistor structure, the isolation column structure having an upper section with a first width and a lower section with a second width different from the first width.

16. An integrated circuit according to claim 15, wherein the upper section of the isolation column structure contacts the channels of the first and second upper field effect transistor devices in the first and second stacked field effect transistor structures, and wherein the lower section of the isolation column structure contacts the channels of the first and second lower field effect transistor devices in the first and second stacked field effect transistor structures.

17. A microelectronic structure comprising: two or more stacked field effect transistor structures, each of the two or more stacked field effect transistor structures comprising two or more field effect transistor devices stacked on one another; as well as an isolation pillar structure separating first and second stacked field effect transistor structures of the two or more stacked field effect transistor structures; wherein the isolation column structure comprises a first section and a second section, the first section contacts a channel of at least a first field effect transistor device among the two or more field effect transistor devices in the first and second stacked field effect transistor structures of the two or more stacked field effect transistor structures, and the second section contacts a channel of at least a second field effect transistor device among the two or more field effect transistor devices in the first and second stacked field effect transistor structures of the two or more stacked field effect transistor structures; as well as The first section of the isolation column structure has a first width, and the second section of the isolation column structure has a second width different from the first width.

18. The microelectronic structure of claim 17, wherein the first of the two or more field effect transistor devices comprises an n-type field effect transistor device and the second of the two or more field effect transistor devices comprises a p-type field effect transistor device, and wherein the first width of the isolation pillar structure defines a first active area region of the n-type field effect transistor device and the second width of the isolation pillar defines a second active area region of the p-type field effect transistor device.

19. The microelectronic structure of claim 17, further comprising an additional isolation pillar structure separating a third and a fourth stacked field effect transistor structure of the two or more stacked field effect transistor structures, wherein: The additional isolation column structure includes a first section and a second section, the first section contacts the channel of at least a first field effect transistor device among the two or more field effect transistor devices in the third and fourth stacked field effect transistor structures among the two or more stacked field effect transistor structures, and the second section contacts the channel of at least a second field effect transistor device among the two or more field effect transistor devices in the third and fourth stacked field effect transistor structures among the two or more stacked field effect transistor structures, wherein the first section of the additional isolation column structure has a third width, and the second section of the isolation column structure has a fourth width different from the third width, and wherein the third width is different from at least one of the first width and the fourth width is different from the second width.

20. A method comprising: forming first and second stacked field effect transistor device structures, each of the first and second stacked field effect transistor device structures comprising an upper field effect transistor device and a lower field effect transistor device, wherein the upper field effect transistor device of the first and second stacked field effect transistor device structures has a merged channel, and wherein the lower field effect transistor device of the first and second stacked field effect transistor device structures has a merged channel; as well as An isolation column structure is formed between the first and second stacked field effect transistor structures, the isolation column structure including an upper section having a first width and a lower section having a second width different from the first width, the upper section separating the merged channels of the upper field effect transistor device of the first and second stacked field effect transistor device structures, and the lower section separating the merged channels of the lower field effect transistor device of the first and second stacked field effect transistor device structures.

21. The method according to claim 20, wherein forming the isolation column structure comprises: performing a first cutting process, the first cutting process etching through the merged channel of the upper field effect transistor device of the first and second stacked field effect transistor device structures, the first cutting process stopping on an intermediate dielectric isolation layer, the intermediate dielectric isolation layer disposed between the upper field effect transistor device and the lower field effect transistor device of the first and second stacked field effect transistor device structures; forming a protection spacer on an exposed sidewall of the merged channel of the upper field effect transistor device of the first and second stacked field effect transistor device structures; as well as A second cutting process is performed, wherein the second cutting process etches through the merged channel of the lower field effect transistor device of the first and second stacked field effect transistor device structures, and the second cutting process stops on a bottom dielectric isolation layer, wherein the bottom dielectric isolation layer is disposed below the lower field effect transistor device of the first and second stacked field effect transistor device structures. The method of claim 21, wherein forming the isolation pillar structure further comprises performing a recess etch that removes a portion of the merged channel of the lower field effect transistor device.

22. The method according to claim 22, wherein forming the isolation column structure further comprises: removing the guard spacer; as well as A dielectric material is filled in the spaces exposed by the first cutting process, the second cutting process, and the recess etching.

23. The method of claim 22, wherein the recess etch controls a ratio of a lower active area region of the lower field effect transistor device to an upper active area region of the upper field effect transistor device.

24. The method of claim 24, wherein the lower field effect transistor device comprises one of an n-type field effect transistor device and a p-type field effect transistor device, and the upper field effect transistor device comprises the other of the n-type field effect transistor device and the p-type field effect transistor device.

Images