Semiconductor device, electronic device, and vehicle

Abstract

The invention relates to a semiconductor device, an electronic machine and a vehicle. And the output leakage current characteristic is improved. A semiconductor device according to the present disclosure includes a semiconductor substrate, a well formed in the semiconductor substrate, an output terminal electrically connected to the semiconductor substrate, a ground terminal to which a ground voltage is applied, and a detection signal generation circuit that generates a negative current detection signal when detecting that an output voltage of the output terminal is lower than the ground voltage. And a control circuit that applies a ground voltage or an output voltage to the well in accordance with the negative current detection signal. The detection signal generation circuit includes a comparator that compares an output detection voltage (Vs) and a ground voltage to generate a negative current detection signal, a bias circuit that applies an output voltage or a bias voltage as the output detection voltage (Vs), and a clamp circuit (CLP) that operates when Vs > VCLP.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and an electronic device and a vehicle using the semiconductor device. Background Art

[0002] The applicant of this case has proposed many new technologies so far regarding semiconductor devices such as automotive IPDs [intelligent power devices] (for example, high-side switch LSIs [large scale integration] or low-side switch LSIs) (for example, refer to Patent Document 1).

[0003] [Background Technology Literature]

[0004] [Patent Document]

[0005] [Patent Document 1] International Publication No. 2017 / 187785 Summary of the invention

[0006] However, there is still room for further research on preventing malfunction of parasitic elements in semiconductor devices such as automotive IPDs.

[0007] The semiconductor device disclosed in the present invention comprises: a semiconductor substrate of a first conductivity type; a well of a second conductivity type, which is different from the first conductivity type formed in the semiconductor substrate; an output terminal, which is configured to be electrically connected to the semiconductor substrate; a ground terminal, which is configured to be applied with a ground voltage; a detection signal generating circuit, which is configured to detect a situation where an output voltage appearing at the output terminal is lower than the ground voltage or a threshold voltage and generate a negative current detection signal; and a control circuit, which is configured to switch whether to apply the ground voltage or the output voltage to the well according to the negative current detection signal; and the detection signal generating circuit comprises: a comparator, which is configured to compare the output detection voltage with the ground voltage or the threshold voltage and generate the negative current detection signal; a bias circuit, which is configured to switch whether to apply the output voltage or a bias voltage as the output detection voltage; and a clamping circuit, which is configured to act when the absolute value of the output detection voltage is higher than the clamping action voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a diagram showing the overall structure of a semiconductor device.

[0009] Figure 2 This is a diagram showing a configuration example (first stage) of an electronic device.

[0010] Figure 3 This is a diagram showing a configuration example (second stage) of an electronic device.

[0011] Figure 4 This is a diagram showing a configuration example (third stage) of an electronic device.

[0012] Figure 5 It is a diagram showing a first embodiment of a negative current detection circuit.

[0013] Figure 6 It is a diagram showing a first operating state of the negative current detection circuit.

[0014] Figure 7 It is a diagram showing the second operating state of the negative current detection circuit.

[0015] Figure 8 It is a diagram showing the third operating state of the negative current detection circuit.

[0016] Fig. 9 It is a diagram showing the fourth operating state of the negative current detection circuit.

[0017] Fig.10 This is a diagram showing the behavior when a negative current is generated (without a negative current detection circuit).

[0018] Fig.11 It is a diagram showing a longitudinal section of a semiconductor device (without a negative current detection circuit).

[0019] Fig.12 This diagram shows the behavior when a negative current is generated (with a negative current detection circuit).

[0020] Fig.13 This is a diagram showing a longitudinal section of a semiconductor device (with a negative current detection circuit).

[0021] Fig.14 This is a diagram showing the behavior when the output is turned off (first leakage condition) in the first embodiment.

[0022] Fig.15 It is a diagram showing the relationship between the output voltage and the output leakage current in the first embodiment (first leakage condition).

[0023] Fig.16 This is a diagram showing the behavior when the output is turned off (second leakage condition) in the first embodiment.

[0024] Fig.17 It is a diagram showing the relationship between the output voltage and the output leakage current in the first embodiment (second leakage condition).

[0025] Fig.18 It is a graph showing the output leakage current characteristics in the first embodiment.

[0026] Fig.19 It is a diagram showing a second embodiment of a negative current detection circuit.

[0027] Fig. 20 This is a diagram showing the behavior when the output is turned off (first leakage condition) in the second embodiment.

[0028] Fig.21 It is a diagram showing the relationship between the output voltage and the output leakage current in the second embodiment (first leakage condition).

[0029] Fig. 22 This is a diagram showing the behavior when the output is turned off (second leakage condition) in the second embodiment.

[0030] Fig.23 It is a diagram showing the relationship between the output voltage and the output leakage current (second leakage condition) in the second embodiment.

[0031] Fig.24 It is a graph showing the output leakage current characteristics in the second embodiment.

[0032] Fig.25 It is a graph showing the effect of improving the output leakage current characteristics.

[0033] Fig.26 A diagram showing the appearance of a vehicle. DETAILED DESCRIPTION

[0034] <Semiconductor devices>

[0035] Figure 1 The semiconductor device 1 of this configuration example is a low-side switch LSI (a type of vehicle-mounted IPD) for use in a vehicle that switches on and off between a load and a ground terminal according to an external control signal IN and an external start signal EN output from an ECU (electronic control unit) not shown.

[0036] The semiconductor device 1 has external terminals T1 to T7 as a mechanism for establishing an electrical connection with the outside of the device. The external terminal T1 is a power supply terminal for accepting the supply of the power supply voltage VDD. The external terminals T2 and T3 are signal input terminals for accepting external inputs of the external start signal EN and the external control signal IN, respectively. The external terminal T4 is a load connection terminal for externally connecting a load (a light bulb, a relay coil, a solenoid, a light emitting diode or a motor, etc.). In addition, the external terminal T4 can also be understood as an output terminal to which the output voltage OUT is applied. The external terminal T5 is a slew rate adjustment terminal for accepting external input of the slew rate adjustment signal SR. The external terminal T6 is a signal output terminal for externally outputting the state signal ST. The external terminal T7 is a ground terminal.

[0037] In addition, according to the description of this figure, the semiconductor device 1 integrates a power transistor 10 (for example, NMOSFET [N-channeltype metal oxide semiconductor field effect transistor: N-channel type metal oxide semiconductor field effect transistor]), a sensing transistor 20 (for example, NMOSFET), a gate control system 30, a logic device 40, an input system 50, a reference system 60, a protection system 70, a status output unit 80, and current limiting resistors 91 and 92.

[0038] The drain of the power transistor 10 is connected to the external terminal T4. The source of the power transistor 10 is connected to the external terminal T7. The gate of the power transistor 10 is connected to the application end of the gate drive signal G1. The power transistor 10 connected in this way functions as a lower switch element for turning on / off the current path of the output current Io from the external terminal T4 to the external terminal T7. In addition, the power transistor 10 becomes an on state when the gate drive signal G1 is at a high level, and becomes an off state when the gate drive signal G1 is at a low level. In addition, the power transistor 10 only needs to be designed in such a way that the on resistance Ron becomes tens of mΩ.

[0039] The sensing transistor 20 is a current detection element whose gate and drain are commonly connected to the power transistor 10. The sensing transistor 20 generates a sensing current Is corresponding to the output current Io flowing through the power transistor 10. The size ratio of the power transistor 10 to the sensing transistor 20 is m:1 (where m>1). Therefore, the sensing current Is becomes the size of the output current Io reduced to 1 / m. In addition, the sensing transistor 20, like the power transistor 10, becomes the on state when the gate drive signal G1 is at a high level, and becomes the off state when the gate drive signal G1 is at a low level.

[0040] The gate control system 30 generates a gate driving signal G1 according to a gate control signal S1 from a logic unit 40 to perform on / off control of the power transistor 10 and the sensing transistor 20. For example, the gate control system 30 includes a slew rate control circuit 31, an active clamp circuit 32, a gate resistor 33, and a transistor 34 (NMOSFET in this figure).

[0041] The slew rate control circuit 31 operates by receiving the supply of the power supply voltage VDD from the external terminal T1 via the path of the current limiting resistor 91. The slew rate control circuit 31 includes, for example, a reference current source REF, a charging section CHG, and a discharging section DCHG. The reference current source REF generates a reference current Iref corresponding to the slew rate adjustment signal SR externally input to the external terminal T5. The charging section CHG generates a charging current Ichg corresponding to the reference current Iref. The discharging section DCHG generates a discharging current Idchg corresponding to the reference current Iref. The slew rate control circuit 31 generates a gate drive signal G1 through charge-discharge control corresponding to the gate control signal S1.

[0042] The active clamp circuit 32 is connected between the external terminal T4 and the gate of the power transistor 10. In an application where an inductive load is connected to the external terminal T4, when the power transistor 10 is switched from the on state to the off state, the output voltage OUT becomes a negative voltage (OUT < GND) due to the back electromotive force of the load. Therefore, the active clamp circuit 32 is provided to absorb energy. The active clamp circuit 32 restricts the drain-source voltage of the power transistor 10 ( = output voltage OUT) to below the active clamp voltage Vclp by not fully turning off the power transistor 10 during the turn-off transition of the power transistor 10.

[0043] The gate resistor 33 is connected between the output terminal of the slew rate control circuit 31 and the gate of the power transistor 10 ( = the application terminal of the gate drive signal G1).

[0044] The transistor 34 is connected in parallel with the gate resistor 33. The transistor 34 can also be turned on / off controlled according to the slew rate adjustment signal SR, for example.

[0045] The logic unit 40 operates by receiving the supply of the power supply voltage VDD from the external terminal T1 via the path of the current limiting resistor 92. The logic unit 40 comprehensively controls the gate control system 30, the reference system 60, and the protection system 70 according to the external control signal IN and the external start signal EN.

[0046] For example, when the external start signal EN is at a high level ( = the logic level at startup) and the external control signal IN is at a high level ( = the logic level for turning on the power transistor 10), the logic unit 40 sets the gate control signal S1 to a high level. On the other hand, when the external start signal EN is at a low level ( = the logic level for disabling) or the external control signal IN is at a low level ( = the logic level for turning off the power transistor 10), the logic unit 40 sets the gate control signal S1 to a low level.

[0047] In addition, the logic device 40 monitors various signals outputted from the gate control system 30 , the input system 50 , the reference system 60 , and the protection system 70 .

[0048] The input system 50 operates by receiving the supply of the power supply voltage VDD from the external terminal T1 via the current limiting resistor 92. For example, the input system 50 includes an input control circuit 51, a startup control circuit 52, and a UVLO (under voltage lock out) circuit 53.

[0049] The input control circuit 51 receives an external input of an external control signal IN from the external terminal T3 and transmits the external control signal IN to the logic device 40. The input control circuit 51 may be, for example, a Schmitt trigger.

[0050] The start-up control circuit 52 receives an external input of an external start-up signal EN from the external terminal T4 and transmits the signal to the logic unit 40. The start-up control circuit 52 may be, for example, a Schmitt trigger.

[0051] The UVLO circuit 53 detects whether a low voltage abnormality occurs in the power supply voltage VDD, and outputs the detection result to the logic 40 and the reference system 60 (especially the reference generation circuit 61 described below). The UVLO circuit 53 can also be controlled by the startup control circuit 52 to be able to operate.

[0052] The reference system 60 operates by receiving the supply of the power supply voltage VDD from the external terminal T1 via the current limiting resistor 92. For example, the reference system 60 includes a reference generation circuit 61 and a negative current detection circuit 62.

[0053] The reference generation circuit 61 generates a specified reference voltage VREF and a reference current IREF according to the power supply voltage VDD. The reference voltage VREF and the reference current IREF may be supplied to the gate control system 30, for example.

[0054] The negative current detection circuit 62 monitors the output voltage OUT and detects whether the output current Io flows in the negative direction (=direction from the source to the drain of the power transistor 10). The configuration and operation of the negative current detection circuit 62 will be described in detail later.

[0055] The protection system 70 operates by receiving the supply of the power supply voltage VDD from the external terminal T1 via the current limiting resistor 92. For example, the protection system 70 includes an overcurrent protection circuit 71, a temperature protection circuit 72, and a load open detection circuit 73.

[0056] The overcurrent protection circuit 71 monitors the sense current Is, detects whether an overcurrent abnormality of the output current Io occurs, and outputs the detection result to the logic 40. In addition, the overcurrent protection circuit 71 may also have the function of reducing the gate drive signal G1 to limit the output current Io when an overcurrent is detected.

[0057] The temperature protection circuit 72 detects whether abnormal heating of the semiconductor device 1 occurs, and outputs the detection result to the logic unit 40 and the state output unit 80. In addition, the temperature protection circuit 72 may also have a function of forcibly turning off the power transistor 10 by setting the gate drive signal G1 to a low level when abnormal heating is detected. In addition, the temperature protection circuit 72 may monitor the element temperature of the power transistor 10, and may also monitor the temperature difference between the power transistor 10 and other circuit blocks (such as the logic unit 40).

[0058] The load open detection circuit 73 detects whether the load of the external terminal T4 is open, and outputs the detection result to the logic device 40 and the state output unit 80 .

[0059] The state output unit 80 operates by receiving the supply voltage VDD from the external terminal T1 via the current limiting resistor 92. The state output unit 80 generates a state signal ST based on the detection results of the temperature protection circuit 72 and the load open detection circuit 73, and outputs it externally from the external terminal T6.

[0060] In addition to the ground voltage GND, a reference voltage GND_REF (the details will be described later) is applied to each of the functional blocks.

[0061] <Electronic equipment>

[0062] Figure 2 to Figure 4 Each of the diagrams shows an example of a configuration of an electronic device to which the semiconductor device 1 can be applied. The electronic device 100 of this example of configuration includes a voltage source E, transistors M1 to M4 (eg, NMOSFET), and a load Z.

[0063] The voltage source E may also be, for example, a vehicle battery that outputs a battery voltage VBAT.

[0064] The drains of transistors M1 and M3 are connected to the positive terminal of voltage source E (= the end for applying battery voltage VBAT). The source of transistor M1 and the drain of transistor M2 are connected to the first end of load Z. The source of transistor M3 and the drain of transistor M4 are connected to the second end of load Z. The sources of transistors M2 and M4 are connected to the negative terminal of voltage source E (= the end for applying ground voltage GND).

[0065] In this way, transistors M1 to M4 form a full-bridge switching output stage for driving load Z.

[0066] That is, transistors M1 and M2 form a half-bridge switching output stage (first phase) for driving the first end of load Z. Furthermore, transistors M3 and M4 form a half-bridge switching output stage (second phase) for driving the second end of load Z.

[0067] The semiconductor device 1 described above can be used as, for example, a lower switching element of a switching output stage, that is, a transistor M2 or M4 (or a driving mechanism thereof). In other words, it can be understood that the power transistor 10 described above is equivalent to the transistor M2 or M4.

[0068] The load Z may also be an inductive load (for example, a coil forming a motor on a vehicle).

[0069] In addition, Figure 2 to Figure 4 , the first to third stages of the electronic device 100 are depicted respectively. The operation states of each figure will be described in detail below.

[0070] Phase 1 Figure 2 ) is equivalent to the load Z, that is, the state of the motor rotation. According to this figure, in the first stage ( Figure 2 ), transistors M1 and M4 are both in the on state, and transistors M2 and M3 are both in the off state. Therefore, the output current Io flows from the application end of the battery voltage VBAT through the transistor M1, the load Z and the transistor M4 toward the application end of the ground voltage GND. At this time, there is no path for the output current Io to flow in the negative direction through the transistor M2. Therefore, the power consumption CP1 of the transistor M2 is 0.

[0071] Phase 2 Figure 3 ) corresponds to the dead time from the motor rotation state to the regeneration state. Such a dead time is set to prevent excessive through-current through transistors M1 and M2. Figure 2 )Switch to Phase 2 ( Figure 3 ), the transistor M1 switches from the on state to the off state. At this time, the inductive load Z will continue to flow the output current Io in the same direction as before. However, both transistors M1 and M2 are in the off state. Therefore, the output current Io flows in the negative direction from the application end of the ground voltage GND through the body diode BD attached to the transistor M2 toward the load Z. As a result, the power consumption CP2 of the transistor M2 becomes relatively large (CP2 = Io × Vf, where Vf is set to the forward drop voltage of the body diode BD).

[0072] Phase 3 Figure 4 ) is equivalent to the regeneration state. According to this figure, by Figure 3 )Switch to Phase 3 ( Figure 4), the transistor M2 switches from the off state to the on state. At this time, the inductive load Z will be in the second stage ( Figure 3 ) continues to flow the output current Io in the same direction. In addition, in the third stage ( Figure 4 ), the transistor M2 is in the on state. Therefore, the output current Io flows in the negative direction from the application end of the ground voltage GND through the transistor M2 toward the load Z. As a result, the power consumption CP3 of the transistor M2 becomes relatively small (CP3 = Io × Io × Ron, where Ron is set as the on resistance of the transistor M2).

[0073] However, in the case where the semiconductor device 1 is used as the transistor M2 or M4 , malfunction of a parasitic element may become a problem.

[0074] For example, in the previous Phase 2 ( Figure 3 ), consider the case where the transistor M2 is a VDMOSFET [vertical doublediffused MOSFET] in which the N-type semiconductor substrate is used as the drain. In this case, since the drain voltage of the transistor M2 becomes a negative voltage (-Vf), the parasitic element (parasitic npn bipolar transistor or parasitic pn junction diode) attached to the semiconductor device 1 may malfunction.

[0075] In addition, due to malfunction of parasitic elements, the power supply voltage VDD may drop or latch-up may occur. Figure 3 ) to Stage 3 ( Figure 4 ), if transistor M2 is not correctly switched to the on state, the resulting power consumption (heat generation) increases.

[0076] In view of the above considerations, a negative current detection circuit 62 capable of preventing malfunction of a parasitic element included in the semiconductor device 1 is proposed below.

[0077] <Negative Current Detection Circuit (First Embodiment)>

[0078] Figure 5 1 is a diagram showing a first embodiment of a negative current detection circuit 62. The negative current detection circuit 62 of this embodiment includes a comparator CMP, transistors N1 to N4 (eg, NMOSFETs), transistors P1 and P2 (eg, PMOSFETs), and resistors R1 to R4 (eg, semiconductor diffusion resistors).

[0079] The source and back gate of transistor P1 are both connected to the application end of power supply voltage VDD. The gate of transistor P1 is connected to the application end of inverted external start signal ENB (=logic inversion signal of external start signal EN). The drain of transistor P1 is connected to the first end of resistor R1. The second end of resistor R1 is connected to the first end of resistor R2. The second end of resistor R2 and the first end of resistor R3 are both connected to the non-inverting input end (+) of comparator CMP (=application end of output detection voltage Vs). The second end of resistor R3 and the inverting input end (-) of comparator CMP are both connected to the application end of ground voltage GND.

[0080] The drain of transistor N1 is connected to the application end of output voltage OUT (=N-type semiconductor substrate N-SUB). The gate of transistor N1 is connected to the drain of transistor P1 (=application end of node voltage VA). The source and back gate of transistor N1 are both connected to the non-inverting input end (+) of comparator CMP.

[0081] The source and back gate of transistor P2 are connected to the application end of power supply voltage VDD. The drain of transistor P2 is connected to the drain of transistor N2. The source and back gate of transistor N2 and the drain and back gate of transistor N3 are connected to the application end of reference voltage GND_REF (=P-type well P / W). The gates of transistors P2, N2 and N3 are connected to the output end of comparator CMP (=application end of negative current detection signal DET). The source of transistor N3 is connected to the application end of ground voltage GND.

[0082] The drain of transistor N4 is connected to the application end of output voltage OUT (=N-type semiconductor substrate N-SUB). The gate of transistor N4 is connected to the drain of transistors P2 and N2 respectively (=application end of node voltage VB). The source and back gate of transistor N4 and the first end of resistor R4 are all connected to the application end of reference voltage GND_REF (=P-type well P / W). The second end of resistor R4 is connected to the application end of ground voltage GND.

[0083] Furthermore, transistors P1 and P2 and resistors R1 to R4 are respectively formed in P-type well P / W (= application end of reference voltage GND_REF) of semiconductor device 1. That is, reference voltage GND_REF is applied to P-type well P / W and back gates of NMOSFETs of all circuit blocks.

[0084] The comparator CMP operates by receiving the supply of the power supply voltage VDD. The comparator CMP compares the output detection voltage Vs input to the non-inverting input terminal (+) with the ground voltage GND applied to the inverting input terminal (-), and generates a negative current detection signal DET. Therefore, the negative current detection signal DET becomes a high level when the output detection voltage Vs is higher than the ground voltage GND, and becomes a low level when the output detection voltage Vs is lower than the ground voltage GND.

[0085] In addition, a specified threshold voltage VTH may be applied to the inverting input terminal (-) of the comparator CMP instead of the ground voltage GND. In addition, the comparator CMP may also control whether the above-mentioned action can be performed according to the external start signal EN (and the inverted external start signal ENB). In addition, a reference voltage VREF may be applied to the comparator CMP.

[0086] Among the above-described components, the transistor N3 functions as a first transistor that switches on and off between an application end of the reference voltage GND_REF (=P-type well P / W) and an application end of the ground voltage GND in accordance with the negative current detection signal DET.

[0087] The transistor N4 functions as a second transistor that switches on and off between the application end (=P-type well P / W) of the reference voltage GND_REF and the application end of the output voltage OUT according to the negative current detection signal DET.

[0088] The transistors P2 and N2 function as an inverter that drives the transistor N4 according to the negative current detection signal DET.

[0089] The transistors P1 and P2 and the resistors R1 to R3 function as a bias unit that switches whether to apply the output voltage OUT or a specified bias voltage (=divided voltage of the power supply voltage VDD) to the non-inverting input terminal (+) of the comparator.

[0090] The negative current detection circuit 62 of this embodiment detects the output voltage OUT appearing at the external terminal T4 (=output terminal), and switches whether to apply the ground voltage GND or the output voltage OUT to the application end (=P-type well P / W) of the reference voltage GND_REF.

[0091] More specifically, when the output voltage OUT is detected to be lower than the ground voltage GND, the negative current detection circuit 62 applies the output voltage OUT to the application end (=P-type well P / W) of the reference voltage GND_REF. On the other hand, when the output voltage OUT is detected to be higher than the ground voltage GND, the negative current detection circuit 62 applies the ground voltage GND to the application end (=P-type well P / W) of the reference voltage GND_REF.

[0092] For example, when the output current Io flows in the negative direction and the output voltage OUT becomes a negative voltage (-Vf), the output voltage OUT is applied to the application end of the reference voltage GND_REF. That is, the N-type semiconductor substrate N-SUB and the P-type well P / W become the same voltage. Therefore, the malfunction of the parasitic element attached to the semiconductor device 1 is prevented. As a result, the reduction of the power supply voltage VDD and latch-up can be suppressed. In particular, since it is difficult to Figure 3 ) to Stage 3 ( Figure 4 ) is not obstructed in the conversion, so the power consumption (heat generation) is suppressed to a small extent.

[0093] Hereinafter, a plurality of operating states of the negative current detection circuit 62 are listed and described in detail.

[0094] Figure 6 : is a diagram showing the first operating state (on sequence & positive current) of the negative current detection circuit 62. In the first operating state, the power transistor 10 is in the on state, and the output current Io flows in the positive direction (= from the drain to the source of the power transistor 10). At this time, the output voltage OUT becomes a positive voltage (= Io×Ron) determined by the output current Io and the on resistance Ron of the power transistor 10. In addition, the first operating state of this figure corresponds to the first to third stages ( Figure 2 to Figure 4 ) of transistor M4.

[0095] When the external start signal EN is at a high level, that is, when the inverted external start signal ENB is at a low level, the transistor P1 is turned on. Therefore, the node voltage VA becomes a high level (≒VDD), so the transistor N1 is turned on. As a result, the output voltage OUT is applied to the non-inverting input terminal (+) of the comparator CMP as the output detection voltage Vs.

[0096] As described above, in the first operation state, since the output voltage OUT becomes a positive voltage higher than the ground voltage GND (=Io×Ron), the negative current detection signal DET becomes a high level. At this time, the transistor P2 becomes an off state, and the transistors N2 and N3 become an on state. Therefore, since the node voltage VB becomes a low level (≒GND), the transistor N4 becomes an off state. As a result, the reference voltage GND_REF becomes the same voltage as the ground voltage GND.

[0097] In addition, the output detection voltage Vs in the first operation state is in the order of several tens to several hundreds of mV. Therefore, it is desirable that the comparator CMP has a low offset.

[0098] Furthermore, even if the output voltage OUT is a value close to the ground voltage GND, the resistance value of each of the resistors R1 to R3 can be appropriately set so that the output detection voltage Vs is surely higher than the ground voltage GND.

[0099] Figure 7 : is a diagram showing the second operating state (on sequence & negative current) of the negative current detection circuit 62. In the second operating state, the power transistor 10 is in the on state, and the output current Io flows in the negative direction (= from the source to the drain of the power transistor 10). At this time, the output voltage OUT becomes a negative voltage (= -Io×Ron) determined by the output current Io and the on resistance Ron of the power transistor 10. In addition, the second operating state of this figure is equivalent to the third stage ( Figure 4 ) of transistor M2.

[0100] In the second operation state, since the output voltage OUT becomes a negative voltage lower than the ground voltage GND (=-Io×Ron), the negative current detection signal DET becomes a low level. At this time, the transistor P2 becomes an on state, and the transistors N2 and N3 become an off state. Therefore, the node voltage VB becomes a high level (≒VDD), so the transistor N4 becomes an on state. As a result, the reference voltage GND_REF becomes the same voltage as the output voltage OUT.

[0101] In addition, the output detection voltage Vs in the second operation state is in the order of -10s to -100s of mV. Therefore, it is desirable that the comparator CMP has a low offset.

[0102] Figure 8 3 is a diagram showing the third operating state (off sequence) of the negative current detection circuit 62. In the third operating state, the power transistor 10 is in the off state, and the output current Io does not flow in either the positive or negative direction. At this time, the output voltage OUT rises to near the battery voltage VBAT via the upper switch (e.g., transistor M1 or M3) forming the half-bridge type switch output stage. In addition, the third operating state of this figure corresponds to the first stage ( Figure 2 ) of transistor M2.

[0103] In the third operation state, since the output detection voltage Vs is clamped to a positive voltage (≒VDD-Vgs) that is lower than the node voltage VA by the gate-source voltage Vgs of the transistor N1, the negative current detection signal DET becomes a high level. At this time, the transistor P2 becomes an off state, and the transistors N2 and N3 become an on state. Therefore, since the node voltage VB becomes a low level (≒GND), the transistor N4 becomes an off state. As a result, the reference voltage GND_REF becomes the same voltage as the ground voltage GND.

[0104] Fig. 9 : is a diagram showing the fourth operating state (off sequence & negative current) of the negative current detection circuit 62. In the fourth operating state, the power transistor 10 is in the off state, and the output current Io flows in the negative direction (= from the anode to the cathode of the body diode BD attached to the power transistor 10). At this time, the output voltage OUT becomes a negative voltage (= -Vf) determined by the forward drop voltage Vf of the body diode BD. In addition, the fourth operating state of this figure is equivalent to the second stage ( Figure 3 ) of transistor M2.

[0105] In the fourth operation state, since the output voltage OUT becomes a negative voltage (=-Vf) lower than the ground voltage GND, the negative current detection signal DET becomes a low level. At this time, the transistor P2 becomes an on state, and the transistors N2 and N3 become an off state. Therefore, the node voltage VB becomes a high level (≒VDD), so the transistor N4 becomes an on state. As a result, the reference voltage GND_REF becomes the same voltage as the output voltage OUT.

[0106] <Behavior when negative current is generated>

[0107] Fig.10 This is a diagram showing the behavior when a negative current is generated (especially the behavior when the negative current detection circuit 62 is not provided). In this figure, the behavior of the external enable signal EN, the inverted external enable signal ENB, the output voltage OUT and the reference voltage GND_REF are depicted in order from top to bottom.

[0108] As shown in this figure, assuming that the negative current detection circuit 62 is not provided, even if the output voltage OUT becomes a negative voltage (-Vf), the reference voltage GND_REF is maintained at the ground voltage GND. Therefore, as described above, parasitic elements included in the semiconductor device 1 may malfunction.

[0109] Fig.11 This is a diagram showing a longitudinal section of the semiconductor device 1 (a diagram for explaining the behavior when the negative current detection circuit 62 is not provided). The semiconductor device 1 includes an N-type semiconductor substrate 201. An N-type epitaxial layer 202 is formed by stacking on the N-type semiconductor substrate 201. Various circuit elements are formed on the N-type epitaxial layer 202. According to this figure, a power transistor 10 (e.g., VDMOSFET) and a transistor Nx (e.g., NMOSFET) are formed on the N-type epitaxial layer 202.

[0110] First, the device structure of the power transistor 10 is described. In the formation region of the power transistor 10, a plurality of trench gates 203 are formed at predetermined intervals in an N-type epitaxial layer 202. In addition, an N-type drift region 204 is buried in the N-type epitaxial layer 202 so as to surround the plurality of trench gates 203, respectively.

[0111] An N-type body region 205 is formed on the upper layer of the N-type drift region 204. A high-concentration P-type region 206 and a high-concentration N-type region 207 are formed in the N-type body region 205. The formation region of the power transistor 10 is surrounded by an element isolation region 208.

[0112] The high concentration P-type region 206, the high concentration N-type region 207 and the element isolation region 208 are respectively connected to the metal wiring 210 via the via hole 209. The metal wiring 210 is connected to the application end of the ground voltage GND as the source (or back gate) of the power transistor 10. On the other hand, the N-type semiconductor substrate 201 is connected to the application end of the output voltage OUT as the drain of the power transistor 10.

[0113] Next, the device structure of the transistor Nx is described with attention. In the formation region of the transistor Nx, a high-voltage P-type well 211 is buried in the N-type epitaxial layer 202. In the upper layer of the high-voltage P-type well 211, a low-voltage P-type well 212 is formed in a range that is wider than the high-voltage P-type well 211 in the lateral direction and reaches the surface of the N-type epitaxial layer 202.

[0114] In the low-voltage P-type well 212, high-concentration N-type regions 213a and 213b (equivalent to the drain region and the source region) are formed with a predetermined channel length. In addition, in the low-voltage P-type well 212, a high-concentration P-type region 214 (equivalent to the back gate contact) is formed along the outer edge.

[0115] A gate insulating layer 215 is formed in an upper layer of the channel region sandwiching the high-concentration N-type regions 213a and 213b. In addition, a formation region of the transistor Nx is surrounded by an element isolation region 216.

[0116] The high concentration P-type region 214 and the element isolation region 216 are respectively connected to the metal wiring 218 via the via 217. The metal wiring 218 is connected to the application end of the ground voltage GND via the resistor R4 as the back gate (=application end of the reference voltage GND_REF) of the transistor Nx.

[0117] The high-concentration N-type region 213a is electrically connected to the metal wiring 219 via the via hole 217. The metal wiring 219 corresponds to the drain of the transistor Nx. The gate insulating layer 215 is electrically connected to the metal wiring 220 via the via hole 217. The metal wiring 220 corresponds to the gate of the transistor Nx. The high-concentration N-type region 213b is electrically connected to the metal wiring 221 via the via hole 217. The metal wiring 221 corresponds to the source of the transistor Nx and is connected to the application terminal of the ground voltage GND.

[0118] In addition, the surface layer of the N-type epitaxial layer 202, except for the formation region of the via hole 217, is covered with the protective layer 222.

[0119] However, in the power transistor 10 having the above-described element structure, a body diode BD is attached, with the high-concentration P-type region 206 as the anode and the N-type semiconductor substrate 201 and the N-type epitaxial layer 202 as the cathode. In addition, a parasitic transistor Q1 (= npn bipolar transistor) is attached to the transistor Nx, with the high-concentration N-type region 213a as the collector, the N-type semiconductor substrate 201 and the N-type epitaxial layer 202 as the emitter, and the high-concentration P-type region 214, the low-voltage withstand P-type well 212, and the high-voltage withstand P-type well 211 as the base.

[0120] Here, consider the case where the body diode BD of the power transistor 10 becomes in a forward-biased state and an output current Io flows in the negative direction (from the application terminal of the ground voltage GND toward the N-type semiconductor substrate 201) via the body diode BD. In this case, the output voltage OUT applied to the emitter of the parasitic transistor Q1 becomes a negative voltage (-Vf < GND). On the other hand, the reference voltage GND_REF applied to the base of the parasitic transistor Q1 is maintained at the ground voltage GND. As a result, there is a concern that the parasitic transistor Q1 may turn on.

[0121] Fig.12 It is a diagram showing the behavior when a negative current is generated (the behavior in the case where the negative current detection circuit 62 is provided). In this figure, similar to the above Fig.10 The behaviors of the external start signal EN, the inverted external start signal ENB, the output voltage OUT, and the reference voltage GND_REF are depicted in order from top to bottom.

[0122] As shown in this figure, in the case where the negative current detection circuit 62 is provided, when the output voltage OUT becomes a negative voltage (-Vf), the reference voltage GND_REF becomes the same voltage as the output voltage OUT. Therefore, the parasitic elements attached to the semiconductor device 1 are less likely to malfunction.

[0123] Fig.131 is a diagram showing a longitudinal section of the semiconductor device 1 (a diagram for explaining the behavior when the negative current detection circuit 62 is provided). Fig.11 Based on , the transistor N4 provided between the application end of the output voltage OUT and the application end of the reference voltage GND_REF is clearly shown.

[0124] When the output current Io flows in the negative direction and the output voltage OUT becomes a negative voltage (-Vf), the transistor N4 becomes turned on by the operation of the negative current detection circuit 62. As a result, the reference voltage GND_REF becomes the same voltage as the output voltage OUT. Therefore, the base-emitter voltage of the parasitic transistor Q1 (=GND_REF-OUT) becomes 0. As a result, the erroneous turning on of the parasitic transistor Q1 can be prevented.

[0125] <Consideration on Output Leakage Current Characteristics of Negative Current Detection Circuit (First Embodiment)>

[0126] However, it is desirable that the negative current detection circuit 62 suppresses the output leakage current Io_leak (Io_leak ≒ 0 μA) when the output voltage OUT is above 0 V. In addition, the output leakage current Io_leak can be defined as the current flowing through the external terminal T4 when the output of the semiconductor device 1 is turned off, that is, when the power transistor 10 is in the off state (standby state).

[0127] However, in the negative current detection circuit 62 of the first embodiment, there is room for improvement in the output leakage current characteristics.

[0128] Fig.14 1 is a diagram showing the behavior (first leakage condition) when the output is turned off in the negative current detection circuit 62 of the first embodiment. In addition, as the first leakage condition, it is conceivable that the battery voltage VBAT (≒output voltage OUT) is higher than the differential voltage VDD-Vth obtained by subtracting the on-threshold voltage Vth of the transistor N1 from the power supply voltage VDD (VBAT≒OUT>VDD-Vth).

[0129] When the first leakage condition is satisfied, as indicated by the arrow in the figure, a positive output leakage current Io_leak may flow from the application end of the output voltage OUT to the ground end via the transistor N1 and the resistor R3 .

[0130] At this time, if the transistor N1 is in the off state, the output leakage current Io_leak does not flow. The transistor N1 is in the off state when the gate-source voltage Vgs is lower than the on-threshold voltage Vth.

[0131] Here, when the first leakage condition is satisfied, among the two main electrodes of the transistor N1, the main electrode connected to the application terminal of the output detection voltage Vs functions as the source electrode. That is to say, the gate-source voltage Vgs of the transistor N1 is expressed by the following formula (1).

[0132] Vgs = VA - Vs…(1)

[0133] In addition, VA ≒ VDD. Moreover, Vs = VA × R3 / (R1 + R2 + R3). Therefore, the formula (1) is rewritten as the following formula (2).

[0134] Vgs ≒ VDD × (R1 + R2) / (R1 + R2 + R3)…(2)

[0135] It can be seen from the formula (2) that in order to set the transistor N1 to the off state (Vgs < Vth), it is necessary to satisfy (R1 + R2) << R3. Therefore, in order to suppress the positive output leakage current Io_leak (set Io_leak ≒ 0 μA), it is necessary to set R1 + R2 to a value relatively smaller than R3. That is to say, the smaller R1 + R2 is, the better the positive output leakage current characteristic is.

[0136] Fig.15 It is a diagram showing the relationship between the output voltage OUT and the output leakage current Io_leak in the first embodiment (the first leakage condition: VBAT ≒ OUT > VDD - Vth).

[0137] When R1 + R2 is small, since the gate-source voltage Vgs of the transistor N1 decreases, the transistor N1 is easily turned off (the on-resistance value becomes high). Therefore, as shown by the solid line in this figure, the positive output leakage current Io_leak (Io_leak ≒ 0 μA) is suppressed. In this way, when R1 + R2 is small, the positive output leakage current characteristic is good.

[0138] On the other hand, when R1 + R2 is large, since the gate-source voltage Vgs of the transistor N1 increases, the transistor N1 is not easily turned off (the on-resistance value becomes low). Therefore, as shown by the dotted line in this figure, the positive output leakage current Io_leak may increase according to the output voltage OUT. In this way, when R1 + R2 is large, the positive output leakage current characteristic deteriorates.

[0139] Fig.16This is a diagram showing the behavior (second leakage condition) when the output is disconnected in the negative current detection circuit 62 of the first embodiment. Additionally, as the second leakage condition, a situation where the battery voltage VBAT (≈ output voltage OUT) is lower than the differential voltage VDD - Vth obtained by subtracting the on-threshold voltage Vth of the transistor N1 from the power supply voltage VDD (VBAT ≈ OUT < VDD - Vth) can be envisioned.

[0140] When the second leakage condition is satisfied, among the two main electrodes of the transistor N1, the main electrode connected to the application terminal of the output voltage OUT functions as the source. That is, the gate-source voltage Vgs of the transistor N1 is expressed by the following equation (3).

[0141] Vgs = VA - OUT…(3)

[0142] Furthermore, VA ≈ VDD. Therefore, when the second leakage condition is satisfied, the transistor N1 may enter the on state (Vgs > Vth). Thus, as shown by the arrow in the figure, an output leakage current Io_leak in the negative direction may flow from the application terminal of the power supply voltage VDD, through the transistor P1, resistors R1 and R2, and the transistor N1, towards the application terminal of the output voltage OUT.

[0143] Here, the output leakage current Io_leak in the negative direction is expressed by the following equation (4).

[0144] Io_leak ≈ (VDD - Vs) / (R1 + R2)…(4)

[0145] Moreover, since the transistor N1 is in the on state, Vs ≈ OUT. Therefore, the above equation (4) is rewritten as the following equation (5).

[0146] Io_leak ≈ (VDD - OUT) / (R1 + R2)…(5)

[0147] From the above equation (5), it can be seen that the larger R1 + R2 is, the more the output leakage current Io_leak in the negative direction is suppressed (Io_leak ≈ 0 μA). That is, the larger R1 + R2 is, the better the output leakage current characteristics.

[0148] Fig.17 This is a diagram showing the relationship between the output voltage OUT and the output leakage current Io_leak in the first embodiment (second leakage condition: VBAT ≈ OUT < VDD - Vth).

[0149] When R1 + R2 is large, as shown by the solid line in this figure, the output leakage current Io_leak in the negative direction is suppressed (Io_leak ≈ 0 μA). Thus, when R1 + R2 is large, the output leakage current characteristics in the negative direction are good.

[0150] On the other hand, when R1+R2 is small, as shown by the dotted line in this figure, the negative output leakage current Io_leak may increase (depart from 0 μA) according to the output voltage OUT. In other words, when R1+R2 is small, the negative output leakage current characteristic deteriorates.

[0151] Fig.18 This figure is a diagram showing the output leakage current characteristics of the negative current detection circuit 62 of the first embodiment. Fig.15 and Fig.17 .

[0152] When R1+R2 is small, as shown by the solid line in this figure, the output leakage current characteristics in the positive direction are good, while the output leakage current characteristics in the negative direction are deteriorated. On the other hand, when R1+R2 is large, as shown by the dotted line in this figure, the output leakage current characteristics in the negative direction are good, while the output leakage current characteristics in the positive direction are deteriorated. That is, a trade-off relationship is established between the output leakage current characteristics in the positive direction and the output leakage current characteristics in the negative direction.

[0153] Thus, in the negative current detection circuit 62 of the first embodiment, no matter what value R1+R2 is set to, the output leakage current characteristic is changed with OUT=VDD-Vth as the boundary. Therefore, when the output voltage OUT is above 0V, it is difficult to achieve the goal of suppressing the output leakage current Io_leak (setting Io_leak ≒ 0μA).

[0154] In view of the above considerations, a second embodiment is proposed below, which can achieve good output leakage current characteristics in both positive and negative bidirectional directions.

[0155] <Negative Current Detection Circuit (Second Embodiment)>

[0156] Fig.19 1 is a diagram showing a second embodiment of the negative current detection circuit 62. The negative current detection circuit 62 of this embodiment is different from the first embodiment ( Figure 5 ) is used as the basis, and its circuit structure is changed. In the following description, the components that have appeared are marked with Figure 5 The same reference numerals may be used to indicate the same components, and duplicate descriptions of the components that have already appeared may be omitted.

[0157] The negative current detection circuit 62 of this embodiment includes a detection signal generation circuit 62a, a reference voltage control circuit 62b, a transistor N4 (eg, NMOSFET), and a resistor R4. The transistor N4 may also be a VDMOSFET.

[0158] The detection signal generation circuit 62a detects a situation where the output voltage OUT appearing at the external terminal T4 is lower than the ground voltage GND (or a specified threshold voltage) applied to the external terminal T7, and generates a negative current detection signal DET. Describing according to this figure, the detection signal generation circuit 62a includes a bias circuit BIAS and a clamping circuit CLP in addition to the comparator CMP that has appeared.

[0159] As also described before, the comparator CMP compares the output detection voltage Vs input to the non-inverting input terminal (+) with the ground voltage GND (or a specified threshold voltage VTH) input to the inverting input terminal (-), and generates a negative current detection signal DET. Describing according to this figure, the negative current detection signal DET becomes high level when Vs > GND, and becomes low level when Vs < GND. In addition, the comparator CMP can also be a hysteresis comparator.

[0160] The bias circuit BIAS switches whether to apply the output voltage OUT or a bias voltage (≒VA - Vth ≒ VDD - Vth) as the output detection voltage Vs. Describing according to this figure, the bias circuit BIAS includes a transistor N5 (e.g., NMOSFET), and resistors R5 and R6. The transistor N5 can also be a VDMOSFET.

[0161] The drain of the transistor N5 is connected to the external terminal T4 (= output terminal). The source of the transistor N5 is connected to the first end of the resistor R5. The second end of the resistor R5 is connected to the application end of the output detection voltage Vs. The first end of the resistor R6 is connected to the external terminal T1 (= the application end of the power supply voltage VDD). The second end of the resistor R6 is connected to the gate of the transistor N5.

[0162] The resistor R5 is equivalent to the first resistor connected between the source of the transistor N5 and the application end of the output detection voltage Vs. The resistor R6 is equivalent to the second resistor connected between the gate of the transistor N5 and the external terminal T1 (= the application end of the power supply voltage VDD). The resistors R5 and R6 respectively function as ESD [electro - static discharge] protection elements for protecting the non-inverting input terminal (+) of the comparator CMP and the gate of the transistor N5.

[0163] The clamping circuit CLP operates when the absolute value of the output detection voltage Vs is higher than the clamping operation voltage VCLP. Therefore, the upper limit value in the positive direction of the output detection voltage Vs is limited to +VCLP, and the upper limit value in the negative direction is limited to -VCLP. That is to say, the clamping operation voltage VCLP can be understood as the upper limit values of the positive and negative of the output detection voltage Vs. Describing according to this figure, the clamping circuit CLP includes diodes D1 and D2.

[0164] The cathode of the diode D1 is connected to the application terminal of the output detection voltage Vs. The anode of the diode D1 is connected to the anode of the diode D2. The cathode of the diode D2 is connected to the external terminal T7 (=ground terminal). A plurality of diodes D1 and D2 may be provided in a vertical column.

[0165] The diode D1 corresponds to at least one first diode connected with a first polarity between the application end of the output detection voltage Vs and the external terminal T7 (=ground terminal). The diode D2 corresponds to at least one second diode connected with a second polarity opposite to the first polarity between the application end of the output detection voltage Vs and the external terminal T7 (=ground terminal).

[0166] It is desirable that the clamping operation voltage VCLP is higher than a differential voltage VA-Vth (≒VDD-Vth) obtained by subtracting the on-threshold voltage Vth of the transistor N5 from the node voltage VA applied to the gate of the transistor N5 (details will be described later).

[0167] The reference voltage control circuit 62b switches the node voltage VB applied to the gate of the transistor N4 to a high level or a low level according to the negative current detection signal DET. In this way, the reference voltage control circuit 62b switches whether to apply the ground voltage GND or the output voltage OUT to the application end (=P-type well P / W) of the reference voltage GND_REF. In addition, although not explicitly shown in this figure, the reference voltage control circuit 62b may also include, for example, the above-mentioned transistors P2, N2 and N3 ( Figure 5 ).

[0168] The negative current detection circuit 62 of this embodiment is different from the first embodiment ( Figure 5 ), when the output voltage OUT is detected to be lower than the ground voltage GND, the output voltage OUT is applied to the application end (=P-type well P / W) of the reference voltage GND_REF. On the other hand, when the output voltage OUT is detected to be higher than the ground voltage GND, the negative current detection circuit 62 applies the ground voltage GND to the application end (=P-type well P / W) of the reference voltage GND_REF.

[0169] For example, when the output current Io flows in the negative direction and the output voltage OUT becomes a negative voltage (=-Io×Ron or -Vf), the output detection voltage Vs (≒OUT) is lower than the ground voltage GND. Therefore, the negative current detection signal DET becomes a low level. At this time, the reference voltage control circuit 62b turns on the transistor N4. As a result, the output voltage OUT is applied to the application end of the reference voltage GND_REF.

[0170] That is, the N-type semiconductor substrate N-SUB and the P-type well P / W become the same voltage. Therefore, the malfunction of the parasitic element attached to the semiconductor device 1 is prevented. As a result, the reduction of the power supply voltage VDD and latch-up can be suppressed. In particular, since it is difficult to Figure 3 ) to Stage 3 ( Figure 4 ) is not obstructed in the conversion, so the power consumption (heat generation) is suppressed to a small extent.

[0171] In addition, when the output current Io flows in the positive direction and the output voltage OUT becomes a positive voltage (=Io×Ron), the output detection voltage Vs (≒OUT) is higher than the ground voltage GND. Therefore, the negative current detection signal DET becomes a high level. At this time, the reference voltage control circuit 62b sets the transistor N4 to the off state. As a result, the application end of the reference voltage GND_REF is pulled down to the external terminal T7 via the resistor R4. In other words, the reference voltage GND_REF becomes the same voltage as the ground voltage GND.

[0172] <Consideration on Output Leakage Current Characteristics of Negative Current Detection Circuit (Second Embodiment)>

[0173] Fig. 20 1 is a diagram showing the behavior of the negative current detection circuit 62 according to the second embodiment when the output is turned off (first leakage condition: VBAT≒OUT>VDD-Vth).

[0174] When the first leakage condition is met, as shown by the arrow in the figure, the output leakage current Io_leak may flow in the positive direction from the external terminal T4 (= the application end of the output voltage OUT) through the transistor N5, the resistor R5, the diodes D1 and D2 toward the external terminal T7 (= the application end of the ground voltage GND).

[0175] Here, when the first leakage condition is satisfied, the main electrode connected to the first end of the resistor R5 among the two main electrodes of the transistor N5 functions as a source. At this time, the upper limit value of the output detection voltage Vs reaches VA-Vth (≒VDD-Vth) by the operation of the bias circuit BIAS.

[0176] Therefore, when VCLP>VDD-Vth, the clamp circuit CLP does not operate. In other words, the clamp circuit CLP does not become a path for conducting the output leakage current Io_leak in the positive direction. Therefore, the output leakage current Io_leak in the positive direction is suppressed (Io_leak ≒ 0 μA). In other words, the output leakage current characteristic in the positive direction is good.

[0177] Fig.21This is a diagram showing the relationship between the output voltage OUT and the output leakage current Io_leak in the negative current detection circuit 62 of the second embodiment (first leakage condition: VBAT ≒ OUT > VDD - Vth).

[0178] When VCLP > VDD - Vth, as described previously, the clamping circuit CLP does not operate. Therefore, as shown by the solid line in this figure, the positive - direction output leakage current Io_leak (Io_leak ≒ 0 μA) is suppressed. In this way, when VCLP > VDD - Vth, the positive - direction output leakage current characteristic is good.

[0179] On the other hand, when VCLP < VDD - Vth, the clamping circuit CLP operates. In other words, the clamping circuit CLP becomes a path for conducting the positive - direction output leakage current Io_leak. Therefore, as shown by the dashed line in this figure, the positive - direction output leakage current Io_leak may increase according to the output voltage OUT. In this way, when VCLP < VDD - Vth, the positive - direction output leakage current characteristic deteriorates.

[0180] Fig. 22 This is a diagram showing the behavior when the output is disconnected in the negative current detection circuit 62 of the second embodiment (second leakage condition: VBAT ≒ OUT < VDD - Vth).

[0181] When the second leakage condition is satisfied, among the two main electrodes of the transistor N5, the main electrode connected to the external terminal T4 (= the application terminal of the output voltage OUT) functions as the source electrode. Therefore, the transistor N5 may be in the on - state (Vgs > Vth). As shown by the arrow in the figure, a negative - direction output leakage current Io_leak may flow from the external terminal T7 (= the application terminal of the ground voltage GND) through the diodes D2 and D1, the resistor R5, and the transistor N5 towards the external terminal T4 (= the application terminal of the output voltage OUT).

[0182] However, if the output detection voltage Vs (≒ OUT ≒ VBAT) does not drop to a negative voltage (-VCLP) that is only lower than the ground voltage GND by the clamping operation voltage VCLP, then the clamping circuit CLP does not operate. Here, the minimum value of the battery voltage VBAT is 0 V. Therefore, the clamping circuit CLP does not operate. In other words, the clamping circuit CLP does not become a path for conducting the negative - direction output leakage current Io_leak. Therefore, no negative - direction output leakage current Io_leak flows.

[0183] Fig.23 This is a diagram showing the relationship between the output voltage OUT and the output leakage current Io_leak in the negative current detection circuit 62 of the second embodiment (second leakage condition: VBAT ≒ OUT < VDD - Vth).

[0184] As described above, under the second leakage condition, even if the battery voltage VBAT is at the lowest value (0V), the clamp circuit CLP does not operate. Therefore, as shown by the solid line and the dotted line in this figure, the output leakage current Io_leak in the negative direction does not flow regardless of the relationship between the clamping action voltage VCLP and the differential voltage VDD-Vth. In other words, the output leakage current characteristic in the negative direction is always good.

[0185] Fig.24 This figure is a diagram showing the output leakage current characteristics of the negative current detection circuit 62 of the second embodiment. Fig.21 and Fig.23 As shown by the solid line in this figure, when VCLP>VDD-Vth, the output leakage current characteristics of both positive and negative directions are good.

[0186] Fig.25 1 is a diagram showing the improvement effect of the output leakage current characteristic. In this diagram, as the output leakage current characteristic of the second embodiment, Fig.24 The solid line (VCP>VDD-Vth) is directly drawn as a solid line. In addition, in this figure, as the output leakage current characteristics of the first embodiment, Fig.18 The solid line (R1+R2: small) is depicted as a dotted line.

[0187] It is clear from the comparison between the solid line and the dotted line that the negative current detection circuit 62 of this embodiment is different from the first embodiment ( Fig.18 ) is different, and the output leakage current characteristic does not change with OUT = VDD - Vth as the boundary. Therefore, as long as the clamping action voltage VCLP is appropriately set, the goal of suppressing the output leakage current Io_leak (setting Io_leak ≒ 0μA) when the output voltage OUT is above 0V can be achieved.

[0188] <Application to Vehicles>

[0189] Fig.26 The vehicle X of this configuration example is equipped with various electronic devices that operate by receiving power supplied from a battery.

[0190] Vehicle X includes, in addition to engine vehicles, electric vehicles (xEVs such as BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV [plug-in hybrid electric vehicle / plug-in hybrid vehicle], or FCEV / FCV [fuel cell electric vehicle / fuel cell vehicle]).

[0191] In addition, the semiconductor device 1 described above can be incorporated into any electronic equipment mounted in the vehicle X.

[0192] <Note>

[0193] The disclosure is supplemented below. According to the disclosure, malfunction of a parasitic element can be prevented.

[0194] (Note 1)

[0195] A semiconductor device (1) comprises: a semiconductor substrate (N-SUB) of a first conductivity type;

[0196] a well (P / W) of a second conductivity type different from the first conductivity type formed in the semiconductor substrate (N-SUB);

[0197] an output terminal (T4) configured to be electrically connected to the semiconductor substrate (N-SUB);

[0198] A ground terminal (T7) configured to be applied with a ground voltage (GND);

[0199] A detection signal generating circuit (62a) configured to generate a negative current detection signal (DET) by detecting that the output voltage (OUT) appearing at the output terminal (T4) is lower than the ground voltage (GND) or the threshold voltage; and

[0200] A control circuit (62b) configured to switch whether to apply the ground voltage (GND) or the output voltage (OUT) to the well (P / W) according to the negative current detection signal (DET); and

[0201] The detection signal generating circuit (62a) comprises:

[0202] a comparator (CMP) configured to compare an output detection voltage (Vs) with the ground voltage (GND) or the threshold voltage to generate the negative current detection signal (DET);

[0203] a bias circuit (BIAS) configured to switch between applying the output voltage (OUT) or applying a bias voltage (VA-Vth) as the output detection voltage (Vs); and

[0204] The clamp circuit (CLP) is configured to operate when the absolute value of the output detection voltage (Vs) is higher than a clamp operation voltage (VCLP).

[0205] (Note 2)

[0206] According to the semiconductor device (1) described in Appendix 1, the clamping circuit (CLP) includes: at least one first diode (D1) connected with a first polarity between the application end of the output detection voltage (Vs) and the ground terminal (T7); and at least one second diode (D2) connected with a second polarity opposite to the first polarity between the application end of the output detection voltage (Vs) and the ground terminal (T7).

[0207] (Note 3)

[0208] The semiconductor device (1) according to Supplementary Note 1 or 2, wherein the bias circuit (BIAS) includes a first transistor (N5) connected between the output terminal (T4) and an application end of the output detection voltage (Vs); and

[0209] The clamping operation voltage (VCLP) is higher than a differential voltage (VA-Vth) obtained by subtracting a turn-on threshold voltage (Vth) of the first transistor from a voltage (VA) applied to a control terminal of the first transistor (N5).

[0210] (Note 4)

[0211] According to the semiconductor device (1) described in Supplementary Note 3, the bias circuit (BIAS) further includes a first resistor (R5) connected between the main electrode of the first transistor (N5) and the application end of the output detection voltage (Vs).

[0212] (Note 5)

[0213] According to the semiconductor device (1) described in Supplementary Note 4, the bias circuit (BIAS) further includes a second resistor (R6) connected between the control terminal of the first transistor (N5) and the application terminal of the power supply voltage (VDD).

[0214] (Note 6)

[0215] The semiconductor device (1) according to any one of Supplements 1 to 5, further comprising:

[0216] a second transistor (N3) configured to conduct or disconnect the well (P / W) and the ground terminal (T7) according to the negative current detection signal (DET); and

[0217] The third resistor (R4) is connected between the well (P / W) and the ground terminal (T7).

[0218] (Note 7)

[0219] The semiconductor device (1) according to any one of Supplementary Notes 1 to 6, further comprising: a power transistor (10) configured to be connected between the output terminal (T4) and the ground terminal (T7).

[0220] (Note 8)

[0221] An electronic device (100) comprising:

[0222] Inductive load (Z);

[0223] A half-bridge or full-bridge switching output stage (M1-M4) configured to drive the load (Z); and

[0224] The semiconductor device (1) described in any one of Supplementary Notes 1 to 7 is configured to become the lower side switching element (M2, M4) or its driving mechanism of the switching output stage (M1 to M4).

[0225] (Note 9)

[0226] The electronic device (100) according to Supplementary Note 8, wherein the load (Z) includes a motor.

[0227] (Note 10)

[0228] A vehicle (X) comprising the electronic device (100) according to Supplementary Note 8 or 9.

[0229] <Other>

[0230] In addition, the various technical features disclosed in this specification can be modified in various ways without departing from the scope of the technical creation in addition to the embodiments described. In other words, the embodiments described should be considered to be illustrative and non-restrictive in all aspects. In addition, it should be understood that the technical scope of the present disclosure is defined by the claims, including all changes within the meaning and scope equivalent to the claims.

[0231] [Explanation of Symbols]

[0232] 1 Semiconductor device (Low-side switch LSI)

[0233] 10 Power transistor (NMOSFET)

[0234] 20 Sense transistor (NMOSFET)

[0235] 30 Grid control system

[0236] 31 Slew rate control circuit

[0237] 32 Active clamp circuit

[0238] 33 Gate resistance

[0239] 34 transistors (NMOSFET)

[0240] 40 Logic

[0241] 50 Input System

[0242] 51 Input control circuit

[0243] 52 Start control circuit

[0244] 53 UVLO circuit

[0245] 60 Benchmark Systems

[0246] 61 Reference generation circuit

[0247] 62 Negative current detection circuit

[0248] 62a Detection signal generating circuit

[0249] 62b Reference voltage control circuit

[0250] 70 Protection System

[0251] 71 Overcurrent protection circuit

[0252] 72 Temperature protection circuit

[0253] 73 Load open circuit detection circuit

[0254] 80 Status output unit

[0255] 91,92 Current limiting resistor

[0256] 100 Electronic equipment

[0257] 201 N-type semiconductor substrate

[0258] 202 N-type epitaxial layer

[0259] 203 Trench Gate

[0260] 204 N-type drift area

[0261] 205 N-type main area

[0262] 206 High concentration P-type region

[0263] 207 High-concentration N-type region

[0264] 208 Component separation area

[0265] 209 Via

[0266] 210 Metal wiring

[0267] 211 High Voltage P-type Well

[0268] 212 Low voltage P-type well

[0269] 213a, 213b High concentration N-type region

[0270] 214 High concentration P-type region

[0271] 215 gate insulation layer

[0272] 216 Component separation area

[0273] 217 Via

[0274] 218,219,220,221 Metal wiring

[0275] 222 protective layer

[0276] BD Body diode

[0277] CHG Charging Unit

[0278] CMP Comparator

[0279] D1,D2 diodes

[0280] DCHG Discharge Unit

[0281] E Voltage Source

[0282] M1~M4 transistors (NMOSFET)

[0283] N1~N5,Nx transistor (NMOSFET)

[0284] P1, P2 transistors (PMOSFET)

[0285] Q1 parasitic transistor (npn bipolar transistor)

[0286] R1~R6 resistors

[0287] REF Reference current source

[0288] T1~T7 external terminals

[0289] X Vehicle

[0290] Z load.

Claims

1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a well of a second conductivity type, which is different from the first conductivity type formed in the semiconductor substrate; an output terminal configured to be electrically connected to the semiconductor substrate; A ground terminal configured to be applied with a ground voltage; a detection signal generating circuit configured to generate a negative current detection signal by detecting that the output voltage at the output terminal is lower than the ground voltage or the threshold voltage; and A control circuit is configured to switch whether to apply the ground voltage or the output voltage to the well according to the negative current detection signal; and The detection signal generating circuit comprises: a comparator configured to compare the output detection voltage with the ground voltage or the threshold voltage to generate the negative current detection signal; a bias circuit configured to switch between applying the output voltage or applying a bias voltage as the output detection voltage; and The clamp circuit is configured to operate when the absolute value of the output detection voltage is higher than a clamp operation voltage.

2. The semiconductor device according to claim 1, wherein the clamping circuit comprises: at least one first diode connected with a first polarity between the application end of the output detection voltage and the ground terminal; and at least one second diode connected with a second polarity opposite to the first polarity between the application end of the output detection voltage and the ground terminal.

3. The semiconductor device according to claim 1 or 2, wherein the bias circuit includes a first transistor connected between the output terminal and an application end of the output detection voltage; and The clamping operation voltage is higher than a differential voltage obtained by subtracting an on-threshold voltage of the first transistor from a voltage applied to a control terminal of the first transistor. 4 . The semiconductor device according to claim 3 , wherein the bias circuit further includes a first resistor connected between a main electrode of the first transistor and an application terminal of the output detection voltage. 5 . The semiconductor device according to claim 4 , wherein the bias circuit further includes a second resistor connected between a control terminal of the first transistor and an application terminal of a power supply voltage.

6. The semiconductor device according to any one of claims 1 to 5, further comprising: a second transistor configured to switch on / off the connection between the well and the ground terminal according to the negative current detection signal; and The third resistor is connected between the well and the ground terminal. 7 . The semiconductor device according to claim 1 , further comprising: a power transistor connected between the output terminal and the ground terminal.

8. An electronic device comprising: Inductive loads; A half-bridge or full-bridge switching output stage configured to drive the load; and The semiconductor device according to any one of claims 1 to 7 is configured to serve as a lower switching element or a driving mechanism thereof in the switching output stage.

9. The electronic machine according to claim 8, wherein the load comprises a motor.

10. A vehicle comprising the electronic device according to claim 8 or 9.

Images