Data transmission device and method, electronic equipment and storage medium

Abstract

The invention provides a data transmission device and method, electronic equipment and a storage medium, and relates to the technical field of data processing, the data transmission device comprises a data splicing unit and an address calculation unit; wherein the data splicing unit is used for carrying out data splicing processing on input data according to input bit width information, initial offset information and output bit width information under the condition that data initial offset exists, and outputting spliced output data; wherein the address calculation unit is used for performing address calculation and maintenance on the read spliced output data according to a read initial address, a write-in initial address and a read length.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a data transmission device, method, electronic equipment and storage medium. Background Art

[0002] Direct Memory Access (DMA) allows data to be transferred independently and at high speed between different address spaces, such as between peripherals and memory or between memory and memory. When the processor or processing unit starts the transfer operation, the DMA controller will take over and complete the data transfer task.

[0003] However, traditional DMA has limitations when dealing with unaligned or offset data addresses because it requires data to be aligned to specific boundaries. In this case, traditional DMA often cannot work effectively and usually requires data to be rearranged in advance, which not only adds extra time cost but also reduces efficiency.

[0004] Therefore, how to efficiently transmit address-unaligned data has become a problem that needs to be solved urgently in the industry. Summary of the invention

[0005] The present invention provides a data transmission device, method, electronic equipment and storage medium, which are used to solve the problem of how to efficiently perform data transmission in the prior art.

[0006] The present invention provides a data transmission device, comprising: Data splicing unit and address calculation unit; The data splicing unit is used to perform data splicing processing on the input data according to the input bit width information, the starting offset information, and the output bit width information when there is a data starting offset, and output the spliced ​​output data; The address calculation unit is used to calculate and maintain the address of the spliced ​​output data read according to the read start address, the write start address and the read length.

[0007] According to a data transmission device provided by the present invention, the data splicing unit comprises: a data writing module, a data output module, a ring register and a position control module; Wherein, the position control module is used to maintain a write pointer and a read pointer; The data writing module is used to write the input data into the ring register and update the write pointer according to the input bit width information; The data output module is used to output the spliced ​​output data according to the read pointer and update the read pointer; wherein the spliced ​​output data is data output after data splicing is performed on the data in the ring register.

[0008] According to a data transmission device provided by the present invention, the data output module is specifically used for: Initializing the read pointer to the starting offset information; When the distance that the write pointer in the ring register leads the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data corresponding to the byte length of the output bit width information, and at the same time, the read pointer is maintained.

[0009] According to a data transmission device provided by the present invention, the data output module is further used for: In the ring register, when the write pointer is located behind the read pointer and the difference between the sum of the write pointer and the depth of the ring register and the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data of the byte length corresponding to the output bit width information, and at the same time, the read pointer is maintained.

[0010] The present invention also provides a data transmission method based on any of the above data transmission devices, comprising: The data splicing unit performs data splicing processing on the input data according to the input bit width information, the starting offset information, and the output bit width information when there is a data starting offset, and outputs the spliced ​​output data; The address calculation unit is used to calculate and maintain the address of the spliced ​​output data read according to the read start address, the write start address and the read length.

[0011] According to a data transmission method provided by the present invention, the data splicing unit performs data splicing processing on input data according to input bit width information, start offset information, and output bit width information when there is a data start offset, and outputs spliced ​​output data, including: The data writing module in the data splicing unit writes the input data into the ring register and updates the write pointer according to the input bit width information; The data output module in the data splicing unit outputs the splicing output data according to the read pointer and updates the read pointer; wherein the splicing output data is data output after data splicing is performed on the data in the ring register in the data splicing unit.

[0012] According to a data transmission method provided by the present invention, the method for obtaining spliced ​​output data includes: Initializing the read pointer to the starting offset information; When the distance that the write pointer in the ring register leads the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data corresponding to the byte length of the output bit width information, and at the same time, the read pointer is maintained.

[0013] According to a data transmission method provided by the present invention, the method for obtaining spliced ​​output data further includes: In the ring register, when the write pointer is located behind the read pointer and the difference between the sum of the write pointer and the depth of the ring register and the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data of the byte length corresponding to the output bit width information, and at the same time, the read pointer is maintained; The method for determining the depth of the ring register includes: The maximum value of the input bit width N and the output bit width M of the ring register is obtained, and the depth of the ring register is determined according to twice the maximum value of the bit width.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-mentioned data transmission methods when executing the computer program.

[0015] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, any of the data transmission methods described above is implemented.

[0016] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned data transmission methods.

[0017] The data transmission device, method, electronic device and storage medium provided by the present invention can significantly improve the efficiency of data transmission through the processing of the data splicing unit, especially when processing non-continuous or unaligned data. This efficient data processing capability makes data transmission faster and reduces the time consumption caused by data rearrangement. The data transmission device not only improves the efficiency and accuracy of data transmission through the coordinated work of its data splicing unit and address calculation unit, but also enhances the flexibility and performance of the system, especially when processing complex and changeable data transmission tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a structural schematic diagram of the data transmission device provided by the present invention.

[0020] Figure 2 A schematic diagram of the data splicing unit structure provided in an embodiment of the present application.

[0021] Figure 3 This is an example diagram of data splicing according to an embodiment of the present application.

[0022] Figure 4 A working diagram of the device provided in the embodiment of the present application; Figure 5 A schematic diagram of the Ethernet message structure provided in an embodiment of the present application; Figure 6 A schematic diagram of a data transmission method flow chart provided in an embodiment of the present application; Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] Figure 1 is a schematic diagram of the structure of the data transmission device provided by the present invention, such as Figure 1 As shown, including the following: Data splicing unit 101 and address calculation unit 102; The data splicing unit 101 is used to perform data splicing processing on the input data according to the input bit width information, the starting offset information, and the output bit width information when there is a data starting offset, and output the spliced ​​output data; Optionally, the data splicing unit includes: a data writing module, a data output module, a ring register and a position control module; Wherein, the position control module is used to maintain a write pointer and a read pointer; The data writing module is used to write the input data into the ring register and update the write pointer according to the input bit width information; The data output module is used to output the spliced ​​output data according to the read pointer and update the read pointer; wherein the spliced ​​output data is data output after data splicing is performed on the data in the ring register.

[0025] The data splicing unit 101 is a key part of the data transmission device, and is specially designed to handle the situation where there is a data start offset. It includes a data writing module, a data output module, a ring register and a position control module, which work together to achieve efficient data splicing and output.

[0026] Figure 2 A schematic diagram of the structure of a data splicing unit provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, it includes: a position control module 201, a data writing module 202, a data output module 203, and a ring register 204; The position control module is responsible for maintaining the write pointer and read pointer to ensure that data can be correctly written to and read from the ring register. The write pointer indicates where the next data block should be written to the ring register, while the read pointer indicates where the next data block should be read from the ring register.

[0027] The data write module is responsible for writing the input data to the ring register and updating the write pointer according to the input bit width information. This module ensures that the data is correctly stored in the ring register according to the input bit width and updates the write pointer to reflect the new write location.

[0028] The data output module splices the output data according to the read pointer output and updates the read pointer. This module reads the data from the ring register, performs the necessary splicing, and then outputs the spliced ​​data to the next processing stage or memory, while updating the read pointer to reflect the new read position.

[0029] The ring register is used as a data cache to temporarily store the written data. It supports fast loading, splicing and output of data and is a core component for implementing data splicing in the data splicing unit 101.

[0030] In the embodiment of the present application, the ring register is physically implemented by a register file and combinational logic. This implementation allows efficient data storage and access.

[0031] Depth of the ring register W Is a key parameter that determines how many bytes of data can be stored. W Must be at least the input widthN and output bit width M twice the maximum value in .

[0032] Each time a transmission is configured, the data splicing unit 101 needs to set the input bit width N Byte, output bit width M Bytes, and starting offset K Bytes, where K <N .

[0033] The position control module 201 maintains two pointers: write pointer P and read pointer Pr .

[0034] Input data is written to the pointer each time Start writing to the ring register 204, when and or and When writing is allowed, the position control module 201 updates the write pointer for When writing is not allowed, it will wait for the read operation before determining when writing is allowed.

[0035] Read pointer Initialized at the beginning of the transfer .

[0036] when and or and When a read operation occurs, M bytes of data are read. After the read operation, the read pointer Updated to .

[0037] The read and write pointers are calculated in a circular manner: and , to ensure that the pointer loops within the range of the ring register.

[0038] The address calculation unit 102 is used to calculate and maintain the address of the spliced ​​output data according to the read start address, the write start address and the read length.

[0039] In the embodiment of the present application, the address calculation unit 102 is responsible for performing accurate address calculation on the data according to the provided read start address, write start address and read length, including determining the address from which the data should be read and the address to which the data should be written.

[0040] This unit not only calculates the address, but is also responsible for maintaining this address information, ensuring the correctness and consistency of the address during data transfer. This involves updating the address after each data transfer to point to the read and write location of the next data block.

[0041] The address calculation unit 102 manages the data flow to ensure that the data is moved from the source address to the target address in an orderly and accurate manner. It controls the flow of data by maintaining address information to avoid data overwriting or loss.

[0042] In the embodiment of the present application, through the processing of the data splicing unit, the device can significantly improve the efficiency of data transmission, especially when processing non-continuous or unaligned data. This efficient data processing capability makes data transmission faster and reduces the time consumption caused by data rearrangement. The data transmission device not only improves the efficiency and accuracy of data transmission through the coordinated work of its data splicing unit and address calculation unit, but also enhances the flexibility and performance of the system, especially when processing complex and changeable data transmission tasks.

[0043] Optionally, the data output module is specifically used to: Initializing the read pointer to the starting offset information; When the distance that the write pointer in the ring register leads the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data corresponding to the byte length of the output bit width information, and at the same time, the read pointer is maintained.

[0044] The data output module is further specifically used for: In the ring register, when the write pointer is located behind the read pointer and the difference between the sum of the write pointer and the depth of the ring register and the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data of the byte length corresponding to the output bit width information, and at the same time, the read pointer is maintained.

[0045] In the embodiment of the present application, the data output module initializes the read pointer to the position specified by the start offset information. This means that before starting data transmission, the read pointer will be set to the correct starting position in the ring register so that data can be read from there.

[0046] In the embodiment of the present application, when the distance that the write pointer in the ring register leads the read pointer is greater than the output bit width information, the data output module triggers a read operation. This condition ensures that there is enough data in the ring register to be read, avoiding conflicts between the read operation and the write operation.

[0047] In this case, the data output module reads data of a byte length corresponding to the output bit width information, that is, data of an output bit width of M bytes.

[0048] After each read operation, the data output module updates the position of the read pointer to point to the starting position of the next read operation. This is achieved by moving the read pointer forward by M bytes, that is, .

[0049] When the write pointer is behind the read pointer, and the difference between the sum of the write pointer and the depth of the ring register and the read pointer is greater than the output bit width information, the data output module will also trigger a read operation. This condition takes into account the circular nature of the ring register and ensures that there is enough data to read even when the write pointer wraps around to the end of the ring register.

[0050] In the embodiment of the present application, by precisely controlling the triggering conditions of the read operation, the data output module ensures the security and accuracy of data reading and avoids reading incompletely written data. The design of the data output module enables the ring register to be efficiently utilized, and the continuity and stability of the data flow can be maintained even when data writing and reading operations are frequently performed alternately. The data output module optimizes data flow control by controlling the triggering timing of the read operation and reduces delays and bottlenecks caused by improper data flow control.

[0051] Figure 3 This is an example diagram of data splicing in the embodiment of the present application, such as Figure 3 As shown in the figure, for a 64-bit wide storage, the addresses are arranged in bytes and aligned to 8 bytes. If 32 bytes of data are moved starting from address 3, it will not work if traditional DMA is used, and the processor will often hand it over to load instructions to complete this task.

[0052] Assume W=32, N=8, M=8, K=3; each time the Load instruction reads an 8-byte number, it needs to access the storage twice because it is a non-aligned access, concatenate the two data and then save them, which will increase the delay of moving the number and increase the memory access volume.

[0053] When using this device, after configuring the low address offset, high address offset, read start address, destination start address and length, this device only needs to access the storage 5 times to complete the data movement.

[0054] In the first clock cycle, 8 bytes of data A at address 3 are loaded. , ,because , so no data is output; In the second clock cycle, the 8-byte data B at address 4 is loaded. ,because , so output the data once, ; In the third clock cycle, the 8-byte data C at address 5 is loaded. ,because , so output the data once, ; In the fourth clock cycle, the 8-byte data D at address 6 is loaded. ,because , so output the data once, ; ; In the fifth clock cycle, the 8-byte data E at address 7 is loaded. ,because and , so output the data once, ; Therefore, the storage is read a total of 5 times. Except for the first time when data needs to be prepared, data can be output once in each of the other clock cycles.

[0055] In the embodiment of the present application, data with non-aligned start addresses can be moved, written into the cache or output from the exit. As a peripheral of a processor or a processing unit, it can greatly improve the efficiency of accessing storage.

[0056] It decouples reading and writing, supports the case where the inlet rate is equal to the outlet rate, and also supports the case where the inlet rate is less than the outlet rate. The device can make automatic adjustments; the inlet bit width and outlet bit width can be freely configured to support various combinations. It has a wide range of application scenarios, and can be used in scenarios such as fast load movement in network message processing.

[0057] Figure 4 The working flow diagram of the device provided in the embodiment of the present application is as follows: Figure 4 As shown, first, configure a data transmission, including parameters such as read start address, write start address, move length, and input and output bit width; Then, the address calculation unit normalizes the read address, write address and length to ensure the accuracy of data movement; according to the set starting offset, the address calculation unit maintains an initial read pointer to track the starting position of data movement; After the entry data is written into the ring register, the data splicing unit is responsible for maintaining the write pointer to ensure that the data is correctly written into the ring register. The address calculation unit will also maintain the read address to ensure that the address is correctly updated during the data movement process.

[0058] When enough data is accumulated in the ring register, the data will be output from the exit. During this process, the data splicing unit is responsible for maintaining the read pointer, while the address calculation unit maintains the write address and the remaining transfer length, and the transfer length is reduced by 1 for each data output.

[0059] If the remaining transfer length has not reached 0, that is, the data transfer has not been completed, the process will continue to return to the step of writing the entry data into the ring register, and the data splicing unit will maintain the write pointer, and the address calculation unit will maintain the read address.

[0060] Once the remaining transfer length is equal to zero, all data has been successfully transmitted and the data transmission is completed.

[0061] Figure 5 The schematic diagram of the Ethernet message structure provided in the embodiment of the present application is as follows: Figure 5 As shown, on the receiving side of the network processor, for a message including a payload, the payload portion is usually accessed into the SRAM. Since the position of the payload in the network message is not fixed and there may be misalignment, this device is needed to accelerate the movement work.

[0062] In an ORAN message of a 5G fronthaul interface, a 5000-byte message has a total header of 36 bytes, which requires 100 clock overheads; the payload is 4964 bytes, and using this device to move data only requires 621 clocks. On average, processing 1 8-byte message requires only 1.15 clock overheads, making the network throughput reach 55.6Gbps, which greatly reduces system latency and improves the processing rate of the network processor.

[0063] The data transmission method provided by the present invention is described below. The data transmission method described below and the data transmission device described above can be referenced to each other.

[0064] Figure 6 A schematic diagram of a data transmission method flow chart provided in an embodiment of the present application, such as Figure 6 As shown, including: Step 610: When there is a data start offset, the data splicing unit performs data splicing processing on the input data according to the input bit width information, the start offset information, and the output bit width information, and outputs spliced ​​output data; Step 620: the address calculation unit is used to calculate and maintain the address of the spliced ​​output data read according to the read start address, the write start address and the read length.

[0065] Optionally, when there is a data start offset, the data splicing unit performs data splicing processing on the input data according to the input bit width information, the start offset information, and the output bit width information, and outputs the spliced ​​output data, including: The data writing module in the data splicing unit writes the input data into the ring register and updates the write pointer according to the input bit width information; The data output module in the data splicing unit outputs the splicing output data according to the read pointer and updates the read pointer; wherein the splicing output data is data output after data splicing is performed on the data in the ring register in the data splicing unit.

[0066] Optionally, the method for obtaining the spliced ​​output data includes: Initializing the read pointer to the starting offset information; When the distance that the write pointer in the ring register leads the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data corresponding to the byte length of the output bit width information, and at the same time, the read pointer is maintained.

[0067] Optionally, the method for obtaining the spliced ​​output data further includes: In the ring register, when the write pointer is located behind the read pointer and the difference between the sum of the write pointer and the depth of the ring register and the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data of the byte length corresponding to the output bit width information, and at the same time, the read pointer is maintained.

[0068] In the embodiment of the present application, through the processing of the data splicing unit, the device can significantly improve the efficiency of data transmission, especially when processing non-continuous or unaligned data. This efficient data processing capability makes data transmission faster and reduces the time consumption caused by data rearrangement. The data transmission device not only improves the efficiency and accuracy of data transmission through the coordinated work of its data splicing unit and address calculation unit, but also enhances the flexibility and performance of the system, especially when processing complex and changeable data transmission tasks.

[0069] Figure 7 is a schematic diagram of the structure of the electronic device provided by the present invention, such as Figure 7As shown, the electronic device may include: a processor 710, a communication interface 720, a memory 730 and a communication bus 740, wherein the processor 710, the communication interface 720 and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute the data transmission method, which includes: the data splicing unit performs data splicing processing on the input data according to the input bit width information, the starting offset information and the output bit width information in the case of the existence of the data starting offset, and outputs the spliced ​​output data; The address calculation unit is used to calculate and maintain the address of the spliced ​​output data read according to the read start address, the write start address and the read length.

[0070] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0071] On the other hand, the present invention further provides a computer program product, the computer program product includes a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the data transmission method provided by the above methods, the method includes: a data splicing unit performs data splicing processing on input data according to input bit width information, starting offset information, and output bit width information in the case of a data starting offset, and outputs spliced ​​output data; The address calculation unit is used to calculate and maintain the address of the spliced ​​output data read according to the read start address, the write start address and the read length.

[0072] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to execute the data transmission method provided by the above methods, the method comprising: a data splicing unit performs data splicing processing on input data according to input bit width information, starting offset information, and output bit width information in the case where there is a data starting offset, and outputs spliced ​​output data; The address calculation unit is used to calculate and maintain the address of the spliced ​​output data read according to the read start address, the write start address and the read length.

[0073] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0074] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data transmission device, characterized in that: include: Data splicing unit and address calculation unit; The data splicing unit is used to perform data splicing processing on the input data according to the input bit width information, the starting offset information, and the output bit width information when there is a data starting offset, and output the spliced ​​output data; The address calculation unit is used to calculate and maintain the address of the spliced ​​output data read according to the read start address, the write start address and the read length.

2. The data transmission device according to claim 1, characterized in that: The data splicing unit includes: a data writing module, a data output module, a ring register and a position control module; Wherein, the position control module is used to maintain a write pointer and a read pointer; The data writing module is used to write the input data into the ring register and update the write pointer according to the input bit width information; The data output module is used to output the spliced ​​output data according to the read pointer and update the read pointer; wherein the spliced ​​output data is data output after data splicing is performed on the data in the ring register.

3. The data transmission device according to claim 2, characterized in that: The data output module is specifically used for: Initializing the read pointer to the starting offset information; When the distance that the write pointer in the ring register leads the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data corresponding to the byte length of the output bit width information, and at the same time, the read pointer is maintained.

4. The data transmission device according to claim 2, characterized in that: The data output module is further specifically used for: In the ring register, when the write pointer is located behind the read pointer and the difference between the sum of the write pointer and the depth of the ring register and the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data of the byte length corresponding to the output bit width information, and at the same time, the read pointer is maintained.

5. A data transmission method based on the data transmission device according to any one of claims 1 to 4, characterized in that: include: The data splicing unit performs data splicing processing on the input data according to the input bit width information, the starting offset information, and the output bit width information when there is a data starting offset, and outputs the spliced ​​output data; wherein the input bit width information and the output bit width information are different; The address calculation unit is used to calculate and maintain the address of the spliced ​​output data read according to the read start address, the write start address and the read length.

6. The data transmission method according to claim 5, characterized in that: The data splicing unit performs data splicing processing on the input data according to the input bit width information, the starting offset information, and the output bit width information when there is a data starting offset, and outputs the spliced ​​output data, including: The data writing module in the data splicing unit writes the input data into the ring register and updates the write pointer according to the input bit width information; The data output module in the data splicing unit outputs the splicing output data according to the read pointer and updates the read pointer; wherein the splicing output data is data output after data splicing is performed on the data in the ring register in the data splicing unit.

7. The data transmission method according to claim 6, characterized in that: The method for obtaining the spliced ​​output data includes: Initializing the read pointer to the starting offset information; When the distance that the write pointer in the ring register leads the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data corresponding to the byte length of the output bit width information, and at the same time, the read pointer is maintained.

8. The data transmission method according to claim 7, characterized in that: The method for obtaining the spliced ​​output data further includes: In the ring register, when the write pointer is located behind the read pointer and the difference between the sum of the write pointer and the depth of the ring register and the read pointer is greater than the output bit width information, a read operation occurs to read the spliced ​​output data of the byte length corresponding to the output bit width information, and at the same time, the read pointer is maintained; The method for determining the depth of the ring register includes: The maximum value of the input bit width N and the output bit width M of the ring register is obtained, and the depth of the ring register is determined according to twice the maximum value of the bit width.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the data transmission method according to any one of claims 5 to 8 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data transmission method according to any one of claims 5 to 8 is implemented.

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