Three-core processor parallel controller self-correction method, system and program

Abstract

The invention discloses a three-core processor parallel controller self-correction method, system and program. The method comprises the following steps: receiving encrypted data of three processor cores of a three-core processor; the encrypted data is decrypted; comparing the three groups of decrypted data; and executing preset operation based on the comparison result. According to the processing scheme, on the premise that the performance of the processor is not affected, the instruction result comparison efficiency and the stability and reliability of the system are remarkably improved, and the method is suitable for high-performance calculation, real-time control and other complex application scenes.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a self-correction method, system and program for a parallel controller of a triple-core processor. Background Art

[0002] With the rapid development of information technology, multi-core processors have become a key technology to improve computing performance. However, in multi-core processor systems, especially in master-slave processor architectures, data inconsistency and errors have become important factors restricting system performance.

[0003] Therefore, how to create a self-correction method for multi-core processors has become a goal that the industry urgently needs to improve. Summary of the invention

[0004] In view of this, an embodiment of the present disclosure provides a self-correction method for a parallel controller of a triple-core processor, which at least partially solves the problems existing in the prior art.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for self-correction of a parallel controller of a three-core processor, the method comprising the following steps:

[0006] receiving encrypted data from three processor cores of a triple-core processor;

[0007] Decrypting the encrypted data;

[0008] Compare the three sets of decrypted data;

[0009] Perform a preset action based on the comparison results.

[0010] According to a specific implementation of the embodiment of the present disclosure, the performing of a preset operation based on the comparison result includes:

[0011] When the comparison of the three processor cores is completed and there is no error in the comparison, the request control code is queried again and the operation enable is issued to the current processor core;

[0012] When the comparison of the three processor cores is completed and one of the remaining two processor cores is faulty, the faulty processor core number and correction code are sent;

[0013] When the comparison of the three processor cores is completed and the three processor cores are all wrong when compared with each other, a global reset signal is sent.

[0014] According to a specific implementation manner of the embodiment of the present disclosure, the method further includes encrypting and decrypting information sent between the master processor and the slave processor.

[0015] According to a specific implementation of the embodiment of the present disclosure, the encryption includes:

[0016] Concatenate the processor number, register number, control code and register data;

[0017] Shift the control code and register data right by the register number, and concatenate them with the processor number and register number to obtain the initial encrypted data;

[0018] The final encrypted data is obtained by concatenating the initially encrypted data with the processor number.

[0019] According to a specific implementation of the embodiment of the present disclosure, the decryption includes:

[0020] Shift the encrypted data left by the processor number bit, and concatenate it with the processor number to obtain the initial decrypted data; wherein the initial decrypted data includes the processor number, the register number and the encrypted data;

[0021] The encrypted data is shifted left by the register number bit, and concatenated with the processor number and the register number to obtain the completely decrypted data; wherein the completely decrypted data includes the processor number, the register number, the control code and the register data.

[0022] In a second aspect, an embodiment of the present disclosure provides a three-core processor parallel controller self-correction system, the system comprising:

[0023] A receiving module, configured to receive encrypted data from three processor cores of the triple-core processor;

[0024] A decryption module, configured to decrypt the encrypted data;

[0025] A comparison module, configured to compare the three sets of decrypted data;

[0026] The execution module is configured to execute a preset operation based on the comparison result.

[0027] In a third aspect, an embodiment of the present disclosure further provides an electronic device, the electronic device comprising:

[0028] at least one processor; and,

[0029] a memory communicatively connected to the at least one processor; wherein,

[0030] The memory stores instructions that can be executed by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor implements the self-correction method of the three-core processor parallel controller as described in any one of the first aspect or any one of the implementations of the first aspect.

[0031] In a fourth aspect, an embodiment of the present disclosure further provides a computer program product, wherein the computer program product includes a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program includes program instructions, and when the program instructions are executed by a computer, the computer executes the self-correction method of the three-core processor parallel controller in the aforementioned first aspect or any implementation of the first aspect.

[0032] The three-core processor parallel controller self-correction method in the disclosed embodiment significantly improves the efficiency of instruction result comparison and the stability and reliability of the system by using a separate parallel controller without affecting the processor performance, and is suitable for complex application scenarios such as high-performance computing and real-time control. It can monitor and automatically correct data errors in real time, thereby ensuring the stability and reliability of the system, and providing strong support for application scenarios such as high-performance computing and real-time control. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0034] Figure 1 A framework diagram of a three-core processor parallel controller self-correction system provided by an embodiment of the present disclosure;

[0035] Figure 2 A schematic diagram of an information receiving module provided in an embodiment of the present disclosure;

[0036] Figure 3 A schematic diagram of an encrypted data format provided by an embodiment of the present disclosure;

[0037] Figure 4 A schematic diagram of an initial encrypted data format provided by an embodiment of the present disclosure;

[0038] Figure 5 A schematic diagram of a fully decrypted data format provided by an embodiment of the present disclosure;

[0039] Figure 6 A schematic diagram of a core control module architecture provided by an embodiment of the present disclosure;

[0040] Figure 7 A schematic diagram of an information sending module architecture provided in an embodiment of the present disclosure;

[0041] Figure 8 A schematic diagram of a format of data to be encrypted provided in an embodiment of the present disclosure;

[0042] Fig. 9 A schematic diagram of a format of initially encrypted data provided by an embodiment of the present disclosure;

[0043] Fig.10 A schematic diagram of a final encrypted data format provided by an embodiment of the present disclosure;

[0044] Fig.11 A schematic flow chart of a self-correction method for a three-core processor parallel controller provided by an embodiment of the present disclosure;

[0045] Fig.12 A schematic diagram of the structure of a three-core processor parallel controller self-correction system provided by an embodiment of the present disclosure;

[0046] Fig.13 A schematic diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0048] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0049] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement a device and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.

[0050] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0051] The embodiment of the present invention provides a self-correction method for a three-core processor parallel controller. By adopting a serial polling architecture, during the operation of the three-core processor, when each processor core completes the execution of an instruction, the processor execution is paused, and the currently modified register number and data are uniformly sent to the parallel controller. The parallel controller ensures the stable operation of the three processor cores by comparing the three-core register data and numbers. If the comparison result of a single processor is wrong, the results of the two processors can be used to correct another erroneous processor; if the comparison results of the three cores are different, a global reset is initiated to ensure that the three-core processor continues to be error-free during operation. The system has simple logic and high correction efficiency, which greatly improves the operation stability of the three-core system.

[0052] Figure 1 A framework diagram of a three-core processor parallel controller self-correction system provided by the present invention.

[0053] like Figure 1 As shown in the figure, the overall framework mainly includes three processor cores, three-core controllers and data buses. Each processor core includes five parts: processor core, general register stack (or register), information receiving module, core control module and information sending module. The following is a description of each part:

[0054] Data bus: The data bus serves as the data bus for the three processor cores to interact with the outside world and is responsible for receiving read and write requests from the processor cores.

[0055] Three-core controller: The three-core controller is connected to three processor cores. It receives encrypted data from the three processor cores, decrypts them separately, and compares the three sets of processor data sent by the three cores. According to the different comparison results, it sends encrypted instructions to each processor core to reset, continue to run, and self-correct.

[0056] Processor core: The three processor cores serve as the core of the entire system, executing the same program independently and ensuring the stability of the three cores through polling and comparison.

[0057] Processor core: Each core executes its own instruction stream independently, and polls each other to ensure the correctness of instruction execution.

[0058] General register stack: This part is the register required for instructions, which is responsible for reporting temporary data and data pointers saved during the execution of each processor core. Each processor analyzes whether the current instruction stream has an execution error by comparing this module.

[0059] Information receiving module: This module receives polling data (including the current processor core number, changed register number, changed register data and control code) sent by other processor cores, compares it with the register data sent by the current processor core, thereby confirming the next control code and sending the control code to the core control module.

[0060] Core control module: The core control module receives the control code from the information receiving module and the register data from the general register stack. After analysis, it sends a global reset signal to the main reset device as required, sends self-correction data and control enable to the general register stack, and sends a new control code to the information sending module.

[0061] Information sending module: Figure 7 As shown, the module receives the control enable and control code from the core control module, encrypts the register information of the current processor core, and sends it to the target processor core.

[0062] The internal structure of the information receiving module is as follows: Figure 2 As shown in the figure, it mainly includes register backup module, shift decryption module, data comparison module and decoding module. Each part is introduced as follows:

[0063] Register backup module: This part is responsible for saving the register information sent from the general register stack (including the changed register number and the register data after the change), and backing up the data and sending it to the data comparison module.

[0064] Shift decryption module: This part is responsible for receiving the initial encrypted data sent by other processing cores. Figure 3 As shown in the figure, bits 73-72 are the processor core number that initiated the request, and bits 71-0 are the decrypted data. When decrypting, the encrypted data needs to be shifted left by the processor number and the processor number is concatenated to obtain the initial decrypted data. The initial decrypted data is as follows Figure 4 As shown, bits 71-67 are register numbers. When decrypting again, the encrypted data needs to be shifted left by the register number, the processor number, and the register number to obtain the fully decrypted data, such as Figure 5 As shown, 66-64 are three-bit control codes, and 63-0 are register data. After decryption is completed, the register number and register data are sent to the data comparison module, and the current control code and the processor number that initiated the request are sent to the decoding module.

[0065] Data comparison module: This module receives the register information from the register backup module and the register data from the shift decryption module, compares the two parts of data, and sends the comparison result to the core control module.

[0066] Decoding module: This module receives the three-digit control code and the processor number that issued the request from the shift decryption module, analyzes the decoding result, and sends the control information (instruction type, instruction result) to the core control module.

[0067] The internal structure of the core control module is as follows: Figure 6 As shown in the figure, it mainly includes control distribution module, self-correction module, comparison request initiation module and global reset module. Each part is introduced as follows:

[0068] Control distribution module: This module receives the comparison results and control information from the information receiving module and the instruction completion enable from the general register stack. If the current processor has errors when compared with the other two cores, and the other two cores have no errors when compared with each other, then the control enable, register number and correction data are sent to the self-correction module; if the three cores have errors when compared with each other, then an enable signal is sent to the global reset module; if the comparison between the three cores is not yet completed or there are no errors after the comparison is completed, a run enable is sent to the current processor core, allowing the current processor core to continue running and waiting for the instruction completion enable from the processor core. When the enable is valid, the current control code and comparison result are sent to the comparison request initiation module.

[0069] Self-correction module: This module receives the control enable, register number and correction data from the control distribution module. If the enable is valid, the self-correction module writes the register number and correction data sent by the control distribution module into the register stack of the current processor to correct the current processor behavior.

[0070] Comparison request initiation module: This module receives the control code and comparison results from the control distribution module, analyzes the control code and comparison results, and if the three-core comparison is completed and there is no error in the comparison, it sends a re-query request control code to the information sending module; if the three-core comparison is completed and an error occurs in one of the remaining two processor cores, the error processor core number and correction code are sent to the information sending module; if the three-core comparison is still not completed, a continue comparison control code is sent to the information sending module.

[0071] Global reset module: This module receives the global reset enable from the control distribution module. If the enable is valid, it sends a global reset signal to the system to reset the entire system and restart it.

[0072] The internal structure of the information sending module is as follows Figure 6 As shown in the figure, it mainly includes the encoding module, register backup module and encryption module. Each part is introduced as follows:

[0073] Encoding module: This module receives the control code and error processor number from the core controller. According to the control code and error processor number, it updates the control code and sends the error processor number and the new control code to the encryption module.

[0074] Register backup module: This part is responsible for saving the register information sent from the general register stack (including the changed register number and the register data after the change), and backing up the data and sending it to the encryption module.

[0075] Encryption module: This module receives the register information from the register backup module and the data from the encoding module (including the changed register number and the changed register data), and concatenates these four parts of information in the following format: Figure 8 When encrypting, the 66-0 bit data (three-bit control code + register data) is right-shifted by a certain number of bits (the number of right-shift bits is equal to the register number), the processor number, and the register number are concatenated to obtain the initial encrypted data, as shown in Fig. 9 When encrypting for the second time, the 71-0 bits of the first encrypted data (register number + first shift result) are right shifted by a certain number of bits (the number of right shifts is equal to the register number) and the processor number are concatenated to form the final encrypted data, the format of which is as follows: Fig.10 As shown. The final encrypted data is sent to the next processor.

[0076] Fig.11 A schematic diagram of a self-correction method flow for a parallel controller of a triple-core processor provided in an embodiment of the present disclosure.

[0077] like Fig.11 As shown, at step S1110, encrypted data of three processor cores of a triple-core processor are received.

[0078] More specifically, the three processor cores of the triple-core processor receive the encrypted data from the bus; and send the encrypted data to the register stack; the register stack sends the encrypted data to the core control module; and the core control module sends the encrypted data to the information sending module.

[0079] More specifically, go to step S1120 next.

[0080] In step S1120, the encrypted data is decrypted.

[0081] In an embodiment of the present invention, the method further includes encrypting and decrypting information sent between the master processor and the slave processor.

[0082] In an embodiment of the present invention, the encryption includes: splicing the processor number, register number, control code and register data; right-shifting the control code and register data by the register number bit, and splicing them with the processor number and register number to obtain initial encrypted data; splicing the initial encrypted data with the processor number to obtain final encrypted data.

[0083] In an embodiment of the present invention, the decryption includes: shifting the encrypted data left by the processor number bit, and concatenating it with the processor number to obtain initial decrypted data; wherein the initial decrypted data includes the processor number, the register number and the encrypted data; shifting the encrypted data left by the register number bit, and concatenating it with the processor number and the register number to obtain complete decrypted data; wherein the complete decrypted data includes the processor number, the register number, the control code and the register data.

[0084] More specifically, the encrypted data is decrypted by a decoding module in the information sending module.

[0085] Next go to step S1130.

[0086] In step S1130, the three sets of decrypted data are compared.

[0087] Next go to step S1140.

[0088] At step S1140 , a preset operation is performed based on the comparison result.

[0089] In an embodiment of the present invention, the preset operation is performed based on the comparison result, including: when the comparison of the three processor cores is completed and there is no error in the comparison, re-querying the request control code and sending a run enable to the current processor core; when the comparison of the three processor cores is completed and an error occurs in one of the remaining two processor cores, sending the error processor core number and correction code; when the comparison of the three processor cores is completed and the three processor cores are all wrong when compared with each other, sending a global reset signal.

[0090] The three-core processor parallel controller self-correction method proposed in the present invention significantly improves the efficiency of instruction result comparison and the stability and reliability of the system by using a separate parallel controller without affecting the processor performance. It is suitable for complex application scenarios such as high-performance computing and real-time control.

[0091] Fig.12 The present invention shows a three-core processor parallel controller self-correction system 1200 , which includes a receiving module 1210 , a decryption module 1220 , a comparison module 1230 and an execution module 1240 .

[0092] The receiving module 1210 is used to receive encrypted data of three processor cores of the triple-core processor;

[0093] The decryption module 1220 is used to decrypt the encrypted data;

[0094] The comparison module 1230 is used to compare the three sets of decrypted data;

[0095] The execution module 1240 is used to execute a preset operation based on the comparison result.

[0096] See also Fig.13 The present disclosure also provides an electronic device 130, which includes:

[0097] at least one processor; and,

[0098] a memory communicatively connected to the at least one processor; wherein,

[0099] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the three-core processor parallel controller self-correction method in the aforementioned method embodiment.

[0100] The embodiment of the present disclosure also provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable the computer to execute the three-core processor parallel controller self-correction method in the aforementioned method embodiment.

[0101] An embodiment of the present disclosure also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the three-core processor parallel controller self-correction method in the aforementioned method embodiment.

[0102] Reference below Fig.13 , which shows a schematic diagram of the structure of an electronic device 130 suitable for implementing the embodiment of the present disclosure. The electronic device in the embodiment of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (such as vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.13 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0103] like Fig.13As shown, the electronic device 130 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 1301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1302 or a program loaded from a storage device 1308 to a random access memory (RAM) 1303. In the RAM 1303, various programs and data required for the operation of the electronic device 130 are also stored. The processing device 1301, the ROM 1302, and the RAM 1303 are connected to each other via a bus 1304. An input / output (I / O) interface 1305 is also connected to the bus 1304.

[0104] Typically, the following devices may be connected to the I / O interface 1305: input devices 1306 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 1307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 1308 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 1309. The communication device 1309 may allow the electronic device 130 to communicate wirelessly or wired with other devices to exchange data. Although the electronic device 130 with various devices is shown in the figure, it should be understood that it is not required to implement or have all the devices shown. More or fewer devices may be implemented or have alternatively.

[0105] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 1309, or installed from a storage device 1308, or installed from a ROM 1302. When the computer program is executed by the processing device 1301, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0106] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0107] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0108] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device: obtains at least two Internet Protocol addresses; sends a node evaluation request including the at least two Internet Protocol addresses to a node evaluation device, wherein the node evaluation device selects an Internet Protocol address from the at least two Internet Protocol addresses and returns it; receives the Internet Protocol address returned by the node evaluation device; wherein the obtained Internet Protocol address indicates an edge node in a content distribution network.

[0109] Alternatively, the computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device: receives a node evaluation request including at least two Internet Protocol addresses; selects an Internet Protocol address from the at least two Internet Protocol addresses; and returns the selected Internet Protocol address; wherein the received Internet Protocol address indicates an edge node in a content distribution network.

[0110] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0111] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0112] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware. The name of a unit does not limit the unit itself in some cases. For example, the first acquisition unit may also be described as a "unit for acquiring at least two Internet Protocol addresses".

[0113] It should be understood that various parts of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof.

[0114] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A self-correction method for a three-core processor parallel controller, characterized in that: The method comprises the following steps: receiving encrypted data from three processor cores of a triple-core processor; Decrypting the encrypted data; Compare the three sets of decrypted data; Perform a preset action based on the comparison results.

2. The three-core processor parallel controller self-correction method according to claim 1, characterized in that: The performing of a preset operation based on the comparison result includes: When the comparison of the three processor cores is completed and there is no error in the comparison, the request control code is queried again and the operation enable is issued to the current processor core; When the comparison of the three processor cores is completed and one of the remaining two processor cores is faulty, the faulty processor core number and correction code are sent; When the comparison of the three processor cores is completed and the three processor cores are all wrong when compared with each other, a global reset signal is sent.

3. The self-correction method of a three-core processor parallel controller according to claim 1, characterized in that: The method also includes encrypting and decrypting information sent between the master processor and the slave processor.

4. The three-core processor parallel controller self-correction method according to claim 3, characterized in that: The encryption includes: Concatenate the processor number, register number, control code and register data; Shift the control code and register data right by the register number, and concatenate them with the processor number and register number to obtain the initial encrypted data; The final encrypted data is obtained by concatenating the initially encrypted data with the processor number.

5. The three-core processor parallel controller self-correction method according to claim 3, characterized in that: The decryption comprises: Shift the encrypted data left by the processor number bit, and concatenate it with the processor number to obtain the initial decrypted data; wherein the initial decrypted data includes the processor number, the register number and the encrypted data; The encrypted data is shifted left by the register number bit, and concatenated with the processor number and the register number to obtain the completely decrypted data; wherein the completely decrypted data includes the processor number, the register number, the control code and the register data.

6. A three-core processor parallel controller self-correction system, characterized in that: The system comprises: A receiving module, configured to receive encrypted data from three processor cores of the triple-core processor; A decryption module, configured to decrypt the encrypted data; A comparison module, configured to compare the three sets of decrypted data; The execution module is configured to execute a preset operation based on the comparison result.

7. An electronic device, characterized in that: The electronic device includes: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor executes the self-correction method for a three-core processor parallel controller as described in any one of claims 1 to 5.

8. A computer program product, characterized in that The computer program product includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the self-correction method for a three-core processor parallel controller as described in any one of claims 1 to 5.

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