Memory monitoring method, device, system and equipment and medium

Abstract

The invention discloses a memory monitoring method, device, system and equipment and a medium, and relates to the technical field of computers. When it is monitored that a hardware error exists in the memory, hardware interruption is triggered through a preset programmable logic device, so that the micro-control unit is awakened to enter a working state; obtaining error data related to hardware errors in a preset target component by using the substrate management controller, and sending the error data to the awakened micro-control unit; and performing error type analysis on the error data based on the awakened micro-control unit, and sending an error processing request triggered based on an error type analysis result to an operating system of a preset target component, so that the operating system responds to the error processing request to obtain a corresponding error processing result. Through the technical scheme of the invention, the memory error can be quickly and accurately detected and timely processed, and the reliability, availability and energy efficiency management of the system are improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory monitoring method, device, system, equipment and medium. Background Art

[0002] Memory error detection and processing is an important part of computer system reliability. For different types of memory errors, the relevant technologies include the following three technical solutions: ECC (Error Checking and Correcting), memory checksum, and BMC (Baseboard Management Controller). The disadvantages are as follows: Because ECC processing requires data writing, data storage, and data reading, it will consume certain computing resources, resulting in memory access delays, especially under high load conditions, and its correction capability is limited. For multi-bit errors or other more complex error modes, ECC may not be able to effectively handle them; memory checksum can only detect errors, but cannot correct them, resulting in manual intervention or restart after errors are found, and it is easy to miss certain errors, with low precision and accuracy; after detecting an error, BMC often needs to process it through SMI (System Management Interrupt), which may not be able to efficiently respond to high-concurrency error detection and processing requests, resulting in slow processing speed, and if BMC fails, the function of the entire monitoring system will be affected, and other hardware components cannot be monitored or managed.

[0003] It can be seen that how to quickly and accurately detect memory errors and handle them in a timely manner to improve the reliability, availability and energy efficiency management of the system is a problem that technical personnel in this field need to solve. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a memory monitoring method, device, system, equipment and medium, which can quickly and accurately detect memory errors and handle them in a timely manner, thereby improving the reliability, availability and energy efficiency management of the system. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses a memory monitoring method, comprising:

[0006] Perform hardware error monitoring on memory;

[0007] When a hardware error is detected in the memory, a hardware interrupt is triggered by a preset programmable logic device to wake up the microcontroller unit and put it into working state;

[0008] Using the baseboard management controller to obtain error data related to the hardware error in the preset target component, and sending the error data to the awakened micro control unit;

[0009] The microcontroller unit after awakening performs error type analysis on the error data, and sends an error handling request triggered by the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains the corresponding error handling result.

[0010] Optionally, perform hardware error monitoring on the memory, including:

[0011] Starting the baseboard management controller to utilize the baseboard management controller to perform a memory self-check on itself during a startup loading phase;

[0012] A preset programmable logic device is used to monitor a process in which a baseboard management controller performs a memory self-test to determine whether there is a hardware error in the memory.

[0013] Optionally, a preset programmable logic device is used to monitor a process of performing a memory self-test on a baseboard management controller to determine whether there is a hardware error in the memory, including:

[0014] During the process of the baseboard management controller performing the memory self-test, monitoring whether the level of the general input / output port on the preset programmable logic device is a high level;

[0015] When the level of the general purpose input / output port is high, it is determined that there is no hardware error in the memory;

[0016] When the level of the general purpose input / output port is low, it is determined that there is a hardware error in the memory.

[0017] Optionally, when a hardware error is detected in the memory, a hardware interrupt is triggered by a preset programmable logic device to wake up the microcontroller unit to enter a working state, including:

[0018] When a hardware error is detected in the memory, a hardware interrupt is triggered through a preset programmable logic device, and a wake-up signal is sent to the microcontroller unit;

[0019] If the current state of the micro control unit is a low power mode state, the low power mode state of the micro control unit is changed to a normal working state based on the wake-up signal.

[0020] Optionally, the microcontroller unit after awakening performs an error type analysis on the error data, and sends an error handling request triggered by the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains a corresponding error handling result, including:

[0021] Performing error type analysis on the error data based on the awakened microcontroller unit to analyze the error type; the error type includes recoverable error and unrecoverable error;

[0022] If the error type is a recoverable error, the awakened microcontroller unit and the hardware management interface are used to trigger the corresponding memory page isolation processing request, and the memory page isolation processing request is sent to the operating system of the preset target component, so that the operating system uses the memory management technology and performs memory page offline and isolation operations on itself based on the memory page isolation processing request to obtain the corresponding error processing result;

[0023] If the error type is an irrecoverable error, the awakened microcontroller unit and the hardware management interface are used to trigger the corresponding memory mirror backup processing request, and the memory mirror backup processing request is sent to the operating system of the preset target component, so that the operating system can mirror the data corresponding to the processing request from the main memory module to the backup memory module based on the memory mirror backup processing request to obtain the corresponding error processing result.

[0024] Optionally, the memory monitoring method of the present application further includes:

[0025] Obtaining the error processing result from the operating system of the preset target component through the awakened microcontroller unit;

[0026] The baseboard management controller is used to obtain the error processing result and the corresponding error record from the awakened micro control unit, and the error processing result and the error record are saved in a preset shared memory, and the error record is sent to a preset remote server.

[0027] In a second aspect, the present application discloses a memory monitoring device, comprising:

[0028] A monitoring module, used for hardware error monitoring of memory;

[0029] The state wake-up module is used to trigger a hardware interrupt through a preset programmable logic device to wake up the microcontroller unit and put it into working state when a hardware error is detected in the memory;

[0030] An error data sending module, used to obtain error data related to hardware errors in a preset target component by using a baseboard management controller, and send the error data to a micro control unit after being awakened;

[0031] The processing module is used to perform error type analysis on the error data based on the awakened microcontroller unit, and send the error handling request triggered based on the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains the corresponding error handling result.

[0032] In a third aspect, the present application discloses a device system, including a preset programmable logic device, a baseboard management controller and a micro control unit; wherein,

[0033] A programmable logic device is preset to monitor the memory for hardware errors and wake up the microcontroller unit to enter a working state;

[0034] A baseboard management controller, used to obtain error data related to hardware errors in a preset target component and send the error data to the awakened microcontroller unit;

[0035] The microcontroller unit is used to perform error type analysis on error data after being awakened, and send an error handling request triggered based on the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains the corresponding error handling result.

[0036] In a fourth aspect, the present application discloses an electronic device, which includes a processor and a memory; wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the above-mentioned memory monitoring method.

[0037] In a fifth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program implements the aforementioned memory monitoring method when executed by a processor.

[0038] It can be seen that the present application provides a memory monitoring method, including: performing hardware error monitoring on the memory; when a hardware error is detected in the memory, triggering a hardware interrupt through a preset programmable logic device to wake up the microcontroller unit to enter a working state; using a baseboard management controller to obtain error data related to the hardware error in a preset target component, and sending the error data to the awakened microcontroller unit; performing error type analysis on the error data based on the awakened microcontroller unit, and sending an error handling request triggered based on the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains a corresponding error handling result. The present application is aimed at memory error monitoring and processing, and utilizes an optimization method combining software and hardware. First, hardware error monitoring is performed on the memory. When a hardware error is detected, a hardware interrupt is triggered by a preset programmable logic device, and the microcontroller unit is awakened to enter a working state, so that the error event can be processed in a timely manner. The baseboard management controller is used to obtain error data related to the hardware error in the preset target component, and then the error data is sent to the awakened microcontroller unit for error type analysis. A mode of collaborative work between the baseboard management controller and the microcontroller unit is adopted. By sending part of the error data analysis and processing tasks to the microcontroller unit, the load of the baseboard management controller is effectively reduced. The microcontroller unit sends an error processing request triggered based on the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error processing request and obtains a corresponding error processing result. The collaborative working mode can also quickly respond to hardware failures, improve the reliability and maintainability of the system, and improve the efficiency of server management. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A flow chart of a memory monitoring method disclosed in this application;

[0041] Figure 2 This is a diagram of a cooperative working architecture of a micro control unit and a baseboard management controller disclosed in this application;

[0042] Figure 3 A flowchart of specific steps for memory error monitoring and processing disclosed in this application;

[0043] Figure 4 A schematic diagram of the structure of a memory monitoring device disclosed in this application;

[0044] Figure 5 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] Memory error detection and processing is an important part of computer system reliability. For different types of memory errors, related technologies include the following three technical solutions: ECC, memory checksum, and BMC. The disadvantages are as follows: Because ECC processing requires data writing, data storage, data reading and other processes, it will consume certain computing resources, resulting in memory access delays, especially under high load conditions, and its correction capability is limited. For multi-bit errors or other more complex error modes, ECC may not be able to effectively handle them; memory checksum can only detect errors, but cannot correct them, resulting in manual intervention or restart after the error is found, and it is easy to miss certain errors, with low precision and accuracy; after detecting an error, BMC often needs to process it through SMI, and may not be able to efficiently respond to high-concurrency error detection and processing requests, resulting in slow processing speed, and if BMC fails, the function of the entire monitoring system will be affected, and other hardware components cannot be monitored or managed. It can be seen that how to quickly and accurately detect memory errors, and handle them in a timely manner to improve the reliability, availability and energy efficiency management of the system is a problem that technicians in this field need to solve.

[0047] See also Figure 1 As shown, an embodiment of the present invention discloses a memory monitoring method, which may specifically include:

[0048] Step S11: Perform hardware error monitoring on the memory.

[0049] In this embodiment, the baseboard management controller is started to perform a memory self-check on itself during the boot loading phase; a preset programmable logic device is used to monitor the process of the baseboard management controller performing the memory self-check to determine whether there is a hardware error in the memory.

[0050] Among them, a preset programmable logic device is used to monitor the process of the baseboard management controller performing a memory self-test to determine whether there is a hardware error in the memory, including: during the process of the baseboard management controller performing the memory self-test, monitoring whether the level of the general input / output port on the preset programmable logic device is a high level; when the level of the general input / output port is a high level, it is determined that there is no hardware error in the memory; when the level of the general input / output port is a low level, it is determined that there is a hardware error in the memory.

[0051] That is to say, when the BMC (Baseboard Management Controller) starts, the BMC will perform a memory self-test in the U-Boot (Universal Boot Loader) stage. During the memory self-test performed by the baseboard management controller, the BMC monitors whether the level of the general input / output port of the CPLD (Complex Programmable Logic Device) in the preset programmable logic device is high. If it is high, there is no hardware error in the memory. If it is low, there is a hardware error in the memory. The preset programmable logic device includes but is not limited to CPLD and FPGA (Field-Programmable Gate Array).

[0052] Step S12: When a hardware error is detected in the memory, a hardware interrupt is triggered by a preset programmable logic device to wake up the micro control unit and put it into working state.

[0053] In this embodiment, when a hardware error is detected in the memory, a hardware interrupt is triggered by a preset programmable logic device, and a wake-up signal is sent to the microcontroller unit; if the current state of the microcontroller unit is a low power mode state, the low power mode state of the microcontroller unit is changed to a normal working state based on the wake-up signal.

[0054] The present invention adopts a mode in which MCU (Microcontroller Unit) and BMC work together. When the system is in an error-free state, the MCU will enter a sleep mode in a low-power mode; when a hardware error is detected in the memory, the CPLD will trigger a hardware interrupt and send a wake-up signal to wake up the MCU from the sleep mode and enter a normal working state, so as to handle the error event in a timely manner.

[0055] Step S13: using the baseboard management controller to obtain error data related to the hardware error in the preset target component, and sending the error data to the awakened micro control unit.

[0056] In this embodiment, the baseboard management controller and the platform environment control interface are used to obtain error data related to the hardware error from the preset target component, and the error data is sent to the awakened micro control unit.

[0057] This application adopts the key technical feature of RAS Offload (RAS, namely Reliability, Availability, Serviceability), whose main purpose is to offload tasks related to reliability (Reliability), availability (Availability) and maintainability (Serviceability) from the main CPU (Central Processing Unit) and the operating system to the BMC, so as to reduce the burden on the main processor and improve the performance and reliability of the system. Under this mechanism, the collaborative work of MCU and BMC effectively improves the reliability, availability and energy efficiency management of the system. The collaborative work architecture of MCU and BMC is as follows: Figure 2 As shown in the figure, when BMC starts, BMC will perform memory self-check in the U-Boot stage. When the memory hardware fails, the CPLD on the motherboard triggers the hardware interrupt by pulling down the level of the corresponding GPIO (General-Purpose Input / Output) pin, and then sends a wake-up signal to the MCU. The MCU then enters the working state. At the same time, BMC communicates with the preset target components (including CPU and other platform components) through PECI (Platform Environment Control Interface) to obtain detailed error data related to the hardware error, and then sends the error data to the awakened MCU.

[0058] Step S14: Analyze the error type of the error data based on the awakened microcontroller unit, and send an error handling request triggered by the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains a corresponding error handling result.

[0059] In this embodiment, an error type analysis is performed on the error data based on the awakened microcontroller unit to analyze the error type; the error types include recoverable errors and irrecoverable errors; if the error type is a recoverable error, the awakened microcontroller unit and the hardware management interface are used to trigger the corresponding memory page isolation processing request, and the memory page isolation processing request is sent to the operating system of the preset target component, so that the operating system uses the memory management technology and performs memory page offline and isolation operations on itself based on the memory page isolation processing request to obtain the corresponding error processing result; if the error type is an irrecoverable error, the awakened microcontroller unit and the hardware management interface are used to trigger the corresponding memory mirror backup processing request, and the memory mirror backup processing request is sent to the operating system of the preset target component, so that the operating system mirrors the data corresponding to the processing request from the main memory module to the backup memory module based on the memory mirror backup processing request to obtain the corresponding error processing result.

[0060] The specific error type analysis process is as follows: For recoverable memory errors (that is, the error type is recoverable error), the MCU will send a memory page isolation processing request to the operating system of the preset target component so that the operating system can perform the Memory Page Offline operation of the specified memory page, thereby realizing the isolation management of memory errors. MemoryPage Offline is a memory management technology that is used to mark a memory page as unavailable and isolate it from the normal memory pool of the system when a hardware error is detected in the memory page. When a recoverable memory page error occurs and reaches a certain number of times, the MCU sends a memory page isolation processing request to perform the offline operation of the specified memory page, which can ensure that the impact of the memory error is limited to a specific page and avoid the overall system crash;

[0061] For unrecoverable memory errors (i.e., the error type is unrecoverable error), the MCU can still try to mark the memory block as unavailable and perform operations such as Memory Page Offline. If the error is serious enough to affect system stability, the corresponding memory mirror backup processing request is triggered, and the memory mirror backup processing request system is sent to the operating system so that the operating system can further enable memory mirroring technology to back up the corresponding data from the main memory module to the backup memory module. This design not only effectively reduces the burden on the BMC, but also optimizes the system's power consumption management and operating efficiency by quickly responding to hardware failures, thereby improving the system's reliability and maintainability.

[0062] In this embodiment, after obtaining the corresponding error handling result, it also includes: obtaining the error handling result from the operating system of the preset target component through the awakened microcontroller unit; using the baseboard management controller to obtain the error handling result and the corresponding error record from the awakened microcontroller unit, and saving the error handling result and the error record to the preset shared memory, and sending the error record to the preset remote server.

[0063] This application takes the BMC obtaining error processing results and error records from the MCU as an example. In the process of obtaining error records, the BMC can also generate corresponding error records and save the error records and the error processing results sent by the MCU to the preset shared memory.

[0064] The present invention adopts the low-power design of MCU. When the system runs normally and no error occurs, the MCU is in sleep mode to minimize power consumption. When a hardware error occurs, the signal sent by the CPLD wakes up the MCU, and the MCU quickly enters the working state, processes the error and synchronizes the result to the BMC. After the processing is completed, the MCU enters the sleep mode again to maintain low-power operation. This mechanism improves the timeliness of the system's error response and optimizes the overall power consumption. After the MCU receives the error data sent by the BMC, the error type is analyzed and processed, and the error processing result is written back to the preset shared memory of the BMC. Other components of the platform can obtain error records by accessing the preset shared memory of the BMC, and pass these error records to the operating system so that the operating system can perform further response and recovery operations. The MCU obtains and parses these error data through communication with the BMC, thereby realizing the prevention and processing of faults. This design effectively improves the real-time performance of the system in dealing with hardware faults, and at the same time reduces the pressure on the CPU by reasonably allocating tasks, further enhancing the reliability, stability and availability of the system. This architecture optimizes the allocation of computing resources and significantly improves the fault management capability of high-performance servers.

[0065] The present invention aims to improve system reliability, availability and maintainability. It uses an optimization method combining software and hardware to monitor and process memory errors, adopts a BMC and MCU collaborative architecture, reduces the burden on the CPU and BMC, and improves the efficiency of server management. Figure 3 As shown:

[0066] (1) Use the BMC to perform memory self-test during the boot loading phase and monitor the level changes of the general input / output ports on the CPLD.

[0067] (2) If the GPIO pin remains high, it means that no error is detected and the system continues to operate normally. If the GPIO pin is pulled low, that is, an error is detected, the MCU will receive a wake-up signal and wake up from the low power mode state to start processing the error.

[0068] (3) After the MCU is awakened, it will communicate with the BMC. The BMC collects detailed error data from the preset target component through PECI, and then sends the error data to the MCU. For the process of sending error data, during a CE Storm (Corrected Error Storm), the pressure on the BMC and the preset target component to handle will increase dramatically, and the introduction of the MCU can share the pressure.

[0069] (4) During the processing, the MCU will analyze the error type of the error data. For recoverable errors, the MCU sends a memory page isolation processing request to the system through the Redfish interface, executes the memory page offline operation, and isolates the erroneous memory page from the system to ensure the stability of the system. If an unrecoverable memory error is detected and the error affects the stability of the system, a memory mirror backup processing request is sent to the system, and the system will enable memory mirroring technology to redirect data from the main memory module to the backup memory module.

[0070] (5) After the MCU handles the error, it will write the processing result back to the preset shared memory of the BMC. The platform can obtain the error record by accessing the preset shared memory, and use Rsyslog to send the error record to the remote server for timely review by the operation and maintenance engineers. The data items include Socket, Imc, Channel, Slot, Rank, Device, BankGroup, Bank, RowAddress, Column, ErrorType, ParitySyn, Mode, EccBistValid, PersistentError, CorrFsmErrtype, EccBistErrtype, EccBistCorrErrDevnum, RrlLog, RrlMisc, RrlParity, RrlAddress1, RrlAddress2, RrlAddress3, etc.

[0071] In this embodiment, the memory is monitored for hardware errors; when a hardware error is detected in the memory, a hardware interrupt is triggered by a preset programmable logic device to wake up the microcontroller unit to enter a working state; the baseboard management controller is used to obtain error data related to the hardware error in the preset target component, and the error data is sent to the awakened microcontroller unit; based on the awakened microcontroller unit, an error type analysis is performed on the error data, and an error handling request triggered based on the error type analysis result is sent to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains a corresponding error handling result. The present application is aimed at memory error monitoring and processing, and utilizes an optimization method combining software and hardware. First, hardware error monitoring is performed on the memory. When a hardware error is detected, a hardware interrupt is triggered by a preset programmable logic device, and the microcontroller unit is awakened to enter a working state, so that the error event can be processed in a timely manner. The baseboard management controller is used to obtain error data related to the hardware error in the preset target component, and then the error data is sent to the awakened microcontroller unit for error type analysis. A mode of collaborative work between the baseboard management controller and the microcontroller unit is adopted. By sending part of the error data analysis and processing tasks to the microcontroller unit, the load of the baseboard management controller is effectively reduced. The microcontroller unit sends an error processing request triggered based on the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error processing request and obtains a corresponding error processing result. The collaborative working mode can also quickly respond to hardware failures, improve the reliability and maintainability of the system, and improve the efficiency of server management.

[0072] See also Figure 4 As shown, an embodiment of the present invention discloses a memory monitoring device, which may specifically include:

[0073] A monitoring module 11 is used to monitor the memory for hardware errors;

[0074] The state awakening module 12 is used to trigger a hardware interrupt through a preset programmable logic device to awaken the micro control unit to enter a working state when a hardware error is detected in the memory;

[0075] The error data sending module 13 is used to obtain the error data related to the hardware error in the preset target component by using the baseboard management controller, and send the error data to the awakened micro control unit;

[0076] The processing module 14 is used to perform error type analysis on the error data based on the awakened microcontroller unit, and send an error handling request triggered based on the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains a corresponding error handling result.

[0077] In some specific embodiments, the monitoring module 11 may specifically include:

[0078] The memory self-check module is used to start the baseboard management controller so as to use the baseboard management controller to perform a memory self-check on itself during the startup loading phase;

[0079] The memory self-check monitoring module is used to monitor the process of the baseboard management controller performing the memory self-check by using a preset programmable logic device to determine whether there is a hardware error in the memory.

[0080] In some specific embodiments, the monitoring module 11 may specifically include:

[0081] The level monitoring module is used to monitor whether the level of the general input / output port on the preset programmable logic device is a high level during the process of the baseboard management controller performing the memory self-test;

[0082] A hardware error-free module is used to determine that there is no hardware error in the memory when the level of the general input / output port is high;

[0083] There is a hardware error module, which is used to determine that there is a hardware error in the memory when the level of the general input / output port is low.

[0084] In some specific embodiments, the state awakening module 12 may specifically include:

[0085] The hardware interrupt trigger module is used to trigger a hardware interrupt through a preset programmable logic device when a hardware error in the memory is detected, and send a wake-up signal to the micro control unit;

[0086] The state changing module is used for changing the low power consumption mode state of the micro control unit to a normal working state based on the wake-up signal if the current state of the micro control unit is a low power consumption mode state.

[0087] In some specific embodiments, the processing module 14 may specifically include:

[0088] An error type analysis module is used to perform error type analysis on error data based on the awakened microcontroller unit to analyze the error type; the error type includes recoverable error and unrecoverable error;

[0089] The first error type processing module is used to trigger a corresponding memory page isolation processing request by using the awakened micro control unit and the hardware management interface if the error type is a recoverable error, and send the memory page isolation processing request to the operating system of the preset target component, so that the operating system uses the memory management technology and performs memory page offline and isolation operations on itself based on the memory page isolation processing request to obtain a corresponding error processing result;

[0090] The second error type processing module is used to trigger the corresponding memory mirror backup processing request by using the awakened micro control unit and the hardware management interface if the error type is an irrecoverable error, and send the memory mirror backup processing request to the operating system of the preset target component, so that the operating system can mirror the data corresponding to the processing request from the main memory module to the backup memory module based on the memory mirror backup processing request to obtain the corresponding error processing result.

[0091] In some specific embodiments, the memory monitoring device may further include:

[0092] An error processing result acquisition module is used to acquire the error processing result from the operating system of the preset target component through the awakened micro control unit;

[0093] The error record sending module is used to use the baseboard management controller to obtain the error processing result and the corresponding error record from the awakened micro control unit, save the error processing result and the error record in the preset shared memory, and send the error record to the preset remote server.

[0094] An embodiment of the present invention discloses a device system, which may specifically include a preset programmable logic device, a baseboard management controller and a microcontroller unit; wherein the preset programmable logic device is used to monitor hardware errors of a memory and wake up the microcontroller unit to enter a working state; the baseboard management controller is used to obtain error data related to hardware errors in a preset target component and send the error data to the microcontroller unit after being awakened; the microcontroller unit is used to perform error type analysis on the error data after being awakened, and send an error handling request triggered based on the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains a corresponding error handling result.

[0095] Furthermore, the present application also discloses an electronic device. Figure 5 This is a structural diagram of an electronic device 20 according to an exemplary embodiment, and the content in the diagram cannot be considered as any limitation on the scope of use of the present application.

[0096] Figure 5 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the memory monitoring method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be a computer.

[0097] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0098] In addition, the memory 22 as a carrier for resource storage may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon may include an operating system 221, a computer program 222 and data 223, etc. The data 223 may include various data. The storage method may be temporary storage or permanent storage.

[0099] The operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, and can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the memory monitoring method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0100] Furthermore, the embodiments of the present application also disclose a computer-readable storage medium, wherein the computer-readable storage medium mentioned here includes a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a magnetic disk or an optical disk, or any other form of storage medium known in the technical field. Among them, the aforementioned memory monitoring method is implemented when the computer program is executed by the processor. For the specific steps of the method, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0101] Furthermore, an embodiment of the present application also provides a computer program product, including a computer program / instruction, which implements any one of the above-mentioned memory monitoring methods when executed by a processor.

[0102] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0103] The steps of the memory monitoring method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0104] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0105] The above is a detailed introduction to a memory monitoring method, device, system, equipment and medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A memory monitoring method, characterized in that: include: Perform hardware error monitoring on memory; When a hardware error is detected in the memory, a hardware interrupt is triggered by a preset programmable logic device to wake up the microcontroller unit and put it into working state; Using a baseboard management controller to obtain error data related to the hardware error in a preset target component, and sending the error data to the awakened micro control unit; The microcontroller unit after awakening performs error type analysis on the error data, and sends an error handling request triggered based on the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains a corresponding error handling result.

2. The memory monitoring method according to claim 1, characterized in that: The hardware error monitoring of the memory includes: Starting a baseboard management controller to utilize the baseboard management controller to perform a memory self-check on itself during a startup loading phase; A preset programmable logic device is used to monitor the process of the baseboard management controller performing a memory self-check to determine whether there is a hardware error in the memory.

3. The memory monitoring method according to claim 2, characterized in that: The process of using a preset programmable logic device to monitor the process of performing a memory self-check on the baseboard management controller to determine whether there is a hardware error in the memory includes: During the process of the baseboard management controller performing the memory self-test, monitoring whether the level of the general input / output port on the preset programmable logic device is a high level; When the level of the general input / output port is high, it is determined that there is no hardware error in the memory; When the level of the general input / output port is low, it is determined that a hardware error exists in the memory.

4. The memory monitoring method according to claim 1, characterized in that: When a hardware error is detected in the memory, a hardware interrupt is triggered by a preset programmable logic device to wake up the microcontroller unit and put it into working state, including: When a hardware error is detected in the memory, a hardware interrupt is triggered through a preset programmable logic device, and a wake-up signal is sent to the microcontroller unit; If the current state of the micro control unit is a low power consumption mode state, the low power consumption mode state of the micro control unit is changed to a normal working state based on the wake-up signal.

5. The memory monitoring method according to any one of claims 1 to 4, characterized in that: The microcontroller unit after wake-up performs error type analysis on the error data, and sends an error handling request triggered by the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains a corresponding error handling result, including: Performing error type analysis on the error data based on the awakened microcontroller unit to analyze the error type; the error type includes recoverable error and unrecoverable error; If the error type is a recoverable error, the awakened microcontroller unit and the hardware management interface are used to trigger a corresponding memory page isolation processing request, and the memory page isolation processing request is sent to the operating system of the preset target component, so that the operating system uses memory management technology and performs memory page offline and isolation operations on itself based on the memory page isolation processing request to obtain a corresponding error processing result; If the error type is an irrecoverable error, the awakened microcontroller unit and the hardware management interface are used to trigger a corresponding memory mirror backup processing request, and the memory mirror backup processing request is sent to the operating system of the preset target component, so that the operating system can mirror the data corresponding to the processing request from the main memory module to the backup memory module based on the memory mirror backup processing request to obtain a corresponding error processing result.

6. The memory monitoring method according to claim 5, characterized in that: Also includes: Obtaining the error processing result from the operating system of the preset target component through the awakened micro control unit; The baseboard management controller is used to obtain the error processing result and the corresponding error record from the awakened micro control unit, and the error processing result and the error record are saved in a preset shared memory, and the error record is sent to a preset remote server.

7. A memory monitoring device, characterized in that: include: A monitoring module, used for hardware error monitoring of memory; The state wake-up module is used to trigger a hardware interrupt through a preset programmable logic device to wake up the microcontroller unit and put it into working state when a hardware error is detected in the memory; An error data sending module, used for acquiring error data related to the hardware error in a preset target component by using a baseboard management controller, and sending the error data to the awakened micro control unit; A processing module is used to perform error type analysis on the error data based on the microcontroller unit after being awakened, and send an error handling request triggered based on the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains a corresponding error handling result.

8. A device system, characterized in that: It includes a preset programmable logic device, a baseboard management controller and a micro control unit; wherein, The preset programmable logic device is used to monitor the memory for hardware errors and wake up the micro control unit to enter a working state; The baseboard management controller is used to obtain error data related to hardware errors in a preset target component and send the error data to the awakened micro control unit; The micro control unit is used to perform error type analysis on the error data after being awakened, and send an error handling request triggered based on the error type analysis result to the operating system of the preset target component, so that the operating system responds to the error handling request and obtains a corresponding error handling result.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the memory monitoring method as claimed in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the memory monitoring method according to any one of claims 1 to 6 are implemented.

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