Multi-functional logic coprocessor parallel test system based on tree topology structure

Abstract

The invention discloses a tree topology structure-based multi-functional logic coprocessor parallel test system, which comprises a master control node used for managing and distributing test tasks and receiving and summarizing test results returned by each coprocessor; the first-stage branch node is in communication connection with the main control node and is used for receiving the task from the main control node and executing corresponding test operation or further distributing the task to the second-stage branch node; the second-stage branch node is in communication connection with the first-stage branch node and is used for receiving the task from the first-stage branch node and executing corresponding test operation; the tested piece is a tested target device or system, is connected with the secondary branch node and is used for receiving the test instruction and returning test data; the nodes of each level are connected and managed through a tree topology structure to form a multi-level communication network, data transmission and task coordination are carried out among the nodes through a preset communication protocol, and parallel execution of test tasks and feedback of test results are realized.

Description

Technical Field

[0001] The invention relates to the field of automated testing, in particular to a multifunctional logic coprocessor parallel testing system based on a tree topology structure. Background Art

[0002] In modern test systems, parallel testing is often used to improve test efficiency and resource utilization. However, there are some problems and shortcomings in traditional parallel testing methods, the most prominent of which include data competition and resource limitations.

[0003] Data race is one of the common problems in parallel computing. When multiple parallel tasks read and write shared data at the same time, inconsistent data or wrong results may occur. Such race conditions may cause program crashes, deadlocks, or produce unpredictable results. For example, in a test system, if multiple test tasks access and modify shared data resources at the same time, data race may occur, resulting in inaccurate test results or test task failures.

[0004] Resource limitation refers to the difficulty in task scheduling and execution in a parallel test system due to limited hardware resources. For example, when the number of parallel tasks exceeds the number of processor cores available in the system, it may cause problems in task scheduling and load balancing. In addition, resource limitations such as memory, bandwidth, and storage may also affect the performance and scalability of parallel computing. For example, if the system does not have enough memory resources, it may not be able to run multiple test tasks at the same time, thus affecting test efficiency.

[0005] In the process of test system design, with the increase of complexity and performance requirements of the tested system, the traditional single-threaded testing method can no longer meet the requirements of efficient and accurate testing. The existing technical solution to this problem is to use multi-threaded parallel testing.

[0006] With the development of computer hardware architecture, multi-core processor systems have become increasingly popular, and the computing and storage capabilities of computers have been greatly improved. This provides hardware resource support for parallel testing, making it possible to execute more test tasks simultaneously, and multi-threading technology has been widely used in parallel testing.

[0007] In parallel testing, multithreading technology can effectively improve test efficiency. Since test tasks have a certain degree of independence, they can be divided into multiple independent threads and run on different processor cores. This can not only reduce the execution time of test tasks, but also avoid the waiting time that may occur in single-threaded testing.

[0008] In addition, multithreading technology can also improve the resource utilization of test tasks. In a multi-core processor system, different processor cores may have different processing capabilities. If test tasks are allocated according to processing capabilities, full utilization of test resources can be achieved, thereby improving overall test efficiency.

[0009] Although parallel testing technology based on multi-threading technology can improve test efficiency and resource utilization, it still has the following shortcomings that need to be solved urgently:

[0010] Reliability and accuracy of test results: Multiple threads in parallel testing may execute test cases at the same time, which may lead to unreliable or inaccurate test results. For example, if multiple threads write to a database or shared resources at the same time, conflicting or inconsistent results may occur. Therefore, measures need to be taken to ensure the reliability and accuracy of test results, such as proper control and management of access to shared resources.

[0011] Requirements on system resources: Parallel testing requires more system resources, such as CPU, memory, and disk space, to meet the needs of multi-threaded concurrent execution. This may lead to increased testing costs and may limit the possibility of performing parallel testing in resource-limited environments. Summary of the invention

[0012] The present invention proposes a solution to the above disadvantages. First, a tree topology structure is used to divide and expand the test tasks. The tree topology structure can clearly represent the hierarchical relationship and dependency relationship between the test tasks, so as to better manage and execute the test tasks.

[0013] Secondly, the multifunctional coprocessor can perform a variety of different types of test subtasks, which can be assigned to different coprocessors and executed in parallel. In this way, test tasks can be performed simultaneously instead of sequentially, which greatly shortens the test cycle. At the same time, the use of multifunctional coprocessors can reduce the resource pressure of the main control computer. The main control computer is usually responsible for coordinating and managing the test process, including task allocation, progress monitoring, and result aggregation. By assigning some test subtasks to coprocessors for execution, the main control computer can free up some computing resources and bandwidth, so as to better focus on test management and scheduling.

[0014] In the tree topology, test tasks are divided into different levels, each level contains a group of related test tasks. This structure can effectively divert and manage test tasks and improve test efficiency and quality.

[0015] Based on this, the present invention provides a multifunctional logic coprocessor parallel testing system based on a tree topology structure. The technical solution of the present invention is:

[0016] A multifunctional logic coprocessor parallel testing system based on a tree topology structure, the system comprising:

[0017] Master control node: used to manage and allocate test tasks, receive and summarize the test results returned by each coprocessor;

[0018] Level 1 branch node: connected to the master control node for receiving tasks from the master control node and performing corresponding test operations or further assigning tasks to level 2 branch nodes;

[0019] Secondary branch node: connected to the primary branch node for communication, used to receive tasks from the primary branch node and perform corresponding test operations;

[0020] DUT: The target device or system under test, connected to the secondary branch node, is used to receive test instructions and return test data;

[0021] Among them, the main control node, first-level branch nodes and second-level branch nodes are connected and managed through a tree topology structure to form a multi-level communication network. Data transmission and task coordination are carried out between each node through a preset communication protocol to achieve parallel execution of test tasks and feedback of test results.

[0022] The master control node includes:

[0023] Task allocation module: used to allocate test tasks to first-level branch nodes;

[0024] Result summary module: used to receive and summarize the test results returned by the first-level branch nodes and the second-level branch nodes.

[0025] The first-level branch node is a coprocessor composed of FPGA, has logic judgment and instruction control functions, is used to execute test tasks, and communicates with the main control node through a high-speed bus;

[0026] The first-level branch node includes:

[0027] Main task receiving module: used to receive the test tasks assigned by the master control node;

[0028] Logical judgment module: used to perform logical judgment on test tasks and generate corresponding control instructions;

[0029] Instruction control module: used to receive and execute control instructions and generate test results;

[0030] Data transmission module: used to transmit test data and control instructions, and transmit test results to the main control node.

[0031] The secondary branch node is a coprocessor composed of DSP, which has logic judgment and instruction control functions, is used to perform corresponding control according to the test task sent by the primary branch node, and is connected to the primary branch node through RS422 communication;

[0032] The secondary branch node includes:

[0033] Task receiving module: used to receive test tasks assigned by the first-level branch node;

[0034] Logical judgment module: used to perform logical judgment on test tasks and generate corresponding control instructions;

[0035] Instruction control module: used to receive and execute control instructions and generate test results;

[0036] Data processing module: used for preliminary processing and screening of test data;

[0037] Data transmission module: used to transmit test data and control instructions, and transmit test results to the first-level branch node.

[0038] The device under test interacts with the secondary branch node for data, and the communication method includes: serial port communication.

[0039] The tree topology communication network includes a root node and multiple branch nodes; the root node is a main control node, responsible for coordinating and allocating test tasks to each branch node; the branch nodes communicate with each other through a tree structure, share test data and test results, and return the test results to the main control node.

[0040] The system further comprises:

[0041] Task scheduling module: used to allocate test tasks to coprocessors of different levels according to the priority and resource requirements of the test tasks;

[0042] Data management module: used to manage and store test data, analyze test results, and generate test reports.

[0043] The test results include data collected during the test, the execution status of the test cases, and test error information.

[0044] The test report includes the test status of each branch node, the overall test progress and conclusion.

[0045] The present invention also discloses a multifunctional logic coprocessor parallel testing method based on a tree topology structure, which is implemented by the multifunctional logic coprocessor parallel testing system described above, and includes the following steps:

[0046] Loading a multifunctional logic coprocessor parallel test system, the multifunctional logic coprocessor parallel test system has a plurality of first-level branch nodes, each first-level branch node includes a plurality of second-level branch nodes, each second-level branch node is connected to a first-level branch node of an upper level and a plurality of devices under test of a lower level:

[0047] Allocating a test task to each branch node, each test task including a test on the device under test;

[0048] Through the control instructions of branch nodes at all levels, parallel control of multiple DUTs is performed;

[0049] When executing the test, mark the test results of each branch node;

[0050] Analyze test results and generate test reports.

[0051] Compared with the traditional multi-threaded parallel testing technology, the present invention has the following advantages:

[0052] 1. A hierarchical communication network system management method based on a tree topology structure efficiently manages and coordinates the communication and task allocation between multiple logical coprocessors, fully utilizes the system's hardware resources, achieves efficient communication and secure data sharing, and thus reduces the possibility of data competition and resource limitations.

[0053] Efficient communication: The tree topology connects branch nodes to the master node to form a hierarchical communication network. This structure can avoid the resource limitation problem caused by the lack of mature management methods in traditional parallel testing technology.

[0054] Secure data sharing: Branch nodes in the tree topology can share data through the master node. The master node can assign test tasks to the first-level branch nodes and pass the test results back to the master node. The first-level branch node can pass tasks and results to the second-level branch node to achieve data sharing and transmission and avoid data competition during the test process.

[0055] 2. Multifunctional logic coprocessors can improve execution efficiency and system flexibility.

[0056] Compared with single-function coprocessors, multi-function logic coprocessors have the following advantages:

[0057] Execution efficiency: Multifunctional logic coprocessors can handle multiple tasks such as logic judgment, instruction control, and data transmission at the same time, while single-function coprocessors can only perform specific functions. This means that in test tasks, multifunctional logic coprocessors can complete multiple operations more efficiently, improving the execution speed and efficiency of test tasks.

[0058] Flexibility: The multifunctional logic coprocessor has flexible configuration and programming capabilities and can be customized and adjusted according to the requirements of the test task. By programming and configuring the multifunctional logic coprocessor, different logic judgment and instruction control functions can be realized to adapt to different test requirements. This flexibility enables the test system to better adapt to different types of DUTs and test tasks.

[0059] Comprehensive performance: The multifunctional logic coprocessor has higher comprehensive performance. It can handle multiple tasks at the same time, reducing the switching and communication overhead between tasks, and improving the overall test system performance. In addition, the multifunctional logic coprocessor can work with other components (such as master nodes and branch nodes) to form an efficient test system, further improving the execution efficiency and performance of test tasks.

[0060] 3. The combined use of parallel task management of the tree topology structure and multi-functional coprocessor technology gives the system technical advantages such as clear hierarchical structure, strong scalability, and load balancing.

[0061] Clear hierarchy: The tree topology has a clear hierarchy, which can intuitively display the nodes and connection relationships in the network. This makes network management and maintenance more convenient and enables quick location and resolution of network faults.

[0062] Strong scalability: The tree topology can be easily expanded and upgraded. When the network scale expands or the performance requirements increase, nodes or branches can be simply added to meet the changing test requirements.

[0063] Load balancing: Through parallel task management and multi-function coprocessor technology, test tasks can be assigned to multiple nodes and coprocessors for simultaneous execution. This allows the network load to be balanced, avoiding overloading of some nodes or coprocessors, thereby improving the test efficiency of the entire network. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 This is a structural diagram of the multifunctional logic coprocessor parallel test system of the present invention.

[0065] Figure 2 The present invention is a flowchart of the steps of the multi-function logic coprocessor parallel testing method. DETAILED DESCRIPTION

[0066] The following is a detailed description of the embodiments of the present invention in conjunction with the accompanying drawings:

[0067] The present invention provides a multifunctional logic coprocessor parallel test system based on a tree topology structure, and its system architecture is as follows: Figure 1 The system includes:

[0068] (1) Master control node: The master control node is the core of the entire test system. It is used to manage and allocate test tasks and receive and summarize the test results returned by each coprocessor. The master control node includes:

[0069] Task allocation module: used to allocate test tasks to first-level branch nodes;

[0070] Result summary module: used to receive and summarize the test results returned by the first-level branch nodes and the second-level branch nodes.

[0071] The master control node has high reliability and powerful data processing capabilities. It can process a large amount of test data in a short time and ensure the stability and accuracy of the test process.

[0072] (2) Level 1 branch node: The level 1 branch node is connected to the master control node. The level 1 branch node is used to receive tasks from the master control node and perform corresponding test operations or further assign tasks to the level 2 branch node.

[0073] The first-level branch nodes include:

[0074] Main task receiving module: used to receive the test tasks assigned by the master control node;

[0075] Logical judgment module: used to perform logical judgment on test tasks and generate corresponding control instructions;

[0076] Instruction control module: used to accept and execute instruction control and generate test results;

[0077] Data transmission module: used to transmit test data and control instructions, and transmit test results to the main control node.

[0078] The first-level branch node is a coprocessor composed of FPGA, which has logic judgment and instruction control functions, is used to execute test tasks, and communicates with the main control node through a high-speed bus, ensuring high-speed and reliable communication. The first-level branch node is implemented with FPGA, which has high logic flexibility and real-time processing capabilities, can quickly respond to changes in test tasks, and make real-time adjustments, thereby improving test efficiency and the reliability of test results.

[0079] (3) Secondary branch node: The secondary branch node is the terminal node connecting the primary branch node and the device under test. It is responsible for receiving the test tasks assigned by the primary branch node and performing more fine-grained control operations.

[0080] Secondary branch nodes include:

[0081] Task receiving module: used to receive test tasks assigned by the first-level branch node;

[0082] Logical judgment module: used to perform logical judgment on test tasks and generate corresponding control instructions;

[0083] Instruction control module: used to receive and execute control instructions and generate test results;

[0084] Data processing module: used for preliminary processing and screening of test data;

[0085] Data transmission module: used to transmit test data and control instructions, and transmit test results to the first-level branch node.

[0086] The secondary branch node is a coprocessor composed of DSP, which has logic judgment and instruction control functions. It is used to perform corresponding control according to the test tasks sent by the primary branch node, and is connected to the primary branch node through RS422 communication. This communication method is suitable for long-distance and multi-point communication. The secondary branch node is implemented with DSP, which can quickly process and filter the test data, reduce the data processing pressure of the upper node, and improve the accuracy and reliability of the test data.

[0087] (4) DUT: The DUT is the target device or system being tested, which interacts with the secondary branch node through serial communication. This communication method is suitable for short-distance and low-speed communication to perform specific test operations.

[0088] The multifunctional logic coprocessor parallel test system of the present invention also includes:

[0089] Task scheduling module: used to allocate test tasks to coprocessors of different levels according to the priority and resource requirements of the test tasks;

[0090] Data management module: used to manage and store test data, analyze test results and generate reports. Test results include data collected during the test, test case execution and test error information. Test reports include test conditions of each branch node, overall test progress and conclusions.

[0091] The above-mentioned main control node, first-level branch node and second-level branch node are connected and managed through a tree topology structure to form a multi-level communication network. The nodes transmit data and coordinate tasks through a preset communication protocol to achieve parallel execution of test tasks and feedback of test results.

[0092] The tree topology is a hierarchical structure consisting of a root node and multiple branch nodes, similar to the shape of a tree. In this test system, the tree topology is used to connect and manage multiple logical coprocessors:

[0093] The master node is the root node, responsible for coordinating and assigning test tasks to each branch node; the first-level branch node is the first-level branch node, which receives tasks from the master node and performs corresponding test operations or further assigns tasks to the second-level branch node; the second-level branch node is the second-level branch node, which receives tasks from the first-level branch node and performs corresponding test operations; the tree topology also includes at least one additional layer of branch nodes, which is used to further subdivide test tasks and improve test efficiency and resource utilization. Each node has a unique identifier to distinguish and manage each node.

[0094] The hierarchical management method of the tree topology ensures the orderly allocation and efficient execution of test tasks, avoids the problems of data competition and resource limitation, and significantly improves the overall test efficiency and reliability of the system. The master node assigns the test tasks to the branch nodes in the tree structure. After receiving the tasks, the branch nodes perform the corresponding test operations according to the task requirements. The branch nodes can communicate with each other through the tree structure to share test data and results. The branch nodes return the test results to the master node, which summarizes and analyzes the received results and finally generates a test report. The hierarchical task management and feedback mechanism ensures the efficient execution of test tasks and the accurate summary of results, significantly improving the accuracy and reliability of the test.

[0095] The tree topology can better allocate hardware resources and system resources by dividing the test tasks into different levels. For example, the automated test of the bottom-level tasks can be performed separately from the detailed test of the high-level tasks. The task scheduling module and data management module in the system are used to manage and coordinate the communication and task allocation between multiple logical coprocessors. The resource management and optimization mechanism ensures the efficient use of system resources, avoids resource waste and task scheduling bottlenecks, and improves the overall test efficiency and performance of the system.

[0096] The present invention adopts CAN bus and RS422 communication protocols, which can ensure the real-time and reliability of test tasks and test results transmission, and has strong anti-interference ability, which is suitable for test requirements in complex electromagnetic environments. The use of different communication protocols ensures efficient communication and data transmission between nodes at all levels, significantly improving the communication reliability and test efficiency of the system.

[0097] The present invention also provides a multifunctional logic coprocessor parallel testing method based on a tree topology structure, such as Figure 2 As shown, the following steps are included:

[0098] Loading a multifunctional logic coprocessor parallel test system, the multifunctional logic coprocessor parallel test system having a plurality of first-level branch nodes, each first-level branch node including a plurality of second-level branch nodes, each second-level branch node connected to a first-level branch node of an upper level and a plurality of DUTs of a lower level;

[0099] Assigning a test task to each branch node, each test task including a test on a device under test, the device under test including, for example, a sensor, an actuator or other automation equipment;

[0100] Through the control instructions of multi-level branch nodes, parallel control of multiple devices is performed to improve test efficiency;

[0101] When executing the test, the test results of each branch node are marked to display important information during the test process; during implementation, the control network can be adjusted and optimized according to the test results to achieve more efficient test task allocation and control;

[0102] Analyze test results and generate test reports.

[0103] The present invention provides a multifunctional logic coprocessor parallel testing system and method based on a tree topology structure:

[0104] (1) By using a tree topology, the communication and task allocation between multiple logical coprocessors can be effectively managed and coordinated, and the system's hardware resources can be fully utilized, thereby reducing the possibility of data competition and resource limitations, achieving efficient communication and data sharing between branch nodes, and achieving efficient execution of parallel computing and test tasks, thereby improving system performance and efficiency. In addition, the tree topology also has good scalability, and more branch nodes can be added as needed to expand the system's capabilities.

[0105] Specifically, the tree topology can be used in the following aspects:

[0106] Dividing test tasks: By dividing test tasks into different levels, the tree topology can decompose a large number of test tasks into smaller and more manageable subtasks. Test tasks at each level can be assigned to different coprocessors to better coordinate and manage test work.

[0107] Test result location: The tree topology can clearly represent the hierarchical relationship of the test tasks, thereby identifying and locating the test scope. For example, when a test task fails, you can trace it by branch according to the tree structure to quickly locate the branch and level where the test error occurred.

[0108] Resource management and optimization: The tree topology can better manage and optimize resources. By dividing the test tasks into different levels, hardware resources and system resources can be better allocated. For example, the automated testing of low-level tasks can be performed separately from the detailed testing of high-level tasks to better utilize system resources and time.

[0109] (2) By using a multifunctional logic coprocessor, logic judgment, instruction control and data transmission functions can be realized. Compared with a single-function coprocessor, a multifunctional logic coprocessor can improve the execution efficiency and flexibility of test tasks. This coprocessor can effectively handle various test tasks, including but not limited to logic judgment, instruction control and data transmission of data. When processing test tasks, the multifunctional logic coprocessor can automatically identify the type of task to be executed and complete the task quickly and accurately, thereby improving the execution efficiency and flexibility of test tasks.

[0110] In the tree topology, a multifunctional coprocessor is used to cooperate with the main control computer to decompose and execute the test tasks. Since the coprocessor can execute test subtasks in parallel, the test can be completed more quickly and more test data can be collected in a shorter time. This helps to reduce the impact of test errors and uncertainties, thereby improving the accuracy and reliability of the test.

[0111] In addition, the use of multifunctional coprocessors can also improve the scalability and flexibility of the system. Since the coprocessor can perform many different types of test subtasks, the coprocessor can be added or removed as needed to adapt to different test requirements and scenarios. This allows the system to be expanded or reduced according to actual needs, thereby improving the scalability and flexibility of the system. Therefore, in actual applications, the appropriate coprocessor should be selected according to specific needs and scenarios to achieve efficient testing and management.

Claims

1. A multifunctional logic coprocessor parallel test system based on a tree topology structure, characterized in that: The system comprises: Master control node: used to manage and allocate test tasks, receive and summarize the test results returned by each coprocessor; Level 1 branch node: connected to the master control node for receiving tasks from the master control node and performing corresponding test operations or further assigning tasks to level 2 branch nodes; Secondary branch node: connected to the primary branch node for communication, used to receive tasks from the primary branch node and perform corresponding test operations; DUT: The target device or system under test, connected to the secondary branch node, is used to receive test instructions and return test data; Among them, the main control node, first-level branch nodes and second-level branch nodes are connected and managed through a tree topology structure to form a multi-level communication network. Data transmission and task coordination are carried out between the nodes through a preset communication protocol to achieve parallel execution of test tasks and feedback of test results.

2. The multifunctional logic coprocessor parallel testing system according to claim 1, characterized in that: The master control node includes: Task allocation module: used to allocate test tasks to first-level branch nodes; Result summary module: used to receive and summarize the test results returned by the first-level branch nodes and the second-level branch nodes.

3. The multifunctional logic coprocessor parallel testing system according to claim 1, characterized in that: The first-level branch node is a coprocessor composed of FPGA, has logic judgment and instruction control functions, is used to execute test tasks, and communicates with the main control node through a high-speed bus; The first-level branch node includes: Main task receiving module: used to receive the test tasks assigned by the master control node; Logical judgment module: used to perform logical judgment on test tasks and generate corresponding control instructions; Instruction control module: used to receive and execute control instructions and generate test results; Data transmission module: used to transmit test data and control instructions, and transmit test results to the main control node.

4. The multifunctional logic coprocessor parallel testing system according to claim 1, characterized in that: The secondary branch node is a coprocessor composed of DSP, which has logic judgment and instruction control functions, is used to perform corresponding control according to the test task sent by the primary branch node, and is connected to the primary branch node through RS422 communication; The secondary branch node includes: Task receiving module: used to receive test tasks assigned by the first-level branch node; Logical judgment module: used to perform logical judgment on test tasks and generate corresponding control instructions; Instruction control module: used to receive and execute control instructions and generate test results; Data processing module: used for preliminary processing and screening of test data; Data transmission module: used to transmit test data and control instructions, and transmit test results to the first-level branch node.

5. The multifunctional logic coprocessor parallel testing system according to claim 1, characterized in that: The device under test exchanges data with the secondary branch node, and the communication method includes: serial port communication.

6. The multifunctional logic coprocessor parallel testing system according to claim 1, characterized in that: The tree topology communication network includes a root node and multiple branch nodes; the root node is a main control node, responsible for coordinating and allocating test tasks to each branch node; Branch nodes communicate with each other through a tree structure, share test data and test results, and return the test results to the main control node.

7. The multifunctional logic coprocessor parallel testing system according to claim 1, characterized in that: The system further comprises: Task scheduling module: used to allocate test tasks to coprocessors of different levels according to the priority and resource requirements of the test tasks; Data management module: used to manage and store test data, analyze test results, and generate test reports.

8. The multifunctional logic coprocessor parallel testing system according to claim 1, characterized in that: The test results include data collected during the test, the execution status of the test cases, and test error information.

9. The multifunctional logic coprocessor parallel testing system according to claim 7, characterized in that: The test report includes the test status of each branch node, the overall test progress and conclusion.

10. A multifunctional logic coprocessor parallel testing method based on a tree topology structure, implemented by the multifunctional logic coprocessor parallel testing system according to claims 1 to 9, comprising the following steps: Loading a multifunctional logic coprocessor parallel test system, the multifunctional logic coprocessor parallel test system having a plurality of first-level branch nodes, each first-level branch node including a plurality of second-level branch nodes, each second-level branch node connected to a first-level branch node of an upper level and a plurality of DUTs of a lower level; Allocating a test task to each branch node, each test task including a test on the device under test; Through the control instructions of branch nodes at all levels, parallel control of multiple DUTs is performed; When executing the test, mark the test results of each branch node; Analyze test results and generate test reports.

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