Graphic processor interconnection structure and data transmission method

Abstract

The invention provides a graphics processor interconnection structure and a data transmission method, and relates to the technical field of intelligent computing, the graphics processor interconnection structure comprises a plurality of graphics processors and at least one switching device group, each switching device group comprises a plurality of switching devices, the plurality of switching devices in each switching device group comprise switching devices of a first level and switching devices of a second level; wherein each graphics processor is connected with any switching device in each switching device group, and the switching device of the first level in each switching device group is connected with the switching device of the second level; the sum of the number of the switching devices connected with any switching device in each switching device group and the number of the graphics processors is smaller than or equal to the number of ports of the corresponding switching device. According to the structure, interconnection between large-scale graphics processors is realized.

Description

Technical Field

[0001] The present application relates to the field of intelligent computing technology, and in particular to a graphics processor interconnection structure and a data transmission method. Background Art

[0002] As the complexity of computing tasks increases, a single graphics processing unit (GPU) may not be able to complete the computing task, and multiple graphics processing units (GPUs) need to be interconnected to complete the computing task together.

[0003] The graphics processor interconnection method may include direct connection of the graphics processor or interconnection through a switching device. Direct connection of the graphics processor will limit the performance of the graphics processor, while in the method of interconnection through a switching device, each port of a switching device is connected to a graphics processor. Therefore, the method of interconnection through a switching device is limited by the number of ports of the switching device. The number of interconnected graphics processors must be less than or equal to the number of ports of the switching device. This method cannot achieve large-scale interconnection between graphics processors. Summary of the invention

[0004] The present application provides a graphics processor interconnection structure and a data transmission method, which are used to solve the technical problem that large-scale interconnection between graphics processors cannot be achieved.

[0005] In a first aspect, the present application provides a graphics processor interconnection structure, comprising a plurality of graphics processors, at least one switching device group, each switching device group comprising a plurality of switching devices, and the plurality of switching devices in each switching device group comprising a first-level switching device and a second-level switching device; wherein,

[0006] Each graphics processor is connected to any switching device in each switching device group, and the first-level switching device in each switching device group is connected to the second-level switching device;

[0007] The sum of the number of switching devices connected to any switching device in each switching device group and the number of graphics processors is less than or equal to the number of ports of the corresponding switching device.

[0008] Optionally, the number of the switching device groups is less than or equal to the number of ports of the graphics processor.

[0009] Optionally, each graphics processor is connected to any switching device in each switching device group via one link, and a first-level switching device in at least one switching device group is connected to a second-level switching device via two links;

[0010] The sum of the number of links connected to any switching device in each switching device group and the number of links connected to the image processor is less than or equal to the number of ports of the corresponding switching device.

[0011] Optionally, the multiple graphics processors include third-level graphics processors and fourth-level graphics processors, the third-level graphics processors are connected to the first-level switching devices in each switching device group, and the fourth-level graphics processors are connected to the second-level switching devices in each switching device group.

[0012] Optionally, in each switching device group, the number of switching devices at the first level is the same as the number of switching devices at the second level.

[0013] Optionally, the number of graphics processors at the third level is the same as the number of graphics processors at the fourth level.

[0014] Optionally, the first-level switching device is divided into a first part of switching devices and a second part of switching devices, the third-level graphics processor is divided into a first part of graphics processors and a second part of graphics processors, the first part of graphics processors is interconnected with the first part of switching devices, and the second part of graphics processors is interconnected with the second part of switching devices;

[0015] The second-level switching device is divided into a third-part switching device and a fourth-part switching device, and the fourth-level graphics processor is divided into a third-part graphics processor and a fourth-part graphics processor. The third-part graphics processor is interconnected with the third-part switching device, and the fourth-part graphics processor is interconnected with the fourth-part switching device.

[0016] Optionally, the first-level switching devices in each switching device group are connected to the second-level switching devices via links, and at least one link connecting the first-level switching devices in each switching device group and the second-level switching devices includes a first virtual channel and a second virtual channel.

[0017] In a second aspect, a data transmission method is provided, which is applied to a first switching device, wherein the first switching device is any switching device in a graphics processor interconnect structure, and the graphics processor interconnect structure is the graphics processor interconnect structure as described in the first aspect; the method comprises:

[0018] If the destination address of the data to be transmitted is the address of a graphics processor connected to the first switching device, sending the data to be transmitted to the graphics processor corresponding to the destination address;

[0019] If the destination address of the data to be transmitted is not the address of the graphics processor connected to the first switching device, determining whether the switching device connected to the graphics processor corresponding to the destination address is located at the same level as the first switching device;

[0020] If the switching device connected to the graphics processor corresponding to the destination address is at the same level as the first switching device, sending the data to be transmitted to the switching device connected to the first switching device;

[0021] If the switching device connected to the graphics processor corresponding to the destination address is not located at the same level as the first switching device, the data to be transmitted is sent to the switching device connected to the graphics processor corresponding to the destination address.

[0022] Optionally, a link connecting a first-level switching device in each switching device group and a second-level switching device includes a first virtual channel and a second virtual channel; and sending the data to be transmitted to a switching device connected to the first switching device includes:

[0023] Sending the data to be transmitted to a switching device connected to the first switching device through the first virtual channel;

[0024] The step of sending the data to be transmitted to a switching device connected to a graphics processor corresponding to the destination address includes:

[0025] If the graphics processor that sends the data to be transmitted is connected to the first switching device, sending the data to be transmitted to the switching device connected to the graphics processor corresponding to the destination address through the first virtual channel;

[0026] If the graphics processor that sends the data to be transmitted is connected to the first switching device, the data to be transmitted is sent to the switching device connected to the graphics processor corresponding to the destination address through the second virtual channel.

[0027] The graphics processor interconnection structure and data transmission method provided by the present application replace the switching device by a switching device group, and the switching device group is provided with multiple switching devices, and the switching devices at different levels are connected. In this way, multiple graphics processors are connected by a switching device group including multiple switching device groups, and the graphics processor can be connected to any switching device in the switching device group. In this way, the number of graphics processor interconnections will not be limited to the number of ports of a single switching device. At the same time, the connection between the switching devices at different levels in the switching device group can realize data transmission between graphics processors connected to different switching devices in the switching device group. This structure can improve the scale of image processor interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0029] Figure 1 A structural diagram of a sacle-up network shown as an exemplary embodiment of the present application;

[0030] Figure 2 A structural diagram of a graphics processor interconnection structure shown as an exemplary embodiment of the present application;

[0031] Figure 3 A structural diagram of a graphics processor interconnection structure shown as another exemplary embodiment of the present application;

[0032] Figure 4 A structural diagram of a sacle-up network shown in another exemplary embodiment of the present application;

[0033] Figure 5 A structural diagram of a graphics processor interconnection structure shown as another exemplary embodiment of the present application;

[0034] Figure 6 A data transmission link diagram in a switching device group shown as an exemplary embodiment of the present application;

[0035] Figure 7 The present invention is a flowchart of a data transmission method according to an exemplary embodiment of the present invention.

[0036] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0037] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0038] The following is an explanation of the relevant majors:

[0039] Deadlock: A situation where multiple paths in the network are dependent on each other and form a loop, making communication impossible.

[0040] Scale-up network: A network that directly interconnects GPUs.

[0041] There are two ways of sacle-up network connection. One is direct connection between GPUs, and the other is interconnection between GPUs through a switch (switching device). The structure in which GPUs are interconnected through a switch has better performance than the structure in which GPUs are directly connected.

[0042] The structure of GPU interconnection through switches is limited by the number of switch ports. In a server-up network, there can be at most a number of GPUs interconnected that corresponds to the number of switch ports, such as Figure 1 As shown, a general switch has 8 ports, so at most 8 GPUs can be interconnected through the switch, and it is impossible to connect to a larger GPU.

[0043] With the development of large models, the demand for scale-up is getting stronger and stronger. For example, a structure that interconnects 16 GPUs is required, but due to the limitation of the number of switch ports, it is impossible to connect to the interconnection between 16 GPUs. Some methods use fat tree topology to expand to connect large-scale GPUs, but the fat tree topology generally requires 3 layers of fat trees, which consumes too many switches, bringing a series of problems such as cost, hardware complexity, and reliability.

[0044] In other ways, in order to increase the number of GPU interconnections, switches with more ports can be developed, but more ports on the switch means higher costs, lower yields, and higher process levels.

[0045] Based on this, the present application proposes a graphics processor interconnection structure and a data transmission method, which can realize large-scale interconnection between graphics processors.

[0046] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0047] refer to Figure 2 and Figure 3 , providing a graphics processor interconnection structure, including multiple graphics processors, at least one switching device group, each switching device group includes multiple switching devices, and the multiple switching devices in each switching device group include first-level switching devices and second-level switching devices; wherein,

[0048] Each graphics processor is connected to any switching device in each switching device group, and the first-level switching devices in each switching device group are connected to the second-level switching devices.

[0049] The sum of the number of switching devices connected to any switching device in each switching device group and the number of graphics processors is less than or equal to the number of ports of the corresponding switching device.

[0050] In some embodiments, the switching device is a device that can perform data transmission, such as a switch or a switching chip. The switching device is used to transmit information between GPUs in a graphics processor interconnect structure.

[0051] In some embodiments, the number of switching device groups may be one or more, the switching devices in each switching device group may be divided into a first level and a second level, each switching device group includes first-level switching devices and second-level switching devices, the number of switching devices between each switching device group may be the same or different, the number of first-level switching devices in each switching device group may be the same or different, and the number of second-level switching devices in each switching device group may be the same or different.

[0052] In some embodiments, the number of switching devices at the first level and the number of switching devices at the second level in each switching device group are at least one.

[0053] In some embodiments, the first-level switching devices in each switching device group are connected to the second-level switching devices, and the switching devices can be connected through links via ports between the switching devices, such as a port of the first-level switching device is connected to a port of the first-level switching device via a link.

[0054] In some embodiments, there may be one or more links connecting the first-level switching device and the second-level switching device in each switching device group. Two switching devices connected by a link each occupy a port of the corresponding two switching devices. If there are two link connections between two switching devices, then there are two occupied ports in the two switching devices.

[0055] In some embodiments, the number of first-level switching devices and second-level switching devices in each switching device group may be the same or different.

[0056] In some embodiments, for graphics processors that can be connected to each switching device in a switching device group, the number of graphics processors that can be connected is less than the number of ports of the switching device minus the number of switching devices connected to the switching device.

[0057] For example, if there is a switching device in a switching device group, the number of ports of the switching device is 8, the switching device is located at the first level, and there are 2 switching devices at the second level, then the maximum number of image processors that can be connected to the switching device is 8-2, that is, the switching device can be connected to a maximum of 6 image processors.

[0058] It can be understood that in a switching device group, switching devices between different levels are connected through ports, and the switching devices and the image processor are also connected through ports. Therefore, for a switching device in the corresponding switching device group, the sum of the number of links used to connect to other switching devices and the number of links used to connect to the image processor should be less than or equal to the number of ports of the switching device.

[0059] Similarly, if the number of ports of a switching device is 8, the switching device is located at the first level, there are two switching devices at the second level, and there are two link connections between the switching device and the two switching devices at the second level, then the maximum number of image processors that can be connected to the switching device is 8-4, that is, the switching device can be connected to a maximum of 4 image processors.

[0060] Switching devices at the same level are not connected to each other, and two different switching device groups are not connected to each other. Multiple switching device groups can increase the transmission bandwidth between image processors.

[0061] Figure 2 and Figure 3 One switching device group is shown in the figure. In other embodiments, multiple switching device groups may be respectively connected to multiple image processors, that is, each image processor is respectively connected to any one switching device in each switching device group to improve the transmission bandwidth between multiple image processors.

[0062] like Figure 2 As shown, there are 3 switching devices in the switching device group, and the number of the first-level switching devices is 1. Figure 2 In the figure, it is marked as SW1. The number of switching devices at the second level is 2. Figure 2 They are respectively denoted as SW2-1 and SW2-2.

[0063] Figure 2 SW1 is connected to SW2-1 and to SW2-2, and SW1 and SW2-1 are connected via a link, SW1 and SW2-2 are connected via a link, and SW2-1 and SW2-2 are not connected.

[0064] It is assumed that SW1, SW2-1, and SW2-2 all have 8 ports. SW1 can connect to a maximum of 6 image processors, and SW2-1 and SW2-2 can connect to a maximum of 7 image processors.

[0065] like Figure 3As shown, there are 4 switching devices in the switching device group, and the number of switching devices at the first level is 2. Figure 3 In the figure, they are denoted as SW1-1 and SW1-2. The number of switching devices at the second level is 2. Figure 2 They are respectively denoted as SW2-1 and SW2-2.

[0066] Figure 3 , SW1 is connected to SW2-1 and to SW2-2, SW1-2 is connected to SW2-1 and to SW2-2, and SW1-1 and SW2-1 are connected via 2 links, SW1-1 and SW2-2 are connected via 2 links, SW2-1 and SW2-1 are connected via 2 links, SW2-1 and SW2-2 are connected via 2 links, SW2-1 and SW2-2 are not connected, and SW1-1 and SW1-2 are not connected.

[0067] It is assumed that SW1-1, SW2-1, and SW2-2 each have 8 ports, and SW1-1, SW1-2, SW2-1, and SW2-2 each can connect to a maximum of 4 image processors.

[0068] Figure 2 and Figure 3 In the figure, the graphics processor is represented by GPU, and GPU1, GPU2, etc. identify different GPUs.

[0069] For this switching device group, the number of image processors that can be connected is larger than the number of image processors connected to one switching device, and the number of switching devices used in the graphics processor interconnection structure is also much smaller than the number of switching devices required by the fat tree structure. Figure 3 The switching device group in the example can connect up to 16 image processors, while the fat-tree structure requires 6 switching devices. For the scenario where the transmission bandwidth between image processors needs to be improved, taking the example that each image processor can connect up to 7 switching devices, the fat-tree structure requires more switching devices, that is, 7*6=42 switching devices, while the use Figure 3 The switching device group in the , then 7*4=28 switching devices are needed, which can greatly reduce the number of switching devices, and can also achieve the scale of the graphics processor in the graphics processor interconnection structure.

[0070] At the same time, the GPU interconnection structure is also superior to the fat tree structure in terms of performance. Figure 1In the structure shown, there is a switching device between the two image processors. Data transmission between the two image processors requires one hop, i.e., one switching device. In the fat tree solution, data transmission between the two image processors requires three hops, i.e., three switching devices. In the graphics processor interconnection structure of the present application, data transmission between two image processors connected to the switching device at the same level requires three hops, i.e., three switching devices. Figure 3 In the example, if GPU1 transmits data to GPU2, the data must pass through SW1-1, SW2-1 or SW2-2, SW1-2; however, data transmission between two image processors connected by switching devices at different levels only requires two hops, that is, two switching devices. Figure 3 When GPU1 transmits data to GPU9, the data needs to pass through SW1-1 and SW2-1.

[0071] In an embodiment of the present application, a graphics processor interconnection structure is provided, in which a switching device is replaced by a switching device group, a plurality of switching devices are arranged in the switching device group, and switching devices at different levels are connected. Thus, a plurality of graphics processors are connected by a switching device group including a plurality of switching device groups, and the graphics processor can be connected to any switching device in the switching device group. Thus, the number of graphics processor interconnections is not limited to the number of ports of a single switching device. At the same time, the connection between switching devices at different levels in the switching device group can realize data transmission between graphics processors connected to different switching devices in the switching device group. This structure can improve the scale of graphics processor interconnections.

[0072] In some embodiments, the number of switch device groups is less than or equal to the number of ports of the graphics processor.

[0073] In some embodiments, in order to improve the transmission bandwidth between image processors, multiple switching devices may be provided, such as Figure 4 As shown, each image processor can be interconnected through a switching device, so that information exchange between image processors can be achieved through the multiple switching devices. For example, data transmission between two image processors can be achieved through the first switching device, and can also be achieved through the second switching device connected to it, thereby improving the bandwidth between image processors.

[0074] In the scenario where multiple switching devices are connected to the image processor, the number of switching devices generally does not exceed the number of ports on the image processor, such as Figure 4 In the example, the image processor has 7 ports, and each image processor can be connected to at most 7 switching devices to realize the interconnection between image processors.

[0075] In some embodiments, by replacing a switch device with a switch device group, the scale of interconnected graphics processors in a graphics processor interconnect structure can be greatly improved.

[0076] In one embodiment, a graphics processor is connected to any switching device in a switching device group, and the connection between the graphics processor and the switching device is realized through the port of the graphics processor and the port of the switching device. Thus, for the graphics processor, it can be connected to a maximum number of switching device groups equal to the number of ports of the graphics processor.

[0077] If Figure 3 For example, each graphics processor includes 7 ports, and the graphics processor interconnect structure may include at most 7 switching device groups, such as Figure 5 As shown, each image processing is connected to any switching device in the switching device group. Figure 5 The names of the switching devices in each switching device group are the same, but it can be understood that they are different switching device groups. Figure 5 The naming is for convenience.

[0078] In some embodiments, each graphics processor is connected to any switching device in each switching device group via one link, and a first-level switching device and a second-level switching device in at least one switching device group are connected via two links.

[0079] The sum of the number of links connected to any switching device in each switching device group and the number of links connected to the image processor is less than or equal to the number of ports of the corresponding switching device.

[0080] In some embodiments, switching devices at different levels can be connected via one link, two links, or three links. The link connecting a switching device to other switching devices needs to occupy one port. The number of links connected between switching devices at different levels corresponds to the number of ports occupied by each switching device. The more links connected between switching devices at different levels, the fewer image processors that can be connected to the corresponding switching device.

[0081] In some embodiments, the switching device includes multiple ports, the switching device is connected to other switching devices through one port to form a link, and each switching device is connected to the image processor through one port to form a link.

[0082] In some embodiments, a first-level switching device in at least one switching device group is connected to a second-level switching device through two links. For the corresponding first-level or second-level switching device, the number of remaining ports is the number of ports of the switching device minus the number of links connected to other switching devices. For example, if the number of ports of the switching device is 8, the number of remaining ports is 6.

[0083] In some embodiments, each graphics processor is connected to any switching device in each switching device group via a link, and one graphics processor occupies one port in the switching device. Therefore, the number of ports of the switching device minus the number of links connected to other switching devices is the number of graphics processors that can be connected to the switching device, that is, the number of links that can be connected to the image processors.

[0084] In some embodiments, if there is a link between other switching devices or image processors to which the switching device is connected, a port of the switching device is occupied. Thus, the sum of the number of links connected to any switching device in each switching device group and the number of links connected to the image processor is less than or equal to the number of ports of the corresponding switching device.

[0085] The bandwidth of data transmission can be improved by increasing the number of links between switching devices at different levels.

[0086] In some embodiments, the multiple graphics processors include a third-level graphics processor and a fourth-level graphics processor, the third-level graphics processor is connected to the first-level switching device in each switching device group, and the fourth-level graphics processor is connected to the second-level switching device in each switching device group.

[0087] In some embodiments, the image processors may be divided into a third level and a fourth level according to the different switching devices in the connected switching device group. The number of third level image processors may be the same as or different from the number of fourth level image processors. The third level image processors are connected to the first level switching devices, and the fourth level graphics processors are connected to the second level switching devices in each switching device group.

[0088] like Figure 2 , Figure 3 and Figure 5 As shown, GPU1-GPU8 are image processors of the third level, and GPU9-GPU16 are image processors of the fourth level.

[0089] In some embodiments, the graphics processor interconnect structure includes a first level, a second level, a third level, and a fourth level, the third level and the fourth level each include at least one graphics processor, and the first level and the second level each include at least one switching device.

[0090] If there are multiple switching device groups, the first-level switching devices in different switching device groups are all connected to the third-level image processor, and the second-level switching devices in different switching device groups are all connected to the fourth-level image processor.

[0091] In some embodiments, the number of switching devices at the first level and the number of switching devices at the second level in each switching device group are the same.

[0092] In some embodiments, the number of first-level switching devices in the switching device group is set to be the same as the number of second-level switching devices, so that the switching devices in the switching device group are symmetrical. The switching device group has the symmetrical characteristics of a cross-network structure, which can further improve the transmission performance of the switching device group.

[0093] In some embodiments, the number of graphics processors in the third tier is the same as the number of graphics processors in the fourth tier.

[0094] In some embodiments, the number of graphics processors at the third level is set to be the same as the number of graphics processors at the fourth level, so that the arrangement of the graphics processors is symmetrical, which can improve the transmission performance between the graphics processors.

[0095] In some embodiments, the number of first-level switching devices in each switching device group is the same as the number of second-level switching devices and the number of third-level graphics processors is the same as the number of fourth-level graphics processors, so that the graphics processor interconnection structures are symmetrical, further improving the transmission performance of the graphics processor interconnection structures.

[0096] In some embodiments, the first-level switching device is divided into a first part switching device and a second part switching device, and the third-level graphics processor is divided into a first part graphics processor and a second part graphics processor, the first part graphics processor is interconnected with the first part switching device, and the second part graphics processor is interconnected with the second part switching device.

[0097] The second-level switching device is divided into a third-part switching device and a fourth-part switching device. The fourth-level graphics processor is divided into a third-part graphics processor and a fourth-part graphics processor. The third-part graphics processor is interconnected with the third-part switching device, and the fourth-part graphics processor is interconnected with the fourth-part switching device.

[0098] In some embodiments, when there are multiple switching devices at each level, the switching devices at each level may be divided into different parts, such as Figure 3 As shown, SW1-1 is the first part of the switching equipment, S1-2 is the second part of the switching equipment, SW2-1 is the third part of the switching equipment, and S2-2 is the fourth part of the switching equipment.

[0099] Meanwhile, when the number of image processors at each level is multiple, the image processors at each level can be divided into different parts, such as Figure 3As shown, GPU1-GPU4 are the first part of the graphics processors, GPU5-GPU8 are the second part of the graphics processors, GPU9-GPU12 are the third part of the graphics processors, and GPU13-GPU16 are the fourth part of the graphics processors.

[0100] The first part of the graphic processors is interconnected with the first part of the switching device, the second part of the graphic processors is interconnected with the second part of the switching device; the third part of the graphic processors is interconnected with the third part of the switching device, and the fourth part of the graphic processors is interconnected with the fourth part of the switching device, so as to ensure the balance of the image processors connected to each switching device in the switching device group to improve the transmission efficiency.

[0101] It is understandable that when the switching devices at the same level are divided into different parts, they can be divided equally or the difference in the number of switching devices in different parts can be reduced as much as possible.

[0102] For graphics processors of the same level, when dividing them into different parts, they can be divided evenly or the difference in the number of graphics processors in different parts can be reduced as much as possible.

[0103] The number of the first part of switching devices is the same as that of the second part of switching devices, the number of the first part of graphics processors is the same as that of the second part of graphics processors, the number of the third part of switching devices is the same as that of the fourth part of switching devices, and the number of the third part of graphics processors is the same as that of the fourth part of graphics processors, so that the graphics processor interconnection structure maintains symmetry to improve the transmission performance of the graphics processor interconnection structure.

[0104] In some embodiments, the first-level switching devices in each switching device group are connected to the second-level switching devices via links, and at least one link connecting the first-level switching devices in each switching device group to the second-level switching devices includes a first virtual channel and a second virtual channel.

[0105] In some embodiments, when data is transmitted between two image processors at the same level, a deadlock may occur.

[0106] like Figure 6 As shown, Figure 3 For example, if there are four switching devices in a switching device group, when data from SW1-1 is transmitted to SW2-2, the data transmission link is regarded as link0; when data from SW2-2 is transmitted to SW1-2, the data transmission link is regarded as link1; when data from SW1-2 is transmitted to SW2-1, the data transmission link is regarded as link2; and when data from SW2-1 is transmitted to SW1-1, the data transmission link is regarded as link3.

[0107] when Figure 4If the four links transmit data at the same time, a dependent path link0->link1->link2->link3->link0 will be generated, causing a deadlock.

[0108] In this embodiment, two virtual channels are set in the links connected to the switching devices at different levels, and data transmission is performed by switching different virtual channels, thereby avoiding deadlock.

[0109] In some embodiments, the number of links connected to the switching devices at different levels may be one or more, and at least one of the one or more links is set with a virtual channel.

[0110] Figure 6 The link0 in the example can correspond to two virtual channels, link01 and link02; link1 can correspond to two virtual channels, link11 and link12; link2 can correspond to two virtual channels, link21 and link22; and link3 can correspond to two virtual channels, link31 and link32. For example, if link01, link11, link21, and link31 are set as the first virtual channel, and link02, link12, link22, and link32 are set as the second virtual channel, deadlock can be avoided by switching between the two virtual channels.

[0111] In some embodiments, Figure 7 As shown, a data transmission method is proposed, which is applied to a first switching device, and the first switching device is any switching device in the above-mentioned graphics processor interconnection structure; the method includes:

[0112] S701: Determine whether a destination address of data to be transmitted is an address of a graphics processor connected to a first switching device.

[0113] If yes, then execute S702 to send the data to be transmitted to the graphics processor corresponding to the destination address.

[0114] In some embodiments, the first switching device receives data to be transmitted, and the data to be transmitted has a corresponding destination address, where the destination address is the address of the image processor to which the data to be transmitted needs to be transmitted.

[0115] In some embodiments, if the destination address is the address of a graphics processor connected to the first switching device, the first switching device may directly send the data to be transmitted to the graphics processor corresponding to the destination address.

[0116] If the first switching device is Figure 3SW1-1 in the example, the destination address is GPU2, and SW1-1 can directly send the data to be transmitted through the link connected to GPU2.

[0117] In some embodiments, before data transmission, the switching device and the image processor in the graphics processor interconnection structure can be initialized to mark the layers to which the switching device and the image processor belong, as well as the connection request between the switching device and the image processor, such as determining that an image processor is connected to a switching device at a certain layer, that is, the switching device and the image processor can obtain a network topology information table to determine the address of the image processor, the switching device to which the image processor is connected, and the layer to which the switching device is located.

[0118] If not, execute S703 to determine whether the switching device to which the graphics processor corresponding to the destination address is connected is located at the same level as the first switching device.

[0119] In some embodiments, if the destination address of the data to be transmitted is not the address of the graphics processor connected to the first switching device, the first switching device needs to send the data to be transmitted to other switching devices for forwarding through the other switching devices.

[0120] At this time, it may be determined whether the switching device to which the graphics processor corresponding to the destination address is connected is located at the same level as the first switching device.

[0121] If the switching device connected to the graphics processor corresponding to the destination address is at the same level as the first switching device, S704 is executed to send the data to be transmitted to the switching device connected to the first switching device.

[0122] If the first switching device is not connected to the switching device at the same level, the first switching device needs to transmit the data to be transmitted to the switching device at the next level, and the data is forwarded by the switching device at the next level.

[0123] When there are multiple switching devices for exchanging with the first switching device, any connected switching device may be selected for forwarding.

[0124] If the switching device connected to the graphics processor corresponding to the destination address is not located at the same level as the first switching device, S705 is executed to send the data to be transmitted to the switching device connected to the graphics processor corresponding to the destination address.

[0125] If the switching device connected to the graphics processor corresponding to the destination address is not at the same level as the switching device, the switching device connected to the graphics processor corresponding to the destination address can be directly determined, and the data to be transmitted can be sent to the switching device connected to the graphics processor corresponding to the destination address, and the data to be transmitted can be sent to the graphics processor corresponding to the destination address through the switching device connected to the graphics processor corresponding to the destination address.

[0126] In an embodiment of the present application, a data transmission method is provided, which can perform data transmission between graphics processor interconnect structures.

[0127] In some embodiments, the link between the first-level switching device and the second-level switching device in each switching device group includes a first virtual channel and a second virtual channel. By setting the first virtual channel and the second virtual channel, the following is avoided: Figure 6 Deadlock shown.

[0128] Therefore, a switching method between the first virtual channel and the second virtual channel is also proposed.

[0129] If the switching device connected to the graphics processor corresponding to the destination address is at the same level as the first switching device, when sending the data to be transmitted to the switching device connected to the first switching device, the data to be transmitted can be directly sent to the switching device connected to the first switching device through the first virtual channel.

[0130] The first virtual channel is considered as a default virtual channel.

[0131] If the switching device connected to the graphics processor corresponding to the destination address is not at the same level as the first switching device, the data to be transmitted is sent to the switching device connected to the graphics processor corresponding to the destination address. If the graphics processor sending the data to be transmitted is connected to the first switching device, the data to be transmitted is sent to the switching device connected to the graphics processor corresponding to the destination address through the first virtual channel; if the graphics processor sending the data to be transmitted is connected to the first switching device, the data to be transmitted is sent to the switching device connected to the graphics processor corresponding to the destination address through the second virtual channel.

[0132] In some embodiments, if the graphics processor sending the data to be transmitted is connected to the first switching device, it means that the data to be transmitted received by the first switching device comes from the graphics processor. Therefore, the data can be forwarded directly through the default virtual channel without switching the virtual channel.

[0133] In some embodiments, if the graphics processor that sends the data to be transmitted is not connected to the first switching device, it means that the data to be transmitted received by the first switching device comes from other switching devices, and the first switching device is used to forward the data to be transmitted to other switching devices. At this time, it is necessary to switch the virtual channel, switch the default virtual channel to the second virtual channel, and forward the data through the second virtual channel to avoid data deadlock.

[0134] In some embodiments, a data transmission is also proposed, which is applied to a first switching device, and the first switching device is any switching device in a graphics processor interconnect structure; the device includes:

[0135] A first processing module, configured to send the data to be transmitted to the graphics processor corresponding to the destination address if the destination address of the data to be transmitted is the address of the graphics processor connected to the first switching device;

[0136] a second processing module, configured to determine whether the switching device to which the graphics processor corresponding to the destination address is connected is located at the same level as the first switching device if the destination address of the data to be transmitted is not the address of the graphics processor connected to the first switching device;

[0137] A third processing module, configured to send the data to be transmitted to the switching device connected to the first switching device if the switching device connected to the graphics processor corresponding to the destination address is at the same level as the first switching device;

[0138] The fourth processing module is configured to send the data to be transmitted to the switching device connected to the graphics processor corresponding to the destination address if the switching device connected to the graphics processor corresponding to the destination address is not located at the same level as the first switching device.

[0139] In some embodiments, the link connecting the first-level switching device and the second-level switching device in each switching device group includes a first virtual channel and a second virtual channel, and the second processing module also includes a first unit for sending the data to be transmitted to the switching device connected to the first switching device through the first virtual channel; the fourth processing module includes a second unit for sending the data to be transmitted to the switching device connected to the graphics processor corresponding to the destination address through the first virtual channel if the graphics processor sending the data to be transmitted is connected to the first switching device; and a third unit for sending the data to be transmitted to the switching device connected to the graphics processor corresponding to the destination address through the second virtual channel if the graphics processor sending the data to be transmitted is connected to the first switching device.

[0140] In some embodiments, an electronic device is also proposed, which may include: a processor and a memory, wherein the processor and the memory can communicate; exemplarily, the processor and the memory communicate via a communication bus, the memory is used to store computer execution instructions, and the processor is used to call the computer execution instructions in the memory to execute the data transmission method shown in any of the above method embodiments.

[0141] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the present application may be directly implemented as being executed by a hardware processor, or may be implemented by a combination of hardware and software modules in the processor.

[0142] The present application provides a computer-readable storage medium, on which a computer program is stored; when the computer program is executed by a processor, it is used to implement the data transmission method as described in any of the above embodiments.

[0143] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed, the computer executes the above-mentioned data transmission method.

[0144] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0145] It should be noted that the phrases "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. mentioned in the specification indicate that the described embodiments may include certain features, structures or characteristics, but not every embodiment may include the certain features, structures or characteristics. In addition, such phrases do not necessarily refer to the same embodiment. In addition, when describing certain features, structures or characteristics in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such features, structures or characteristics in conjunction with other embodiments, whether explicitly or not explicitly described.

[0146] In general, terms should be understood, at least in part, by the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context.

[0147] It should be easily understood that “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” not only includes the meaning of “above” or “over,” but also may include the meaning of “above” or “over something” with no intervening features or layers therebetween (i.e., directly on something).

[0148] In addition, spatially relative terms, such as "below," "below," "beneath," "above," "above," etc., may be used herein for ease of description to describe the relationship of one element or feature relative to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0149] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A graphics processor interconnect structure, characterized in that: It includes multiple graphics processors and at least one switching device group, each switching device group includes multiple switching devices, and the multiple switching devices in each switching device group include first-level switching devices and second-level switching devices; wherein, Each graphics processor is connected to any switching device in each switching device group, and the first-level switching device in each switching device group is connected to the second-level switching device; The sum of the number of switching devices connected to any switching device in each switching device group and the number of graphics processors is less than or equal to the number of ports of the corresponding switching device.

2. The graphics processor interconnect structure according to claim 1, characterized in that: The number of the switching device groups is less than or equal to the number of ports of the graphics processor.

3. The graphics processor interconnect structure according to claim 1, characterized in that: Each graphics processor is connected to any switching device in each switching device group via one link, and a first-level switching device in at least one switching device group is connected to a second-level switching device via two links; The sum of the number of links connected to any switching device in each switching device group and the number of links connected to the image processor is less than or equal to the number of ports of the corresponding switching device.

4. The graphics processor interconnect structure according to any one of claims 1 to 3, characterized in that: The multiple graphics processors include third-level graphics processors and fourth-level graphics processors. The third-level graphics processors are connected to the first-level switching devices in each switching device group, and the fourth-level graphics processors are connected to the second-level switching devices in each switching device group.

5. The graphics processor interconnect structure according to claim 4, characterized in that: In each switching device group, the number of the first-level switching devices is the same as the number of the second-level switching devices.

6. The graphics processor interconnect structure according to claim 4, characterized in that: The number of the graphics processors of the third level is the same as the number of the graphics processors of the fourth level.

7. The graphics processor interconnect structure according to claim 4, characterized in that: The first-level switching device is divided into a first part of switching devices and a second part of switching devices, the third-level graphics processor is divided into a first part of graphics processors and a second part of graphics processors, the first part of graphics processors is interconnected with the first part of switching devices, and the second part of graphics processors is interconnected with the second part of switching devices; The second-level switching device is divided into a third-part switching device and a fourth-part switching device, and the fourth-level graphics processor is divided into a third-part graphics processor and a fourth-part graphics processor. The third-part graphics processor is interconnected with the third-part switching device, and the fourth-part graphics processor is interconnected with the fourth-part switching device.

8. The graphics processor interconnect structure according to claim 1, characterized in that: The first-level switching devices in each switching device group are connected to the second-level switching devices via links, and at least one link connecting the first-level switching devices in each switching device group and the second-level switching devices includes a first virtual channel and a second virtual channel.

9. A data transmission method, characterized in that: Applied to a first switching device, the first switching device is any switching device in a graphics processor interconnect structure, and the graphics processor interconnect structure is the graphics processor interconnect structure according to any one of claims 1 to 8; the method comprises: If the destination address of the data to be transmitted is the address of a graphics processor connected to the first switching device, sending the data to be transmitted to the graphics processor corresponding to the destination address; If the destination address of the data to be transmitted is not the address of the graphics processor connected to the first switching device, determining whether the switching device connected to the graphics processor corresponding to the destination address is located at the same level as the first switching device; If the switching device connected to the graphics processor corresponding to the destination address is at the same level as the first switching device, sending the data to be transmitted to the switching device connected to the first switching device; If the switching device connected to the graphics processor corresponding to the destination address is not located at the same level as the first switching device, the data to be transmitted is sent to the switching device connected to the graphics processor corresponding to the destination address.

10. The data transmission method according to claim 9, characterized in that: The link connecting the first-level switching device in each switching device group and the second-level switching device includes a first virtual channel and a second virtual channel; The step of sending the data to be transmitted to a switching device connected to the first switching device includes: Sending the data to be transmitted to a switching device connected to the first switching device through the first virtual channel; The step of sending the data to be transmitted to a switching device connected to a graphics processor corresponding to the destination address includes: If the graphics processor that sends the data to be transmitted is connected to the first switching device, sending the data to be transmitted to the switching device connected to the graphics processor corresponding to the destination address through the first virtual channel; If the graphics processor that sends the data to be transmitted is connected to the first switching device, the data to be transmitted is sent to the switching device connected to the graphics processor corresponding to the destination address through the second virtual channel.

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