Chip joint simulation method, electronic device and medium

Abstract

The present invention relates to the field of chip verification technology, in particular to a chip co-simulation method, electronic equipment and medium, the method comprising step S1, simultaneously inputting the same test case to the chip design and simulation model to be tested; step S2, j i The corresponding output data is stored in C i The corresponding j-th first-in-first-out queue Q j i Step S3: Get D in real time i Corresponding DC j i Output data DA j i ; Step S4, Analyze DA j i Get DC j i Corresponding identification, determine the target Q j i , read out the current target Q j i The first data stored in CA j i ; Step S5, compare DA j i , CA j i , if all DA j i =CA j i , then loop through steps S1-S5. If DA j i ≠CA j i , the joint simulation ends and a chip verification failure prompt message is generated. This improves the efficiency of chip verification and reduces the cost of chip verification.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a chip co-simulation method, electronic equipment and medium. Background Art

[0002] In the process of chip verification, it is necessary to input a test stimulus to the chip design under test (Design Under Test, DUT for short) and store the data output by the chip design under test. It is also necessary to set a simulation model (CModel) written in C program with the same logic as the chip design under test, input the same test stimulus (Test Case) into the simulation model, and store the data output by the simulation model. The chip design under test and the simulation model are run independently of each other. It takes a lot of time to finish running the chip design under test and the simulation model. The output data are also stored independently of each other, and the amount of data output is huge, which requires a large amount of storage space. After the chip design under test and the simulation model have all run, the data output by the chip design under test and the simulation model are compared to verify the chip design under test. However, this chip verification method does not have real-time performance, the verification process is complicated, and the verification process is time-consuming, which makes chip verification efficiency low and costly. It can be seen from this that how to improve the efficiency of chip verification and reduce the cost of chip verification. Summary of the Invention

[0003] The present invention aims to provide a chip co-simulation method, electronic equipment and medium, which improve the efficiency of chip verification and reduce the cost of chip verification.

[0004] According to a first aspect of the present invention, a chip co-simulation method is provided, comprising:

[0005] Step S1: Input the same test case to the chip design under test and the simulation model at the same time. The design under test is generated based on a hardware description language, and the simulation model is generated based on a high-level language. The running speed of the simulation model is faster than the running speed of the chip design under test. The chip design under test includes 1 multi-processing module output interface D under test. i The simulation model includes a multi-processing module simulation output interface C i , the value range of i is 1 to I, I is the total number of multi-processing module output interfaces, and the multi-processing module output interface is used to output the output data of multiple parallel processing modules;

[0006] Steps S2, C i Corresponding to f(i) processing modules {BC1 i ,BC2 i ,…,BC j i ,…,BC f(i)i}, D i Corresponding to f(i) processing modules {DC1 i ,DC2 i ,…,DC j i ,…,DC f(i) i}, BC j i C i The corresponding j-th processing module, DC j i D i The corresponding j-th processing module, BC j i and DC j i The function is the same, the value range of j is 1 to f(i), f(i) is C i 、D i The total number of parallel processing modules corresponding to BC j i The corresponding output data is stored in C i The corresponding j-th first-in-first-out queue Q j i Middle, BC j i The corresponding output data includes BC j i corresponding logo;

[0007] Step S3: Get D in real time i Corresponding DC j i Output data DA j i ,DA j i Including DC j i Corresponding logo, DC j i Corresponding logo and BC j i The corresponding identifiers are the same;

[0008] Step S4: Analyze DA j i Get DC j i Corresponding identification, based on DC j i The corresponding identifier determines the target Q j i , and from the target Q j i Read the current target Q ji The first data stored in CA j i ;

[0009] Step S5: Compare DA j i , CA j i , if all DA j i =CA j i , then execute steps S1 to S5 in a loop to perform joint simulation. If DA j i ≠CA j i , the joint simulation ends and a chip verification failure prompt message is generated.

[0010] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0011] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0012] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the chip co-simulation method, electronic device, and medium provided by the present invention can achieve considerable technological advancement and practicality, and have wide industrial application value, with at least the following beneficial effects:

[0013] The present invention directly performs joint simulation on the chip design to be tested and the simulation model. By setting multiple first-in-first-out queues for the output of the simulation model multi-processing module and setting labels for all the output data, it can accurately match the corresponding data for comparison, avoiding errors in the joint simulation based on the multi-processing module interface. In addition, the present invention only needs to store the data output by the simulation model multi-processing module interface, compare the data output by the chip design to be tested with the data corresponding to the simulation model in real time, perform real-time detection, and delete the data corresponding to the simulation model when the detection passes, thereby reducing the storage space occupied, improving the efficiency of chip verification, and reducing the cost of chip verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 This is a flow chart of the chip co-simulation method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0017] The embodiment of the present invention provides a chip joint simulation method, such as Figure 1 As shown, including:

[0018] Step S1: Input the same test case to the chip design under test and the simulation model at the same time. The design under test is generated based on a hardware description language, and the simulation model is generated based on a high-level language. The running speed of the simulation model is faster than the running speed of the chip design under test. The chip design under test includes 1 multi-processing module output interface D under test. i The simulation model includes a multi-processing module simulation output interface C i The value range of i is 1 to I, where I is the total number of multi-processing module output interfaces, and the multi-processing module output interface is used to output the output data of multiple parallel processing modules.

[0019] It should be noted that the chip design and simulation model under test have the same functions and include the same multi-processing module interfaces, but are written and generated in different languages. As an example, the hardware programming language is Verilog and the high-level language is C. Specifically, the driver processing module set up in the chip verification platform (Testbench) can simultaneously input the same test cases to the chip design and simulation model under test.

[0020] Steps S2, C i Corresponding to f(i) processing modules {BC1 i ,BC2 i ,…,BC j i ,…,BC f(i) i}, D iCorresponding to f(i) processing modules {DC1 i ,DC2 i ,…,DC j i ,…,DC f(i) i}, BC j i C i The corresponding j-th processing module, DC j i D i The corresponding j-th processing module, BC j i and DC j i The function is the same, the value range of j is 1 to f(i), f(i) is C i 、D i The total number of parallel processing modules corresponding to BC j i The corresponding output data is stored in C i The corresponding j-th first-in-first-out queue Q j i Middle, BC j i The corresponding output data includes BC j i The corresponding logo.

[0021] The first-in first-out queue can be specifically a FIFO (First Input First Output) memory. It can be understood that in the simulation model, there are multiple processing modules and C i Connected via C i Output data, correspondingly, the chip under test is designed to have only multiple processing modules and D i Connected via D i Output data. C i Contains f(i) first-in-first-out queues Q j i , that is, C i Each corresponding processing module is equipped with an independent first-in first-out queue Q j i . And each output data is set with BC j i The corresponding logo should be noted that each BC j i The corresponding identifier can correspond to a corresponding first-in-first-out queue Q j i It should be noted that f(i) is C i 、D iThe total number of parallel processing modules corresponding to C i The total number of corresponding parallel processing modules is f(i), D i The corresponding total number of parallel processing modules is also f(i).

[0022] Step S3: Get D in real time i Corresponding DC j i Output data DA j i ,DA j i Including DC j i Corresponding logo, DC j i Corresponding logo and BC j i The corresponding identifiers are the same.

[0023] It should be noted that DC j i Corresponding logo and BC j i The corresponding identifiers are the same, which can confirm the DA through the information j i The first-in-first-out queue that should be compared can ensure the correct data comparison order of multiple modules and avoid errors in joint simulation.

[0024] Step S4: Analyze DA j i Get DC j i Corresponding identification, based on DC j i The corresponding identifier determines the target Q j i , and from the target Q j i Read the current target Q j i The first data stored in CA j i .

[0025] Among them, due to DC j i Corresponding logo and BC j i The corresponding identifiers are the same, so it can be directly based on DC j i The corresponding identifier determines the target Q j i , so as to accurately obtain the data that needs to be compared and ensure the correct data comparison order of multiple modules.

[0026] It should be noted that only an integer "int" data cache DA needs to be set j i No additional D i Set up the memory. Only C i Each processing module BC j i Set up a first-in-first-out queue Q j i To store BC j i As an example, in step S4, when the target Q j i Read the current target Q j i The first data stored in CA j i Afterwards, the CA j i From the target Q j i In the prior art, the chip design and simulation models to be tested need to be run separately, and after the runs are completed, all output data need to be stored in memory for comparison, which takes up a lot of space. In the embodiment of the present invention, only a small-capacity first-in-first-out queue is required, which greatly reduces the space occupied by data and reduces the cost of chip verification.

[0027] Step S5: Compare DA j i , CA j i , if all DA j i =CA j i , then execute steps S1 to S5 in a loop to perform joint simulation. If DA j i ≠CA j i , the joint simulation ends and a chip verification failure prompt message is generated.

[0028] It should be noted that for each chip design to be tested and the data output from the simulation output interface of the simulation model, the steps S1 to S5 should be used to perform real-time comparison. j i ≠CA j i, it means that the chip verification has failed, the joint simulation is immediately terminated, and a prompt is given. No subsequent operations are required. In the prior art, the chip design and simulation model to be tested need to be run separately before data comparison can be performed. Therefore, compared with the prior art, the embodiment of the present invention greatly improves the chip verification efficiency and reduces the chip verification cost.

[0029] As an embodiment, step S2 includes:

[0030] Step S21: BC j i The corresponding output data is converted into data described in SystemVerilog language;

[0031] Step S22: Convert the BC described in SystemVerilog language into j i The corresponding output data is stored in C i The corresponding j-th first-in-first-out queue Q j i middle.

[0032] It should be noted that BC j i The corresponding output data is data described in high-level language and cannot be directly connected to DC j i The output data is compared, so C i First BC j i The corresponding output data is transmitted to the chip verification platform, and the chip verification platform transmits BC j i The corresponding output data is converted into data described in SystemVerilog language, and the data described in SystemVerilog language can be directly used with DC j i Compare the output data of the hardware description language.

[0033] As an embodiment, in step S5, generating chip verification failure prompt information includes:

[0034] Step S51: Based on unequal DA j i , CA j i And the corresponding D i 、C i , corresponding DC j i , BC j i , generating a chip verification failure prompt message.

[0035] As can be seen from step S51 , the embodiment of the present invention can not only obtain chip verification results in real time, but also include erroneous data and corresponding interface information in the chip verification results, thereby providing support for user debugging.

[0036] In some application scenarios, although each group of DA j i , CA j i Although all comparisons have passed, it does not necessarily mean that the chip verification is successful. This is because there may be uncompared data in the chip design or simulation model under test at the end of the joint simulation. In this case, it means that there are problems with the chip verification and corresponding errors are required.

[0037] As an embodiment, the method further includes step S10, obtaining a simulation state identifier from a state machine corresponding to the chip design to be tested, and if the obtained simulation end identifier is an end state, executing step S20;

[0038] Step S20: Determine whether there is at least one C i There are still uncompared DA j i If it exists, a chip verification failure prompt message will be generated.

[0039] In step S20, generating chip verification failure prompt information includes:

[0040] Step S201: Based on the uncompared DA j i , and the corresponding D i 、C i , corresponding DC j i , BC j i , generating a chip verification failure prompt message.

[0041] It should be noted that when the simulation end mark is obtained as the end state, it means that the joint simulation has ended, and no DA j i ≠CA j i , but if there is at least one C i There are still uncompared DA j i , it means that the chip verification is not successful, and this may be a problem with the design of the chip to be tested or a problem with the simulation model. j i And the corresponding D i 、C i, corresponding DC j i , BC j i Generate chip verification failure prompt information to provide a reference for users' subsequent debugging.

[0042] As an embodiment, the method further includes step S100, obtaining a simulation state identifier from a state machine corresponding to the chip design to be tested, and if the obtained simulation end identifier is an end state, executing step S200;

[0043] Step S200: Determine whether there is at least one Q j i Not empty. If it exists, a chip verification failure prompt message will be generated.

[0044] In step S200, generating chip verification failure prompt information includes:

[0045] Step S2001: Based on the non-empty Q j i The first data stored in CA j i And the corresponding D i 、C i , corresponding DC j i , BC j i Generate chip verification failure prompt information.

[0046] It should be noted that when the simulation end mark is obtained as the end state, it means that the joint simulation has ended, and no DA j i ≠CA j i , but if there is at least one Q j i If it is not empty, it means that the chip verification is not successful, and this may be a problem with the design of the chip to be tested or a problem with the simulation model. Therefore, based on the non-empty Q j i The first data stored in CA j i , and the corresponding D i 、C i , corresponding DC j i , BC j i Generate chip verification failure prompt information to provide a reference for users' subsequent debugging.

[0047] As an embodiment, the method further includes step S01, obtaining a simulation state identifier from a state machine corresponding to the chip design to be tested, and if the obtained simulation end identifier is an end state, and all D i There is no uncompared DA j i , all Q j i If both are empty, a chip verification success prompt message will be generated.

[0048] Since the simulation model runs faster than the chip design under test, the simulation model will run before the chip design under test. However, for cases where it needs to wait for a reply message before continuing to execute, the simulation model needs to wait. For data that does not need to wait for a reply message, the simulation model can be executed before the chip design under test, thereby ensuring the accuracy of the joint simulation. The step S2 includes:

[0049] Step S211: If BC j i Output data CA j i For the preset first type of data, BC j i Continue to execute the output operation; if BC j i Output data CA j i If the second type of data is preset, C is paused. i The output operation of the jth processing module, waiting for DC j i Output data DA j i And CA j i =DA j i When, based on DA j i Generate corresponding reply information H j i , and send to C at the same time i and D i , when BC j i Receive H j i At BC j i The output operation is continued, the first type of data is data that does not need to wait for reply information, and the second type of data is data that needs to receive reply information.

[0050] Through step S211, it can be ensured that the input information of the chip design to be tested and the simulation model are always synchronized and the input information is the same.i Output data CA j i Specifically, it can be control data, read instruction data, write instruction data, etc.

[0051] As an embodiment, in step S211, if BC j i Output data CA j i To read instruction data, CA j i Including the target read address, if the read instruction data is the second type of data, then wait for CA j i =DA j i When, based on DC j i Output data DA j i Get the target read data corresponding to the target read address from the preset memory and send the target read data to C at the same time i and D i .

[0052] It should be noted that, in the joint simulation process, the chip design and simulation model to be tested always correspond to the same memory. When the read instruction data is the second type of data, C i Output data CA j i The data will not be read from the memory immediately, but it needs to wait until D i Output DA j i , and compared to get CA j i =DA j i After the results, based on CA j i Get the target read data corresponding to the target read address from the preset memory and send the target read data to C at the same time i and D i , thus avoiding C i and D i Different read data is obtained based on the same read instruction data, resulting in errors in the joint simulation.

[0053] As an embodiment, in step S211, if BC j i Output data CA j i To write instruction data, CA j iIncluding the target write address letter and the target write data, if the write instruction data is the second type of data, then wait for CA j i =DA j i When, based on DC j i Output data DA j i Write the target write data to the target write address of the preset memory, generate a confirmation write message, and send the confirmation write message to C i and D i .

[0054] It should be noted that, in the joint simulation process, the chip design and simulation model to be tested always correspond to the same memory. When the write instruction data is the second type of data, C i Output data CA j i The data will not be written to the memory immediately, but it needs to wait until D i Output DA j i , and compared to get CA j i =DA j i After the results, based on DA j i Write the target write data to the target write address of the preset memory and send the confirmation write information to C at the same time. i and D i , thus avoiding errors in joint simulation.

[0055] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0056] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0057] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0058] The embodiment of the present invention directly performs joint simulation on the chip design to be tested and the simulation model. By setting multiple first-in-first-out queues for the output of the multi-processing module of the simulation model and setting identifiers for all the output data, it can accurately match the corresponding data for comparison, thereby avoiding errors in the joint simulation based on the multi-processing module interface. In addition, the present invention only needs to store the data output by the multi-processing module interface of the simulation model, compare the data output by the chip design to be tested with the data corresponding to the simulation model in real time, perform real-time detection, and delete the data corresponding to the simulation model when the detection passes, thereby reducing the storage space occupied, improving the efficiency of chip verification, and reducing the cost of chip verification.

[0059] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A chip co-simulation method, characterized in that: include: Step S1: Input the same test case to the chip design and simulation model at the same time. The chip design is generated based on a hardware description language, and the simulation model is generated based on a high-level language. The simulation model runs faster than the chip design. The chip design includes a multi-processing module output interface D to be tested. i The simulation model includes a multi-processing module simulation output interface C i , the value range of i is 1 to I, I is the total number of multi-processing module output interfaces, and the multi-processing module output interface is used to output the output data of multiple parallel processing modules; Steps S2, C i Corresponding to f(i) processing modules {BC1 i ,BC2 i ,…,BC j i ,…,BC f(i) i }, D i Corresponding to f(i) processing modules {DC1 i ,DC2 i ,…,DC j i ,…,DC f(i) i }, BC j i C i The corresponding j-th processing module, DC j i D i The corresponding j-th processing module, BC j i and DC j i The function is the same, the value range of j is 1 to f(i), f(i) is C i 、D i The total number of parallel processing modules corresponding to BC j i The corresponding output data is stored in C i The corresponding j-th first-in-first-out queue Q j i Middle, BC j i The corresponding output data includes BC j i corresponding logo; Step S3: Get D in real time i Corresponding DC j i Output data DA j i ,DA j i Including DC j i corresponding logo; Step S4: Analyze DA j i Get DC j i Corresponding identification, based on DC j i The corresponding identifier determines the target Q j i , and from the target Q j i Read the current target Q j i The first data stored in CA j i ; Step S5: Compare DA j i , CA j i , if all DA j i =CA j i , then execute steps S1 to S5 in a loop to perform joint simulation. If DA j i ≠CA j i , the joint simulation ends and a chip verification failure prompt message is generated.

2. The method according to claim 1, characterized in that The step S2 comprises: Step S211: If BC j i Output data CA j i For the preset first type of data, BCji continues to perform the output operation; if BC j i Output data CA j i If the second type of data is preset, C is paused. i The output operation of the jth processing module, waiting for DC j i Output data DA j i And CA j i =DA j i When, based on DA j i Generate corresponding reply information H j i , and send to C at the same time i and D i , when BC j i Receive H j i At BC j i The output operation is continued, the first type of data is data that does not need to wait for reply information, and the second type of data is data that needs to receive reply information.

3. The method according to claim 2, characterized in that In step S211, if C i Output data CA j i To read instruction data, CA j i Including the target read address, if the read instruction data is the second type of data, then wait for CA j i =DA j i When, based on DC j i Output data DA j i Get the target read data corresponding to the target read address from the preset memory and send the target read data to C at the same time i and D i .

4. The method according to claim 2, characterized in that In step S211, if BC j i Output data CA j i To write instruction data, CA j i Including the target write address letter and the target write data, if the write instruction data is the second type of data, then wait for CA j i =DA j i When, based on DC j i Output data DA j i Write the target write data to the target write address of the preset memory, generate a confirmation write message, and send the confirmation write message to C i and D i .

5. The method according to claim 1, wherein DC j i Corresponding logo and BC j i The corresponding identifiers are the same.

6. The method according to claim 1, characterized in that In step S4, when the target Q j i Read the current target Q j i The first data stored in CA j i Afterwards, the CA j i From the target Q j i Delete in.

7. The method according to claim 1, characterized in that The method further comprises step S01, obtaining a simulation state identifier from a state machine corresponding to the chip design to be tested, and if the obtained simulation end identifier is an end state, and all D i There is no uncompared DA j i , all Q j i If both are empty, a chip verification success prompt message will be generated.

8. The method according to claim 1, characterized in that The first-in-first-out queue is a FIFO memory.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 8.

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