A method and device for enhancing cache mark bits in GPGPU

Abstract

The present invention relates to the field of GPGPU, and specifically provides a method and device for enhancing cache mark bits in GPGPU. After data or instructions enter the cache unit in the form of Thread, Thread first needs to find the corresponding cache position according to the corresponding index. After finding the corresponding position, Tag and Data will be stripped. After stripping, they will enter their respective CRC encoding and matrix storage for storage comparison. Only when the comparison is correct will the data be processed for the next step. If there is a problem during the comparison, the error_end signal will be pulled high, so that the pipeline will suspend the current work, and the corresponding Error can be repaired before continuing to work. Compared with the prior art, the present invention can enhance the stability of the cache unit in GPGPU by enhancing the marking means of the mark bit, thereby improving the overall working level of GPGPU.

Description

Technical Field

[0001] The present invention relates to the field of GPGPU, and specifically provides a method and a device for enhancing a cache mark bit in a GPGPU. Background Art

[0002] GPGPU (General-Purpose computing on Graphics Processing Units) refers to the use of graphics processing units (GPUs) for general computing, not just for graphics rendering. GPGPU uses the powerful parallel computing capabilities of GPUs to process non-graphics tasks, significantly improving computing efficiency.

[0003] At the same time, GPGPU has broad application prospects in scientific computing, deep learning, image processing, data analysis and many other scientific fields. GPGPU needs to have the ability to process large amounts of data in a timely and reliable manner. The cache unit, as a very important link in GPGPU, is an important carrier for data temporary storage. The cache unit has the fastest read and write speed, but due to the small capacity per unit area and the high cost per unit area, the capacity is generally not high in contemporary GPGPU design. Therefore, a hierarchical design concept is adopted. According to the logic of slower and slower read and write speeds and larger and larger capacities, the entire cache unit is divided into multiple levels of cache such as L1 L2 L3. After the process enters the nanometer level, the voltage requirement for triggering logic is reduced a lot. Although it is more conducive to system integration and electrical integration design, the lower trigger voltage also means that it is more susceptible to electromagnetic interference.

[0004] Cache is a very important data storage link. If it is affected by electromagnetic interference and causes data errors, it will have a very serious impact on GPGPU with a large amount of parallel computing.

[0005] Therefore, how to enhance the stability of the cache unit in GPGPU and thus improve the overall GPGPU performance is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0006] The present invention aims at addressing the above-mentioned deficiencies of the prior art and provides a method for enhancing cache mark bits in GPGPU with strong practicability.

[0007] A further technical task of the present invention is to provide a device for enhancing cache mark bits in GPGPU that is reasonably designed, safe and applicable.

[0008] The technical solution adopted by the present invention to solve its technical problem is:

[0009] A method for enhancing cache tag bits in GPGPU, after data or instructions enter the cache unit in the form of Thread, Thread first needs to find the corresponding cache position according to the corresponding index, after finding the corresponding position, Tag and Data will be stripped, and after stripping is completed, they will enter their respective CRC encoding and matrix storage for storage;

[0010] Data will be copied into two copies and take two routes respectively. One route is to enter the matrix storage unit module for storage after CRC encoding. When the cache unit receives the instruction, it will take out the data of the matrix storage unit and perform CRC decoding, that is, CRC is generated and then enters the comparison module for comparison. The content of the comparison is the second route, which directly stores the data into the matrix storage unit. In the matrix storage unit, it is stored in the same space as the data after CRC encoding.

[0011] After waiting for the relevant command to be issued, the data of the two lines will enter the comparison unit for comparison at the same time. The data will be processed for the next step only when the comparison is correct. If there is a problem during the comparison, the error_end signal will be pulled high, so that the pipeline will suspend the current work and continue to work after the corresponding Error is repaired;

[0012] In the CRC encoding, the operation process is implemented by XORing the input with the corresponding bit number, and then instantiating this process in parallel multiple times, using the result of the previous round of calculation as the input of the next calculation. Among them, for the polynomial generated by CRC, the format needs to be specified in advance, using CRC16.

[0013] In the CRC16, g(x)=x^16+x^12+x^5+1. If the input data is 1011001, then A(X)= = x^6+ x^4 + x^3 + 1. When CRC is generated, P(x)= A(x) × x^n / g(x) n will be generated. g(x) n is the highest power of x in g(x). This process is calculated in the CRC check module. The generation of A(x) is obtained by the corresponding coefficient and does not need to be calculated. Then a new result F(x)= A(x) × x^n + P(x) is generated. The calculated result is brought into the CRC check module for iteration to calculate whether there is a remainder. If there is no remainder, it proves that the data is correct. Then the data part is taken out and compared with the original data.

[0014] If there is an error, the corresponding Error signal will be raised.

[0015] Furthermore, the CRC check module is calculated as follows:

[0016] The generated polynomial g(x)=x^16+x^12+x^5+1 is the fixed check format of CRC16;

[0017] The CRC check code generation process is:

[0018] First, shift A(x) left by r bits, where r = 16, which is equivalent to A(x) × x^16. In polynomial operations, this step adds 16 terms corresponding to 0 after A(x). At this time, A(x) ×x^16 is the dividend, and A(x) ×x^16 is divided by g(x), that is, A(x) ×x^16=Q(x) ×g(x)+P(x), where Q(x) is the quotient, P(x) is the remainder, and the degree of P(x) is less than 16. The division here is binary division without borrowing in modulo 2 division, which is essentially an XOR operation. P(x) is the CRC - 16 check code;

[0019] Generate a new polynomial F(x) = A(x) ×x^16+P(x) and send it out. After the receiving end receives the data corresponding to the polynomial F(x), it divides F(x) by g(x). If the remainder is 0, it is considered that there is no error in the data transmission process. At this time, the data part corresponding to A(x) is extracted from F(x) and compared with the original sent data. The original sent data corresponds to A(x);

[0020] If the remainder is not 0, it means that an error has occurred in the data transmission and the corresponding Error signal will be raised.

[0021] Furthermore, when data enters the cache unit, it enters in the form of threads. A warp is composed of many warps. In GPGPU, the work unit is SM, and an SM core can only process one warp at a time.

[0022] Furthermore, the cache unit is composed of tag+Data, and the tag is composed of Tag+index. The tag is used to index the corresponding Data, wherein the index is used to determine the specific location of the cache line, and the Tag is used to compare whether the data is consistent.

[0023] Furthermore, when the data is first stored in the cache line, the tag is stored together with the data. When a cache line replacement operation occurs, the data to be replaced is indexed to the corresponding position through the index, and the tags of the two are compared. If the tags are consistent, the data is modified or replaced.

[0024] If the tags are inconsistent, a miss will occur and the cache will send the current request to a higher cache level until the tags match.

[0025] A device for enhancing a cache mark bit in a GPGPU, comprising: at least one memory and at least one processor;

[0026] The at least one memory is used to store a machine-readable program;

[0027] The at least one processor is used to call the machine-readable program to execute a method for enhancing a cache tag bit in a GPGPU.

[0028] Compared with the prior art, the method and device for enhancing the cache mark bit in GPGPU of the present invention have the following outstanding beneficial effects:

[0029] The present invention enhances the stability of the cache unit in the GPGPU by enhancing the marking means of the mark bit, thereby improving the working level of the entire GPGPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Attached Figure 1 It is a flowchart of a method for enhancing cache tag bits in GPGPU;

[0032] Attached Figure 2 A schematic diagram of a CRC check module in a method for enhancing cache mark bits in a GPGPU. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] A best embodiment is given below: Example

[0035] like Figure 1As shown, in this embodiment, a method for enhancing the cache tag bit in GPGPU is used. After data or instructions enter the cache unit in the form of Thread, Thread is first required to find the corresponding cache position according to the corresponding index. After finding the corresponding position, Tag and Data will be stripped. After stripping is completed, they will enter their respective CRC encoding and matrix storage for storage.

[0036] Data will be copied into two copies and take two routes respectively. One route is to enter the matrix storage unit module for storage after CRC encoding. When the cache unit receives the instruction, it will take out the data of the matrix storage unit and perform CRC decoding, that is, CRC is generated and then enters the comparison module for comparison. The content of the comparison is the second route, which directly stores the data into the matrix storage unit. In the matrix storage unit, it is stored in the same space as the data after CRC encoding.

[0037] After waiting for the relevant command to be issued, the data of the two lines will enter the comparison unit for comparison at the same time. The data will be processed for the next step only when the comparison is correct. If there is a problem during the comparison, the error_end signal will be pulled high, so that the pipeline will suspend the current work and continue to work after repairing the corresponding Error.

[0038] Take the Data channel as an example to describe the process:

[0039] The data will be copied into two copies and take two different routes. The first route will be stored in the matrix storage unit module after CRC encoding. When the cache unit receives instructions such as write, read, replace, etc., it will take out the data from the matrix storage unit and perform CRC decoding, that is, CRC is generated and then enters the comparison unit for comparison.

[0040] The content of the comparison is the second route. The second route will directly store the Data into the matrix storage unit. In the matrix storage unit, it is stored in the same space as the data after CRC encoding.

[0041] After waiting for the relevant command to be issued, the data of the two lines will enter the comparison unit for comparison at the same time. The data will be processed for the next step only when there is no error. If there is a problem during the comparison, the error_end signal will be pulled high, so that the pipeline will suspend the current work. The corresponding Error needs to be repaired before the work can continue. The repair method is not limited to invalidating the operation, reissuing data and instructions, etc.

[0042] For CRC encoding, the implemented CRC encoding is variable. The operation process is to perform XOR on the input and the corresponding bit number, and then instantiate this process in parallel multiple times, using the result of the previous round of calculation as the input of the next calculation. Among them, for the polynomial generated by CRC, the format needs to be specified in advance, usually CRC16.

[0043] Taking CRC16 as an example, the general g(x)=x^16+x^12+x^5+1. If the input data is 1011001, then A(X)==x^6+x^4+x^3+1. When CRC is generated, P(x)=A(x)×x^n / g(x)n will be generated. g(x)n is the highest power of x in g(x), such as Figure 2 As shown in the figure, this process is calculated in the CRC check module. A(x) is generated by the corresponding coefficient and does not need to be calculated. Then a new result F(x) = A(x) × x^n + P(x) is generated. The calculated result is brought into the CRC check module for iteration to calculate whether there is a remainder. If there is no remainder, it can be proved that the data is correct. At this time, the data part is taken out and compared with the original data. If there is an error, the corresponding Error signal will be pulled up.

[0044] Among them, the calculation method of the CRC check module is:

[0045] The generated polynomial g(x)=x^16+x^12+x^5+1 is the fixed check format of CRC16;

[0046] The CRC check code generation process is:

[0047] First, shift A(x) left by r bits, where r = 16, which is equivalent to A(x) × x^16. In polynomial operations, this step adds 16 terms corresponding to 0 after A(x). At this time, A(x) × x^16 is the dividend, and A(x) ×x^16 is divided by g(x), that is, A(x) × x^16=Q(x) ×g(x)+P(x), where Q(x) is the quotient, P(x) is the remainder, and the degree of P(x) is less than 16. The division here is binary division without borrowing in modulo 2 division, which is essentially an XOR operation. P(x) is the CRC - 16 check code;

[0048] Generate a new polynomial F(x) = A(x) × x^16+P(x) and send it out. After the receiving end receives the data corresponding to the polynomial F(x), it divides F(x) by g(x). If the remainder is 0, it is considered that there is no error in the data transmission process. At this time, the data part corresponding to A(x) is extracted from F(x) and compared with the original sent data. The original sent data corresponds to A(x);

[0049] If the remainder is not 0, it means that an error has occurred in the data transmission and the corresponding Error signal will be raised.

[0050] The division operation in the above process can be realized by the linear feedback shift register structure in the figure, and the relevant calculations and iterative operations are completed in the CRC check module. At the same time, the generation method of the coefficients in g(x) is innovatively updated so that two coefficients can be restored after each XOR unit, that is, the first and second items in g(x) (the item with the lowest power is the first item) are generated. It is designed as an expandable mode, so this module also supports more complex g(x) generation such as CRC32.

[0051] When data enters the cache unit, it enters in the form of a thread. A warp is composed of many warps. In GPGPU, the work unit is SM, and an SM core can only process one warp at a time.

[0052] The cache unit consists of tag + data, and the tag consists of tag + index. The tag is used to index the corresponding data, where the index is used to determine the specific location of the cache line, and the tag is used to compare whether the data is consistent.

[0053] When the cache line is first stored, the tag is stored together with the data. When the cache line is replaced, the data to be replaced is indexed to the corresponding position through the index, and the two tags are compared. If the tags are consistent, the data is modified or replaced.

[0054] If the tags are inconsistent, a miss will occur and the cache will send the current request to a higher cache level until the tags match.

[0055] Cache usually appears in a multi-level form, and work efficiency is improved as much as possible while saving area and cost. Therefore, according to the Harvard structure, the cache is divided into ICache (instruction cache), DCache (data cache), L2 cache, etc., among which Icache and Dcache belong to L1 cache, which have faster read and write speeds and smaller storage space. L2 Cache is distributed outside the SM core and is responsible for coordinating the cache consistency of multiple SM cores. At the same time, depending on the scale of GPGPU, there may also be L3 Cache set for L2 Cache. The specific cache level setting should be determined according to specific design requirements.

[0056] Cache has a variety of usage scenarios and functions. This application is aimed at the relevant reinforcement operations on the cache lines, so as to ensure that the cache can have a more stable storage process for the cache lines during operation, and when it comes to replacement, modification and deletion operations, to ensure that the data in the cache unit is stable and accurate. Example

[0057] This embodiment also provides a device for enhancing a cache mark bit in a GPGPU, comprising: at least one memory and at least one processor;

[0058] The memory is used to store machine-readable programs;

[0059] The processor is used to call the machine-readable program to execute a short video supply and demand diagnosis method.

[0060] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor may be a microprocessor or any conventional processor, etc.

[0061] The memory can be used to store computer programs and / or modules. The processor realizes various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required for a function, etc.; the data storage area can store data created according to the use of the terminal, etc. In addition, the memory can also include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (SMC), a secure digital (SD) card, a flash memory card, at least one disk storage period, a flash memory device, or other volatile solid-state storage devices.

[0062] The above-mentioned specific implementations are only specific cases of the present invention. The patent protection scope of the present invention includes but is not limited to the above-mentioned specific implementations. Any technical solutions that conform to the above-mentioned specific implementations of the present invention and any appropriate changes or substitutions made by ordinary technicians in the relevant technical field shall fall within the patent protection scope of the present invention.

[0063] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for enhancing cache mark bits in GPGPU, characterized in that: After data or instructions enter the cache unit in the form of Thread, Thread first needs to find the corresponding cache location according to the corresponding index. After finding the corresponding location, the Tag and Data will be stripped. After the stripping is completed, they will enter their respective CRC encoding and matrix storage for storage; Data will be copied into two copies and take two routes respectively. One route is to enter the matrix storage unit module for storage after CRC encoding. When the cache unit receives the instruction, it will take out the data of the matrix storage unit and perform CRC decoding, that is, CRC is generated and then enters the comparison module for comparison. The content of the comparison is the second route, which directly stores the data into the matrix storage unit. In the matrix storage unit, it is stored in the same space as the data after CRC encoding. After waiting for the relevant command to be issued, the data of the two lines will enter the comparison unit for comparison at the same time. The data will be processed for the next step only when the comparison is correct. If there is a problem during the comparison, the error_end signal will be pulled high, so that the pipeline will suspend the current work and continue to work after the corresponding Error is repaired; In the CRC encoding, the operation process is realized by XORing the input with the corresponding bit number, and then instantiating this process in parallel multiple times, and taking the result of the previous round of calculation as the input of the next calculation. Among them, for the polynomial generated by CRC, the format needs to be specified in advance, and CRC16 is used; In the CRC16, g(x)=x^16+x^12+x^5+1. If the input data is 1011001, then A(X)= = x^6 + x^4 + x^3 + 1. When CRC is generated, P(x)= A(x) × x^n / g(x) n will be generated. g(x) n is the highest power of x in g(x). This process is calculated in the CRC check module. The generation of A(x) is obtained by the corresponding coefficient and does not need to be calculated. Then a new result F(x)= A(x) × x^n + P(x) is generated. The calculated result is brought into the CRC check module for iteration to calculate whether there is a remainder. If there is no remainder, it proves that the data is correct. Then the data part is taken out and compared with the original data. If there is an error, the corresponding Error signal will be raised.

2. The method for enhancing cache mark bits in GPGPU according to claim 1, characterized in that: The CRC check module is calculated as follows: The generated polynomial g(x)=x^16+x^12+x^5+1 is the fixed check format of CRC16; The CRC check code generation process is: First, shift A(x) left by r bits, where r = 16, which is equivalent to A(x) × x^16. In polynomial operations, this step adds 16 terms corresponding to 0 after A(x). At this time, A(x) ×x^16 is the dividend, and A(x) ×x^16 is divided by g(x), that is, A(x) ×x^16=Q(x) ×g(x)+P(x), where Q(x) is the quotient, P(x) is the remainder, and the degree of P(x) is less than 16. The division here is binary division without borrowing in modulo 2 division, which is essentially an XOR operation. P(x) is the CRC - 16 check code; Generate a new polynomial F(x) = A(x) ×x^16+P(x) and send it out. After the receiving end receives the data corresponding to the polynomial F(x), it divides F(x) by g(x). If the remainder is 0, it is considered that there is no error in the data transmission process. At this time, the data part corresponding to A(x) is extracted from F(x) and compared with the original sent data. The original sent data corresponds to A(x); If the remainder is not 0, it means that an error has occurred in the data transmission and the corresponding Error signal will be raised.

3. The method for enhancing cache mark bits in GPGPU according to claim 2, characterized in that: When data enters the cache unit, it enters in the form of a thread. A warp is composed of many warps. In GPGPU, the work unit is SM, and an SM core can only process one warp at a time.

4. The method for enhancing cache mark bits in GPGPU according to claim 3, characterized in that: The cache unit is composed of tag+Data, and the tag is composed of Tag+index. The tag is used to index the corresponding Data, where the index is used to determine the specific location of the cache line, and the Tag is used to compare whether the data is consistent.

5. The method for enhancing cache mark bits in GPGPU according to claim 4, characterized in that: When the cache line is first stored, the tag is stored together with the data. When the cache line is replaced, the data to be replaced is indexed to the corresponding position through the index, and the two tags are compared. If the tags are consistent, the data is modified or replaced. If the tags are inconsistent, a miss will occur and the cache will send the current request to a higher cache level until the tags match.

6. A device for enhancing cache mark bits in GPGPU, characterized in that: include: at least one memory and at least one processor; The at least one memory is used to store a machine-readable program; The at least one processor is configured to call the machine-readable program to execute the method according to any one of claims 1 to 5.

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