Dynamic acceleration driving circuit and method for high-resolution and high-refresh-rate TFT LCD (Thin Film Transistor Liquid Crystal Display) screen

Abstract

The invention discloses a dynamic acceleration drive control circuit of a high-resolution and high-refresh-rate TFT LCD display screen, a first channel load (31) and a second channel load (32) are controlled by a polarity exchange circuit (2) to alternately display positive and negative polarity voltages, the input end of the polarity exchange circuit (2) is connected with a Source amplifier circuit (1), and the output end of the Source amplifier circuit (1) is connected with a power amplifier circuit (2). The output end of the polarity exchange circuit (2) is respectively connected with the input ends of the first channel load (31) and the second channel load (32); the polarity exchange circuit (2) at least comprises a second selector (MUX2) used for selecting voltages of positive polarity path intermediate nodes EXP1 and EXP2 to be sent to the positive Source amplifier (11) as feedback voltages, and a fourth selector (MUX4) used for selecting voltages of negative polarity path intermediate nodes EXN1 and EXN2 to be sent to the negative Source amplifier (12) as feedback voltages. The invention further provides a corresponding control method. The display screen can be quickly driven, the implementation method is simple, and the efficiency is high.

Description

Technical Field

[0001] The present invention belongs to the field of chips, specifically, to the field of display driver chips, especially for TFT_LCD display screens, specifically to high-resolution and high-refresh-rate TFT_LCD display screens, and specifically to dynamic acceleration drive control circuits and control methods for high-resolution and high-refresh-rate TFT_LCD display screens. Background Art

[0002] In the TFT_LCD screen display driver, the Source circuit generally drives the channel load voltage to the corresponding gamma grayscale voltage, and the Source is mainly driven by the op amp buffer circuit to drive the channel load. Generally speaking, the driving time of each row of pixels on small and medium resolution screens is relatively long, and the use of traditional amplifiers (OP) can meet the driving speed requirements. However, in the driving of high-resolution and high-refresh rate screens, the driving time of each row of pixels will become very short, and it is difficult for general op amps to meet the driving speed requirements. In order to increase the driving speed, the methods currently used in the industry are:

[0003] (1) Improve the slew rate and bandwidth of the op amp: In the initial stage of enabling the amplifier (OP), the tail current is increased by 2 to 4 times to increase the slew rate (SR) of the op amp and speed up the large signal settling time of the amplifier (OP); increase the overall power consumption and area of ​​the amplifier (OP), improve the small signal bandwidth of the OP, and make the amplifier (OP) have a shorter small signal settling time;

[0004] (2) Power supply acceleration driving technology: a MOS switch tube is connected between the output end of the amplifier (OP) and the power supply end, and the channel load is directly driven by the switch tube and the power supply. The principle is to drive the channel load voltage to near the middle gray scale by controlling the conduction time of the switch tube, and then the amplifier (OP) drives the channel load voltage to a stable voltage. This acceleration technology does not consider the gray scale voltage difference between the upstream and downstream lines, nor does it consider the voltage difference between different channel loads in the same line. It uniformly drives all channel load voltages of the same polarity to the corresponding power supply voltage. In fact, it is difficult to achieve a good driving effect.

[0005] The existing technology has many defects, such as:

[0006] (1) Improving the slew rate and bandwidth of the op amp: This solution sacrifices area and power consumption in order to reduce the driving time, which not only increases the chip cost, but also has limited ability to increase the driving speed. Especially in high refresh rate and high resolution display driver applications, the buffer working time is limited to a very short time. Even if this high power consumption and large area solution is adopted, it is difficult to meet the stringent requirements of driving speed.

[0007] (2) Power supply acceleration driving technology: This solution achieves acceleration driving by controlling the on-time of the switch tube. The Source circuit is composed of thousands of amplifiers (OP) driving thousands of channel loads. Since the magnitude and direction of the grayscale voltage between the upper and lower rows of each channel load are different, the magnitude and direction of the driving voltage between each channel load during the refresh process are very different. The above technology cannot achieve independent and refined charging and discharging control, and the acceleration effect is limited. This simple and crude acceleration method will increase the power consumption of the driver chip. In some applications with high driving speed requirements, it is difficult to meet the high-speed requirements. In addition, when the power supply and switch tube are used to accelerate the charging and discharging of the channel load, the channel load voltage slope changes very quickly, and the acceleration time is difficult to control, which often leads to the failure of acceleration driving.

[0008] In some high refresh rate, high resolution screen applications, the RC time constant of the channel load is close to the maximum drive time, which means that even if the Source driver buffer is completely ideal, with a large slew rate and a large bandwidth, it is difficult to drive the channel load voltage to the corresponding grayscale voltage within the maximum drive time.

[0009] In response to the above problems in the prior art, this patent proposes a new TFT_LCD display screen driving technology solution. Summary of the invention

[0010] In view of the technical defects existing in the prior art, the purpose of the present invention is to provide a dynamic acceleration drive control circuit for a high-resolution and high-refresh rate TFT_LCD display screen, which is used for driving a high-resolution and high-refresh rate TFT_LCD display screen, and is characterized in that at least adjacent first channel loads 31 and second channel loads 32 are used as a group of driving units, and the first channel loads 31 and the second channel loads 32 are controlled by a polarity exchange circuit 2 to alternately display positive and negative polarity voltages, and the input end of the polarity exchange circuit 2 is connected to a Source amplifier circuit 1, and the Source amplifier circuit 1 at least includes a positive Source amplifier 11 and a negative Source amplifier 12, and the output end of the polarity exchange circuit 2 is respectively connected to the input ends of the first channel load 31 and the second channel load 32, and is characterized in that the polarity exchange circuit 2 at least includes a second selector MUX2 for selecting the voltages of the positive polarity path intermediate nodes EX_P1 and EX_P2 to be sent to the positive Source amplifier 11 as feedback voltages, and a fourth selector MUX4 for selecting the voltages of the negative polarity path intermediate nodes EX_N1 and EX_N2 to be sent to the negative Source amplifier 12 as feedback voltages.

[0011] Preferably, the polarity exchange circuit 2 selects driving paths of opposite polarities for the first channel load 31 and the second channel load 32 through a polarity control signal. When the first channel load 31 selects a positive polarity driving path, the second channel load 32 selects a negative polarity driving path, and vice versa.

[0012] Preferably, the polarities of the first channel load 31 and the second channel load 32 are periodically exchanged for display.

[0013] Preferably, the two input ends of the second selector MUX2 are respectively connected to the two control circuits of the polarity exchange control circuit 2, and the output end of the second selector MUX2 is used to connect the positive Source amplifier 11; the two input ends of the fourth selector MUX4 are respectively connected to the two control circuits of the polarity control circuit 2, and the output end of the fourth selector MUX4 is used to connect the negative Source amplifier 12.

[0014] Preferably, the Source amplifier uses a floating translinear loop to control a Class AB rail-to-rail operational amplifier, so as to improve the bandwidth and driving capability of the operational amplifier.

[0015] Preferably, the reverse end of the positive Source amplifier 11 is connected to the first selector MUX1, and the input end of the first selector MUX1 is respectively connected to the output end of the positive Source amplifier 11 and the output end of the second selector MUX2; the reverse end of the negative Source amplifier 12 is connected to the third selector MUX3, and the input end of the third selector MUX3 is respectively connected to the output end of the negative Source amplifier 12 and the output end of the fourth selector MUX4.

[0016] Preferably, the first selector MUX1 and the second selector MUX2 select the voltage of the middle node EX_P1 of the positive polarity path and send it to the positive Source amplifier 11 as a feedback voltage to form an acceleration driving buffer of the positive Source amplifier 11, and the third selector MUX3 and the fourth selector MUX4 select the voltage of the middle node EX_N1 of the negative polarity path and send it to the negative Source amplifier 12 as a feedback voltage to form an acceleration driving buffer of the negative Source amplifier 12, and then the first selector MUX1 selects the output terminal voltage OUT_P of the positive Source amplifier 11 as the feedback voltage to form a stable driving buffer of the positive Source amplifier 11, and the third selector MUX3 selects the output terminal voltage OUT_N of the negative Source amplifier 12 as the feedback voltage to form a stable driving buffer of the negative Source amplifier 12.

[0017] Preferably, it also includes at least a zero adjustment resistor 4, the input end of the polarity exchange circuit 2 is connected to one end of the zero adjustment resistor 4, and the other end of the zero adjustment resistor 4 is connected to the output end of the positive Source amplifier 11 and / or the negative Source amplifier 12 circuit.

[0018] Preferably, at least a first discharge switch CS1 and a second discharge switch CS2 are included, the first discharge switch CS1 is connected to the positive polarity path intermediate nodes EX_P1 and EX_P2, the second discharge switch CS2 is connected to the negative polarity path intermediate nodes EX_N1 and EX_N2, and the other ends of the first discharge switch CS1 and the second discharge switch CS2 are grounded GND, which are used for the first channel load 31 and the second channel load 32 to discharge to the ground.

[0019] Preferably, each Source amplifier circuit 1 at least includes a PMOS output tube current sampling and current limiting circuit 15 and an NMOS output tube current sampling and current limiting circuit 16, which are used to increase the overshoot voltage maintenance time of the Source in the acceleration driving stage and suppress the reverse discharge of the power tube current. Each output tube current sampling and current limiting circuit at least includes a sampling tube, a current limiting tube, and an enabling tube. The gate of the PMOS output tube current sampling tube is connected to the gate of the output PMOS power tube of the Source amplifier circuit 1, the drain of the PMOS current limiting tube is connected to the source of the sampling tube, and the sampling The drain of the tube is connected to the source of the enable tube, and the drain of the enable tube is connected to the internal node B of OP, which is used to suppress the NMOS output power tube of the Source amplifier circuit 1 from opening reverse discharge too early; the gate of the NMOS output tube current sampling tube is connected to the gate of the output NMOS power tube of the Source amplifier circuit 1, the drain of the NMOS current limiting tube is connected to the source of the sampling tube, the drain of the sampling tube is connected to the source of the enable tube, and the drain of the enable tube is connected to the internal node A of OP, which suppresses the PMOS output power tube of the Source amplifier circuit 1 from opening reverse discharge too early.

[0020] Preferably, the Source amplifier circuit 1 does not have an internal Miller compensation capacitor, and a zero adjustment resistor 4 is connected in series to the output end of the Source amplifier circuit 1 to improve the small signal bandwidth of the operational amplifier.

[0021] According to another aspect of the present invention, the present invention provides a dynamic acceleration driving method for a high-resolution and high-refresh rate TFT-LCD display screen, which is used to perform dynamic acceleration driving according to the above-mentioned dynamic acceleration driving control circuit, and is characterized in that it includes the following steps:

[0022] a. By controlling the polarity exchange circuit 2 to select the corresponding voltage polarity drive path for the first channel load 31 and the second channel load 32;

[0023] b. After the Source amplifier circuit 1 is enabled, the positive Source amplifier 11 forms a positive Source acceleration drive buffer and the negative Source amplifier 12 forms a negative Source acceleration drive buffer by controlling the acceleration drive enable signal, and the first channel load 31 and the second channel load 32 are quickly driven to near the stable voltage;

[0024] c. When the capacitor voltage on the first channel load 31 and the second channel load 32 is close to or slightly exceeds the stable voltage, the positive Source amplifier 11 is controlled to form a stable driving buffer of the positive Source amplifier 11, and the negative Source amplifier 12 is controlled to form a stable driving buffer of the negative Source amplifier 12, and the first channel load 31 and the second channel load 32 are quickly driven to the stable voltage by using the stable driving buffer.

[0025] Preferably, in the step b, the acceleration driving stage is entered, and at least under the action of the large slew rate and the persistent overcharge voltage of the acceleration driving buffer, the first channel load 31 and the second channel load 32 are quickly driven to near the stable voltage.

[0026] Preferably, in step c, a stable driving stage is entered, and the first channel load 31 and the second channel load 32 are quickly driven to a stable voltage by means of a stable driving buffer having a large small signal bandwidth. Figure 1 , Figure 2 shown.

[0027] Preferably, in the first stage, i.e., the acceleration driving stage, the first selector MUX1 and the second selector MUX2 select the voltage of the middle node EX_P1 of the positive polarity path and send it to the positive Source amplifier 11 as a feedback voltage to form an acceleration driving buffer of the positive Source amplifier 11, and the third selector MUX3 and the fourth selector MUX4 select the voltage of the middle node EX_N1 of the negative polarity path and send it to the negative Source amplifier 12 as a feedback voltage to form an acceleration driving buffer of the negative Source amplifier 12. In the second stage, i.e., the stable driving stage, the first selector MUX1 selects the output terminal voltage OUT_P of the positive Source amplifier 11 as the feedback voltage to form a stable driving buffer of the positive Source amplifier 11, and the third selector MUX3 selects the output terminal voltage OUT_N of the negative Source amplifier 12 as the feedback voltage to form a stable driving buffer of the negative Source amplifier 12.

[0028] Preferably, during the acceleration driving process, the enable tubes in the output tube current sampling and current limiting circuit 15 and the output tube current sampling and current limiting circuit 16 are turned on, and during the stable driving process, the enable tubes in the output tube current sampling and current limiting circuit 15 and the output tube current sampling and current limiting circuit 16 are turned off.

[0029] Preferably, the third switch PS3 and the fourth switch PS4 in the polarity exchange circuit 2 are turned on, and the first switch PS1 and the second switch PS2 are turned off, and the negative polarity driving channel is selected for the first channel load 31; the seventh switch NS3 and the eighth switch NS4 in the polarity exchange circuit 2 are turned on, and the fifth switch NS1 and the sixth switch NS2 are turned off, and the positive polarity driving channel is selected for the second channel load 32; the EN enable signal of the Source amplifier circuit 1 changes from a high level to a low level, and the positive Source amplifier 11 and the negative Source amplifier 12 are turned off, and the output terminals OUT_P and OUT_N of the Source amplifier circuit 1 are both in a high impedance state. For specific invention contents, please refer to Figure 2 .

[0030] Preferably, the first discharge switch CS1 and the second discharge switch CS2 of the polarity exchange circuit 2 are turned on, and the negative charge on the capacitor in the first channel load 31 is discharged to GND through the eighth switch NS4 and the second discharge switch CS2, and the positive charge on the capacitor in the second channel load S2 is discharged to GND through the fourth switch PS4 and the first discharge switch CS1; when the first channel load 31 and the second channel load 32 are discharged to GND, the first discharge switch CS1 and the second discharge switch CS2 to the ground are closed to complete the discharge of the first channel load 31 and the second channel load 32 to the ground. For specific content of the invention, please refer to Figure 2 .

[0031] Preferably, the first switch PS1 and the second switch PS2 in the polarity exchange circuit 2 are turned on, the output end of the positive Source amplifier 11 is connected to the first channel load 31 through the zero adjustment resistor, the first switch PS1, and the second switch PS2, and the third switch PS3 and the fourth switch PS4 are turned off, so as to select the positive polarity drive channel for the first channel load 31, and the fifth switch NS1 and the sixth switch NS2 in the polarity exchange circuit are turned on, the output end of the negative Source amplifier 12 is connected to the second channel load 32 through the zero adjustment resistor, the fifth switch NS1, and the sixth switch NS2, and the seventh switch NS3 and the eighth switch NS4 are turned off, so as to select the negative polarity drive channel for the second channel load 32; at the same time, the first selector MUX1 is controlled to connect the OUT_P signal to the inverting input end of the positive Source amplifier 11 to form a positive drive buffer for the first channel load 31; the OUT_N signal is connected to the inverting input end of the negative Source amplifier 12 by controlling the third selector MUX3 to form a negative drive buffer for the second channel load 32. For specific invention contents, please refer to Figure 2 .

[0032] Preferably, the Source enable signal EN_OP changes from a low level to a high level, and the positive Source amplifier 11 and the negative Source amplifier 12 start to work. At this time, the positive drive buffer and the negative drive buffer start to initially drive the first channel load 31 and the second channel load 32. After the Source enable signal EN_OP changes from a low level to a high level for a clock delay, the current direction of the output stage power tube of the positive Source amplifier 11 and the negative Source amplifier 12 is basically determined, and the acceleration control signal TURBO changes from a low level to a high level, controlling the Source to enter the acceleration drive stage. For specific invention content, please refer to Figure 2 .

[0033] Preferably, the acceleration control signal TURBO changes from a low level to a high level, and controls the first selector MUX1 and the second selector MUX2 to select the positive polarity channel node EX_P1 to be connected to the reverse input terminal of the positive Source amplifier 11, thereby forming a positive polarity acceleration drive buffer, and controls the third selector MUX3 and the fourth selector MUX4 to select the negative polarity channel node EX_N1 to be connected to the reverse input terminal of the negative Source amplifier 12, thereby forming a negative polarity acceleration drive buffer; the positive polarity acceleration drive buffer and the negative polarity acceleration drive buffer are both in a phase under-stable state.

[0034] Preferably, in the acceleration driving stage, when the acceleration control signal TURBO changes from a low level to a high level, the power tube current sampling and current limiting enable EN are turned on inside the positive Source amplifier 11 and the negative Source amplifier 12 circuits. Due to the effect of the current limiting tube, the power consumption of the Source amplifier remains basically unchanged, and the sampling tube current is injected into nodes A and B respectively, which inhibits the power tube from opening and discharging reversely too early. The overshoot voltage maintenance time generated by the Source acceleration driving buffer will be significantly longer, which greatly enhances the acceleration driving speed of the first channel load 31 and the second channel load 32. By adjusting the pulse width of the control acceleration signal TURBO, when the channel load capacitor voltage approaches or slightly exceeds the stable voltage, the acceleration signal TURBO immediately changes from a high level to a low level, turning off the current sampling and current limiting circuit enable, and the acceleration driving stage of the Source for the first channel load 31 and the second channel load 32 is completed. For specific invention content, please refer to Figure 3 , Figure 4 .

[0035] Preferably, after the Source acceleration driving stage is completed, TURBO becomes a low level, and the first selector MUX1 is controlled to connect the OUT_P signal to the inverting input terminal of the positive Source amplifier 11 to form a positive polarity stable driving buffer; the third selector MUX3 is controlled to connect the OUT_N signal to the inverting input terminal of the negative Source amplifier 12 to form a negative polarity stable driving buffer, and the Source enters the stable driving stage of driving the first channel load 31 and the second channel load 32; at this stage, the Source positive polarity driving buffer and the Source negative polarity driving buffer are both in a phase stable state. Since the zero capacitance compensation has a large small signal bandwidth, the stable driving buffer quickly drives the first channel load 31 and the second channel load 32 to a stable voltage, completing the stable driving stage of the Source for the first channel load 31 and the second channel load 32. For specific invention content, please refer to Figure 2 .

[0036] Those skilled in the art will appreciate that the above steps a to c and the corresponding subsequent steps preferably constitute a complete technical solution for controlling dynamic acceleration drive, namely, the control method claimed in the present invention. Based on the technical solution provided by the present invention, the driving speed of the above channel load is increased by about 20-50%.

[0037] The Source dynamic acceleration driving solution provided by the present invention greatly improves the driving speed of the Source circuit. The specific scheme is to change the stability of the buffer by changing the feedback point of the amplifier (OP) circuit, and utilize the characteristics of high speed and large overshoot in the understable state of OP to make the output of the amplifier (OP) significantly higher than the input voltage to accelerate the driving of the channel load, and utilize the output tube sampling current to suppress the opening of another output tube, so that the overshoot voltage can be maintained for a sufficiently long time, and overcome the abnormal power consumption leakage caused by the overshoot voltage, and realize the independent, refined and dynamic acceleration driving function for each channel load. The implementation of the present invention does not increase the cost, volume, etc. of the existing circuit, and consumes less power. The implementation method of the present invention is simple and cost-effective, can effectively solve the above-mentioned technical problems, and has extremely high commercial value. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0039] Figure 1 A circuit diagram of a dynamic acceleration drive control circuit for a high-resolution and high-refresh-rate TFT_LCD display screen is shown in accordance with a specific embodiment of the present invention;

[0040] Figure 2 A circuit diagram of a dynamic acceleration drive control circuit for a high-resolution and high-refresh-rate TFT_LCD display screen according to a first embodiment of the present invention is shown;

[0041] Figure 3 A circuit diagram of a first channel load 31 in a dynamic acceleration drive control circuit of a high-resolution and high-refresh-rate TFT_LCD display screen according to a first embodiment of the present invention is shown;

[0042] Figure 4 A circuit diagram of a Source amplifier circuit 1 in a dynamic acceleration drive control circuit of a high-resolution and high-refresh-rate TFT_LCD display screen according to a first embodiment of the present invention;

[0043] Figure 5 A timing diagram of a control method for a dynamic acceleration drive control circuit applied to a high-resolution and high-refresh-rate TFT_LCD display screen according to a specific embodiment of the present invention is shown;

[0044] Figure 6 A timing diagram of a control method for a dynamic acceleration drive control circuit applied to a high-resolution and high-refresh-rate TFT_LCD display screen according to a specific embodiment of the present invention is shown;

[0045] Figure 7 A timing diagram of a control method for a dynamic acceleration drive control circuit applied to a high-resolution and high-refresh-rate TFT_LCD display screen according to a specific embodiment of the present invention is shown;

[0046] Figure 8 A timing diagram showing a control method of a dynamic acceleration drive control circuit applied to a high-resolution and high-refresh-rate TFT_LCD display screen according to a specific embodiment of the present invention; and

[0047] Fig. 9 A circuit diagram of a dynamic acceleration drive control circuit for a high-resolution and high-refresh-rate TFT_LCD display screen according to a second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0048] In order to better illustrate the technical solution of the present invention, the present invention is further described below in conjunction with the accompanying drawings.

[0049] refer to Figure 4 The embodiment shown shows a circuit diagram of a Source amplifier circuit 1, wherein the Source amplifier circuit 1 uses a floating transconductor linear loop to control a Class A and B rail-to-rail operational amplifier. In order to improve the small signal bandwidth of the operational amplifier, the internal phase compensation capacitor is cancelled, and a zero adjustment resistor 4 is connected in series at the output end of the operational amplifier for phase compensation. The driving of the channel loads 31 and 32 by the Source amplifier circuit 1 needs to go through two steps, namely, the first stage, i.e., the acceleration driving stage, and the second stage, i.e., the stable driving stage, to complete the voltage driving. It is characterized in that in the acceleration driving stage, the Source amplifier circuit 1 is in a phase-understable state, and a large overshoot voltage is generated during the driving process. The overshoot voltage is used to accelerate the driving of the channel load. In order to increase the maintenance time of the overshoot voltage and prevent the overshoot voltage from causing the amplifier (OP) output stage to discharge reversely and cause excessive power consumption, a current sampling and current limiting circuit is added to the two output tubes of the amplifier (OP); in the stable driving stage, the Source amplifier circuit 1 is in a phase-stable state, and the zero adjustment resistor compensation method has the characteristics of large bandwidth, so that the channel load quickly reaches a stable voltage.

[0050] Those skilled in the art understand that, in a preferred embodiment, a zero-adjusting compensation resistor is connected in series at the output end of the amplifier (OP): to allow the buffer in the stable driving stage to obtain a larger bandwidth and have sufficient phase margin, and to allow the buffer in the accelerated driving stage to be in an under-stable state, generating a larger overcharge voltage

[0051] The polarity exchange circuit is used to select and open the correct voltage polarity drive path for the first channel load 31 and the second channel load 32 through the polarity control signal. If one channel load selects the positive polarity drive path, the other must select the negative polarity drive path, and the polarities of the two channel loads 31 and 32 need to be periodically exchanged for display. When the first switch PS1, the second switch PS2, the fifth switch NS1, and the sixth switch NS2 are turned on, and the third switch PS3, the fourth switch PS4, the seventh switch NS3, and the eighth switch NS4 are turned off, the positive polarity drive path is selected for the first channel load 31, and the positive Source amplifier circuit 1 provides a positive voltage drive for the first channel load 31 through the zero adjustment resistor 4, the first switch PS1, and the second switch PS2. At the same time, a negative polarity drive path is selected for the second channel load 32, and the negative Source amplifier circuit 1 provides a positive voltage drive for the second channel load 32 through the zero adjustment resistor, the fifth switch NS1, and the sixth switch NS2. ; When the third switch PS3, the fourth switch PS4, the seventh switch NS3, and the eighth switch NS4 are turned on, and the first switch PS1, the second switch PS2, the fifth switch NS1, and the sixth switch NS2 are turned off, a negative polarity driving path is selected for the first channel load 31, and the negative Source amplifier circuit 1 provides a negative voltage drive for the first channel load S1 through the zero adjustment resistor 4, the seventh switch NS3, and the eighth switch NS4. At the same time, a positive polarity driving path is selected for the second channel load 32, and the positive Source amplifier circuit 1 provides a positive voltage drive for the second channel load 32 through the zero adjustment resistor 4, the third switch PS3, and the fourth switch PS4.

[0052] Each Source amplifier circuit 1 at least includes a PMOS output tube current sampling and current limiting circuit 15 and an NMOS output tube current sampling and current limiting circuit 16, which are used to sample the current of the two output power tubes of the Source amplifier circuit 1. The output tube current sampling and current limiting circuit is used to increase the output voltage slew rate of the acceleration drive stage and suppress the abnormal power consumption of the Source amplifier circuit 1. Each output tube current sampling and current limiting circuit at least includes a sampling tube, a current limiting tube, and an enabling tube. The gate of the PMOS output tube current sampling tube is connected to the gate of the output PMOS power tube of the Source amplifier circuit 1, the drain of the PMOS current limiting tube is connected to the source of the sampling tube, the drain of the sampling tube is connected to the source of the enabling tube, and the drain of the enabling tube is connected to the internal node B of the OP (such as Figure 2), inhibiting the NMOS output power tube of the Source amplifier circuit 1 from opening and discharging too early, and increasing the maintenance time of the positive overshoot voltage; the gate of the NMOS output tube current sampling tube is connected to the gate of the output NMOS power tube of the Source amplifier circuit 1, the drain of the NMOS current limiting tube is connected to the source of the sampling tube, the drain of the sampling tube is connected to the source of the enabling tube, and the drain of the enabling tube is connected to the internal node A of OP, inhibiting the PMOS output power tube of the Source amplifier circuit 1 from opening and discharging too early, and increasing the maintenance time of the negative overshoot voltage.

[0053] The Source amplifier circuit 1 does not have an internal Miller compensation capacitor for OP, and a zero adjustment resistor is connected in series at the output end of OP to obtain a large output slew rate in the acceleration driving stage and a large bandwidth and sufficient phase margin in the stable driving stage.

[0054] refer to Figures 5 to 8 , which shows a timing diagram of a control method of a dynamic acceleration drive control circuit applied to a high-resolution and high-refresh rate TFT_LCD display screen from different angles. Specifically, first perform step a. First, the polarity exchange circuit 2 is used to control the selection of the correct voltage polarity drive path for the channel loads 31 and 32. After the Source amplifier circuit 1 is enabled, the positive Source amplifier circuit 11 is controlled by the acceleration drive enable signal to form a positive Source acceleration drive buffer, and the negative Source amplifier circuit 12 is controlled to form a negative Source acceleration drive buffer, and enter the acceleration drive stage. Under the large slew rate and persistent overcharge voltage of the acceleration drive buffer, the first channel load 31 and the second channel load 32 are quickly driven to near the stable voltage.

[0055] Then execute step b. By adjusting the length of the acceleration driving time, when the capacitor voltage on the channel loads 31 and 32 is close to or slightly exceeds the stable voltage, the acceleration driving circuit is turned off, the positive Source amplifier circuit 11 is controlled to form a stable driving buffer of the positive Source, and the negative Source amplifier circuit 12 is controlled to form a stable driving buffer of the negative Source, and the stable driving stage is entered. The first channel load 31 and the second channel load 32 are quickly driven to the stable voltage by utilizing the characteristics of the stable driving buffer having a large small signal bandwidth.

[0056] The working time of the acceleration driving stage depends on the pulse width of the high level of the control signal TURBO. When the Source drives different screens, it is necessary to adjust the pulse width of the control signal TURBO according to the size of the channel load to achieve the best driving speed. For details, refer to Figures 5 to 7 The embodiment shown.

[0057] Further reference Figure 7 The embodiment shown further describes the process of the control method of the dynamic acceleration drive control circuit applied to the high-resolution and high-refresh rate TFT_LCD display screen. Take the first channel load 31 displaying a positive polarity voltage as an example:

[0058] A. The polarity of Source is exchanged in the row porch area. At this time, the Source amplifier circuit 1 does not work. The polarity exchange circuit selects to open the path between OUT_P and the first channel load 31, and closes the path between OUT_P and the second channel load 32. The first selector MUX1 selects OUT_P to send to the inverting terminal VIN of the Source amplifier circuit 1 as the feedback voltage;

[0059] B. Source amplifier circuit 1 is enabled and starts working. At this time, Source amplifier circuit 1 is an ordinary buffer. After about one clock cycle (e.g. 10ns), the internal current of the waiting amplifier (OP) is slightly stable, TURBO becomes 1, and the first selector MUX1 and the second selector MUX2 select VOP_EX1 to the inverting terminal VIN of Source amplifier circuit 1 as the feedback voltage through the acceleration control signal TURBO. At the same time, the output tube current sampling and current limiting circuit inside the amplifier (OP) are enabled, and the sampling current is injected into the A and B points of the load level ( Figure 2 , 3 ), so that the output tube is opened faster, and the buffer output will have a large voltage overshoot to accelerate the charging and discharging of the channel load;

[0060] C. After the set time, the TURBO signal changes from 1 to 0. At this time, the voltage on the channel load has been accelerated to near the stable voltage, and the acceleration circuit is turned off. That is, the first selector MUX1 and the second selector MUX2 select OUT_P to send to the inverting terminal VIN of the Source amplifier circuit 1 as the feedback voltage. At the same time, the OP internal output tube current sampling and current limiting circuit are turned off, and the buffer enters a stable working state. Since the OP compensation method has a very high small signal bandwidth, it can drive the channel load to quickly reach a stable voltage.

[0061] Furthermore, refer to Figure 8 The embodiment shown again shows the process of the control method of the dynamic acceleration drive control circuit applied to the high-resolution and high-refresh rate TFT_LCD display. Among them, it is a waveform diagram of the buffer output and the voltage change on the channel load when the dynamic acceleration function is turned on and off. From the comparison results, it can be seen that compared with the ordinary buffer drive, the driving time can be shortened by about 30% under the support of the dynamic acceleration drive technology.

[0062] Furthermore, refer to Figures 1 to 8 The embodiment shown discloses a circuit diagram and working principle of a control method of a dynamic acceleration drive control circuit of a high-resolution and high-refresh-rate TFT_LCD display screen. Specifically, by Fig. 9 Explanation:

[0063] 1. The SR limit problem: Figure 2 , Fig. 9 As shown, a zero adjustment resistor (SD_RES) is connected in series at the output end of the amplifier (OP), and the main pole of the loop is set at the output end of OP. At the same time, a zero point is introduced by the zero adjustment resistor to compensate the loop phase. In this way, the slew rate has nothing to do with the internal circuit of the amplifier (OP), but only depends on the charging and discharging speed of the output stage power tube of the amplifier (OP) to the load and the size of the load RC. However, since the zero adjustment resistor 4 is connected in series at the output end, SR will be adversely affected. This adverse effect will be explained in the second point below, and a specific solution is also given in the second point below.

[0064] 2. Dynamic acceleration drive: By changing the feedback point of the amplifier (OP) to change the stability of the buffer, the amplifier (OP) has the characteristics of high speed and large overshoot in the understable state, so that the output of the amplifier (OP) is significantly higher than the input voltage. At the same time, the output tube sampling current is used to suppress the opening of another output tube, so that the overshoot voltage can be maintained for a long enough time to achieve accelerated driving of the channel load. In the acceleration drive stage, the amplifier (OP) feedback voltage is the central node voltage VO_EX1 of the polarity exchange circuit. Under the action of negative feedback regulation, OP will dynamically adjust the output voltage higher or lower, which is equivalent to completely offsetting and shielding the adverse effects of the zero adjustment resistor (SD_RES) and the first-stage tube of the polarity exchange on SR. Therefore, the zero adjustment resistor has no effect on SR in the acceleration mode. In addition, the size and direction of the overshoot voltage generated in the acceleration drive are closely related to the size and positive and negative of the differential voltage input to the amplifier (OP), which means that not only a large slew rate SR can be achieved, but also the function of adaptive accelerated charging according to the size of the differential input voltage is realized, that is, in the initial process of the Source driving the channel load, the amplifier (OP) will dynamically adjust the output voltage of the amplifier (OP) to generate different degrees of overshoot voltage according to the gap between the residual voltage on the channel load of the previous row and the grayscale voltage to be displayed on the next row, so as to realize independent, refined and dynamic charging and discharging acceleration drive for each channel load.

[0065] 3. Adjustable acceleration driving time: Since the Source will eventually drive the voltage on the channel load to a stable grayscale voltage, this requires that the buffer cannot always work in an unstable state. When the channel load is accelerated to near the stable voltage, the feedback point of the amplifier (OP) is switched to the output end (OUT_P) of the OP to make the amplifier (OP) enter a stable working state. Since the amplifier (OP) uses an internal zero capacitor + zero adjustment resistor compensation method, compared with the traditional OP using an internal RC Miller compensation method, it will have a large small signal bandwidth. After the acceleration driving stage, the Source amplifier circuit 1 can quickly enter a stable state to drive the channel load to a stable voltage. Since the load sizes of different screens vary greatly, the time requirements for accelerated charging are also different. In practice, for screens of different specifications, the optimal acceleration time can be adjusted through digital adjustment.

[0066] 4. Overshoot voltage power loss problem: During the acceleration drive process, the Source amplifier circuit 1 is in an unstable state, and the output voltage of the amplifier (OP) will obviously exceed the input voltage. Under the effect of negative feedback, it is easy to quickly discharge the excess voltage through reverse regulation, which will cause abnormal power loss and affect the effect of acceleration drive. Figure 3 As shown, by sampling the current of the OP output tubes NM_0 and PM_0, the sampled current is introduced into the load level (A and B nodes, Figure 2 As shown in the figure, during negative acceleration driving, the power tube PM0 is inhibited from turning on, and during positive acceleration driving, the output tube NM1 is inhibited from turning on in advance, which will have a good suppression of the abnormal current leakage of the Source amplifier circuit 1, and the overshoot voltage can also be maintained for a long time. In addition, in order to prevent the problem of excessive sampling current causing the power consumption of the Source amplifier circuit 1 to increase during the acceleration driving process, the maximum sampling current needs to be limited, and the maximum current limit value should not exceed the tail current of the amplifier (OP).

[0067] Furthermore, combined with Figure 1 , Figure 2 , Figure 3 as well as Fig. 9 It can be seen from the embodiment shown that in the dynamic acceleration driving circuit structure provided by the present invention, whether the voltage on the channel load reaches a stable voltage during the Source driving channel load process depends on the probe5 point ( Figure 3The voltage of the 2-channel load drive is preferably used as an example to illustrate the specific technical solution implementation, wherein OP forms two positive and negative Source amplifier circuits, which respectively output positive grayscale voltage and negative grayscale voltage, and drive two channel loads, load 1 and channel load 2, after the polarity exchange circuit selects the correct polarity. Fig. 9 Source buffer driving circuit for 1 channel load is shown.

[0068] Part 1: Source amplifier circuit 1, the structure is a floating Class AB rail-to-rail operational amplifier. The special feature is that the internal RC compensation of the OP is cancelled, and the current sampling and maximum sampling current limiting functions of the output power tube are added, and the sampling current is injected into the load level corresponding to the other output tube. Finally, the output end is connected to the inverting input end to form a buffer.

[0069] Part 2: Polarity exchange circuit 2 and zero adjustment resistor 4. A zero adjustment resistor is connected in series at the OP output end to compensate for buffer stability. The resistance of the zero adjustment resistor is related to the channel load size. If the buffer phase margin is sufficient, the resistor can be cancelled. The polarity exchange circuit is used to select the polarity of the channel load. The buffer with the correct polarity is selected and connected to the first channel load 31 and the second channel load 32 to drive different channel loads.

[0070] The third part: The first selector MUX1 and the second selector MUX2 are used to select and switch the OP negative feedback voltage signal during the acceleration drive stage. The duration of the acceleration drive needs to be digitally adjusted according to the load size of different screens.

[0071] Furthermore, those skilled in the art understand that the present invention discloses the technical solutions claimed for protection in the present invention through the following aspects:

[0072] First, the current sampling and current limiting circuit inside the amplifier (OP): First, to make the amplifier (OP) have a large slew rate in the acceleration driving stage; second, to make the overcharge voltage of the understable buffer in the acceleration driving stage last longer; third, to prevent the power consumption of the Source OP from increasing in the acceleration driving stage, causing abnormal power consumption;

[0073] Second, the under-stable state buffer in the acceleration driving stage: mainly the MUX selects the polarity exchange circuit node voltage to feed back to the reverse input terminal of the amplifier (OP), using the overcharge voltage to accelerate the load driving, so that the load voltage is quickly driven to near the stable voltage;

[0074] Third, the stable buffer in the stable driving stage: mainly the selector MUX selects the output voltage of the amplifier (OP) and sends it to the reverse input of the amplifier (OP) for feedback, and uses the large small signal bandwidth of the buffer to quickly drive the load voltage to a stable voltage;

[0075] Fourth, cancel the internal Miller capacitor compensation and add a zero compensation resistor in series at the output of the amplifier (OP): This is to allow the buffer in the stable driving stage to obtain a larger bandwidth and sufficient phase margin, and to allow the buffer in the acceleration driving stage to be in an under-stable state, generating a larger overcharge voltage.

[0076] Furthermore, those skilled in the art understand that the dynamic acceleration drive control method claimed in the present invention mainly implements the acceleration drive through the following steps:

[0077] - After the source amplifier circuit 1 is enabled, wait until the internal current of OP is slightly stable, for example, in a preferred embodiment, it is processed according to about 10ns. According to the polarity judgment signal, MUX1 and MUX2 select the correct positive polarity exchange node voltage to the positive source amplifier, and MUX3 and MUX4 select the correct negative polarity exchange node voltage to the reverse input terminal of the negative source amplifier, forming an under-stable positive buffer and an under-stable negative buffer. At the same time, the current sampling and current limiting circuit enable tubes of the positive and negative source amplifiers are turned on, and the source enters the acceleration drive stage. Under the action of the large slew rate and overcharge voltage of the under-stable buffer, the output load is quickly driven to near the stable voltage.

[0078] -According to the size of the screen load, the time of the acceleration driving stage is digitally adjusted. When the voltage on the output load is close to the stable voltage value, the acceleration driving circuit is turned off. MUX1 selects the positive source amplifier output voltage to the inverting end of the positive source amplifier, and MUX3 selects the negative source amplifier output voltage to the inverting end of the negative OP to form a stable positive buffer and a stable negative buffer. The source enters the stable driving stage. Since the buffer has a large small signal bandwidth, the channel load is quickly driven to a stable voltage.

[0079] Furthermore, in the acceleration drive stage, the enable tube of the current sampling and current limiting circuit is turned on. When the amplifier (OP) is driven in the positive direction, the output PMOS tube sampling current is large, and the NMOS sampling current is small. The current sampling and current limiting circuit injects a small current into A and a large current into the B node, so that the output NMOS tube enters the shutdown state and the output PMOS tube is quickly turned on, so that the amplifier (OP) enters the positive acceleration drive state; when the amplifier (OP) is driven in the negative direction, the output PMOS tube sampling current is small, and the NMOS sampling current is large. The current sampling and current limiting circuit injects a large current into A and a small current into the B node, so that the output NMOS tube is accelerated to open, and the output PMOS tube is turned off, so that the amplifier (OP) enters the negative acceleration drive state.

[0080] The sampling current is injected into the A and B points of the load stage for two purposes: first, to allow the amplifier (OP) to have a large unidirectional slew rate during the acceleration drive phase; second, to allow the overcharge voltage generated by the understable buffer during the acceleration drive phase to be maintained for a long enough time.

[0081] Furthermore, those skilled in the art understand that the above Figure 1-Figure 9 A group of channel loads is taken as an example to illustrate the technical solution provided by the present invention. In practical applications, multiple groups of channel loads can be driven simultaneously, and the specific method is described in the content of the invention and the corresponding content of the specific embodiments.

[0082] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art may make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A dynamic acceleration drive control circuit for a high-resolution and high-refresh-rate TFT_LCD display screen, which is used to drive a high-resolution and high-refresh-rate TFT_LCD display screen, characterized in that: At least one adjacent first channel load (31) and second channel load (32) are used as a group of driving units. The first channel load (31) and the second channel load (32) are controlled by a polarity exchange circuit (2) to alternately display positive and negative polarity voltages. The input end of the polarity exchange circuit (2) is connected to a Source amplifier circuit (1). The Source amplifier circuit (1) at least includes a positive Source amplifier (11) and a negative Source amplifier (12). The output end of the polarity exchange circuit (2) is respectively connected to the input ends of the first channel load (31) and the second channel load (32). The polarity exchange circuit (2) is characterized in that the polarity exchange circuit (2) at least includes a second selector (MUX2) for selecting the voltage of the positive polarity path intermediate nodes EX_P1 and EX_P2 to be sent to the positive Source amplifier (11) as feedback voltage, and a fourth selector (MUX4) for selecting the voltage of the negative polarity path intermediate nodes EX_N1 and EX_N2 to be sent to the negative Source amplifier (12) as feedback voltage.

2. The dynamic acceleration drive control circuit according to claim 1, characterized in that: The polarity exchange circuit (2) selects drive paths of opposite polarities for the first channel load (31) and the second channel load (32) through a polarity control signal; when the first channel load (31) selects a positive polarity drive path, the second channel load (32) selects a negative polarity drive path, and vice versa.

3. The dynamic acceleration drive control circuit according to claim 1 or 2, characterized in that: The polarities of the first channel load (31) and the second channel load (32) are periodically exchanged for display.

4. The dynamic acceleration drive control circuit according to any one of claims 1 to 3, characterized in that: The two input ends of the second selector (MUX2) are respectively connected to the two control circuits of the polarity exchange control circuit (2), and the output end of the second selector (MUX2) is used to connect to the positive Source amplifier (11); the two input ends of the fourth selector (MUX4) are respectively connected to the two control circuits of the polarity control circuit (2), and the output end of the fourth selector (MUX4) is used to connect to the negative Source amplifier (12).

5. The dynamic acceleration drive control circuit according to any one of claims 1 to 4, characterized in that: The Source amplifier adopts a floating translinear loop to control a Class AB rail-to-rail structure operational amplifier, so as to improve the bandwidth and driving capability of the operational amplifier.

6. The dynamic acceleration drive control circuit according to claim 5, characterized in that: The reverse end of the positive Source amplifier (11) is connected to the first selector (MUX1), and the input end of the first selector (MUX1) is respectively connected to the output end of the positive Source amplifier (11) and the output end of the second selector (MUX2); the reverse end of the negative Source amplifier (12) is connected to the third selector (MUX3), and the input end of the third selector (MUX3) is respectively connected to the output end of the negative Source amplifier (12) and the output end of the fourth selector (MUX4).

7. The dynamic acceleration drive control circuit according to claim 5 or 6, characterized in that: The first selector (MUX1) and the second selector (MUX2) select the voltage of the middle node EX_P1 of the positive polarity path and send it to the positive Source amplifier (11) as a feedback voltage to form an acceleration driving buffer of the positive Source amplifier (11), and the third selector (MUX3) and the fourth selector (MUX4) select the voltage of the middle node EX_N1 of the negative polarity path and send it to the negative Source amplifier (12) as a feedback voltage to form an acceleration driving buffer of the negative Source amplifier (12), and then the first selector (MUX1) selects the output terminal voltage OUT_P of the positive Source amplifier (11) as a feedback voltage to form a stable driving buffer of the positive Source amplifier (11), and the third selector (MUX3) selects the output terminal voltage OUT_N of the negative Source amplifier (12) as a feedback voltage to form a stable driving buffer of the negative Source amplifier (12).

8. The dynamic acceleration drive control circuit according to any one of claims 1 to 7, characterized in that: At least a zero adjustment resistor (4) is included, the input end of the polarity exchange circuit (2) is connected to one end of the zero adjustment resistor (4), and the other end of the zero adjustment resistor (4) is connected to the output end of the positive Source amplifier (11) and / or the negative Source amplifier (12) circuit.

9. The dynamic acceleration drive control circuit according to any one of claims 1 to 8, characterized in that: The invention at least comprises a first discharge switch (CS1) and a second discharge switch (CS2), wherein the first discharge switch (CS1) is connected to the middle nodes EX_P1 and EX_P2 of the positive polarity path, and the second discharge switch (CS2) is connected to the middle nodes EX_N1 and EX_N2 of the negative polarity path, and the other ends of the first discharge switch (CS1) and the second discharge switch (CS2) are grounded GND, and are used for the first channel load (31) and the second channel load (32) to discharge to the ground.

10. The dynamic acceleration drive control circuit according to any one of claims 1 to 9, characterized in that: Each Source amplifier circuit (1) at least comprises a PMOS output tube current sampling and current limiting circuit (15) and an NMOS output tube current sampling and current limiting circuit (16), which are used to increase the overshoot voltage maintenance time of the Source in the acceleration driving stage and to suppress the reverse discharge of the power tube current. Each output tube current sampling and current limiting circuit at least comprises a sampling tube, a current limiting tube, and an enabling tube. The gate of the PMOS output tube current sampling tube is connected to the gate of the output PMOS power tube of the Source amplifier circuit (1), the drain of the PMOS current limiting tube is connected to the source of the sampling tube, the drain of the sampling tube is connected to the source of the enabling tube, and the drain of the enabling tube is connected to the internal node B of the OP, which is used to suppress the NMOS output power tube of the Source amplifier circuit (1) from opening too early and causing reverse discharge. The gate of the NMOS output tube current sampling tube is connected to the gate of the output NMOS power tube of the Source amplifier circuit (1), the drain of the NMOS current limiting tube is connected to the source of the sampling tube, the drain of the sampling tube is connected to the source of the enabling tube, and the drain of the enabling tube is connected to the OP internal node A, so as to suppress the PMOS output power tube of the Source amplifier circuit (1) from opening too early and discharging in reverse.

11. The dynamic acceleration drive control circuit according to any one of claims 1 to 10, characterized in that: The Source amplifier circuit (1) does not have an internal Miller compensation capacitor, and a zero adjustment resistor (4) is connected in series to the output end of the Source amplifier circuit (1) to improve the small signal bandwidth of the operational amplifier.

12. A dynamic acceleration driving method for a high-resolution and high-refresh rate TFT-LCD display screen, which is used for the dynamic acceleration driving in the dynamic acceleration driving control circuit according to any one of claims 1 to 11, characterized in that: The steps include: a. controlling the polarity exchange circuit (2) to select a corresponding voltage polarity drive path for the first channel load (31) and the second channel load (32); b. After the Source amplifier circuit (1) is enabled, the positive Source amplifier (11) forms a positive Source acceleration drive buffer and the negative Source amplifier (12) forms a negative Source acceleration drive buffer by controlling the acceleration drive enable signal, so as to quickly drive the first channel load (31) and the second channel load (32) to near a stable voltage; c. When the capacitor voltage on the first channel load (31) and the second channel load (32) approaches or slightly exceeds the stable voltage, the positive Source amplifier (11) is controlled to form a stable driving buffer of the positive Source amplifier (11), and the negative Source amplifier (12) is controlled to form a stable driving buffer of the negative Source amplifier (12), and the first channel load (31) and the second channel load (32) are quickly driven to the stable voltage by using the stable driving buffer.

13. The dynamic acceleration driving method according to claim 12, characterized in that: In step b, the acceleration drive phase is entered, and at least under the action of the large slew rate and persistent overcharge voltage of the acceleration drive buffer, the first channel load (31) and the second channel load (32) are quickly driven to near the stable voltage.

14. The dynamic acceleration driving method according to claim 12 or 13, characterized in that: In the step c, a stable driving phase is entered, and the first channel load (31) and the second channel load (32) are quickly driven to a stable voltage by virtue of the large small signal bandwidth of the stable driving buffer.

15. The dynamic acceleration driving method according to any one of claims 12 to 14, characterized in that: In the acceleration driving stage, the first selector (MUX1) and the second selector (MUX2) select the voltage of the middle node EX_P1 of the positive polarity path and send it to the positive Source amplifier (11) as a feedback voltage to form an acceleration driving buffer of the positive Source amplifier (11), and the third selector (MUX3) and the fourth selector (MUX4) select the voltage of the middle node EX_N1 of the negative polarity path and send it to the negative Source amplifier (12) as a feedback voltage to form an acceleration driving buffer of the negative Source amplifier (12). In the stable driving stage, the first selector (MUX1) selects the output terminal voltage OUT_P of the positive Source amplifier (11) as a feedback voltage to form a stable driving buffer of the positive Source amplifier (11), and the third selector (MUX3) selects the output terminal voltage OUT_N of the negative Source amplifier (12) as a feedback voltage to form a stable driving buffer of the negative Source amplifier (12).

16. The dynamic acceleration driving method according to any one of claims 12 to 15, characterized in that: During the acceleration driving process, the enable tubes in the output tube current sampling and current limiting circuit (15) and the output tube current sampling and current limiting circuit (16) are turned on, and during the stable driving stage, the enable tubes in the output tube current sampling and current limiting circuit (15) and the output tube current sampling and current limiting circuit (16) are turned off.

17. The dynamic acceleration driving method according to any one of claims 12 to 16, characterized in that: The third switch (PS3) and the fourth switch (PS4) in the polarity exchange circuit (2) are turned on, and the first switch (PS1) and the second switch (PS2) are turned off, so that a negative polarity driving channel is selected for the first channel load (31); the seventh switch (NS3) and the eighth switch (NS4) in the polarity exchange circuit (2) are turned on, and the fifth switch (NS1) and the sixth switch (NS2) are turned off, so that a positive polarity driving channel is selected for the second channel load (32); the EN enable signal of the Source amplifier circuit (1) is changed from a high level to a low level, so that the positive Source amplifier (11) and the negative Source amplifier (12) are turned off, and the output terminals OUT_P and OUT_N of the Source amplifier circuit (1) are both in a high impedance state.

18. The dynamic acceleration driving method according to any one of claims 12 to 17, characterized in that: The first discharge switch (CS1) and the second discharge switch (CS2) of the polarity exchange circuit (2) are turned on, and the negative charge on the capacitor in the first channel load (31) is discharged to GND through the eighth switch (NS4) and the second discharge switch (CS2), and the positive charge on the capacitor in the second channel load (S2) is discharged to GND through the fourth switch (PS4) and the first discharge switch (CS1); when the first channel load (31) and the second channel load (32) are discharged to GND, the first discharge switch (CS1) and the second discharge switch (CS2) to ground are turned off, and the first channel load (31) and the second channel load (32) are discharged to ground.

19. The dynamic acceleration driving method according to any one of claims 12 to 18, characterized in that: The first switch (PS1) and the second switch (PS2) in the polarity exchange circuit (2) are turned on, the output end of the positive source amplifier (11) is connected to the first channel load (31) through the first switch (PS1) and the second switch (PS2), and the third switch (PS3) and the fourth switch (PS4) are turned off, and the positive polarity driving channel is selected for the first channel load (31), the fifth switch (NS1) and the sixth switch (NS2) in the polarity exchange circuit are turned on, and the output end of the negative source amplifier (12) is connected to the first channel load (31) through the fifth switch (NS1) and the sixth switch (NS 2) connected to the second channel load (32), and the seventh switch (NS3) and the eighth switch (NS4) are closed, so as to select a negative polarity driving channel for the second channel load (32); at the same time, the first selector (MUX1) is controlled to connect the OUT_P signal to the inverting input terminal of the positive Source amplifier (11), so as to form a positive driving buffer of the first channel load (31); and the third selector (MUX3) is controlled to connect the OUT_N signal to the inverting input terminal of the negative Source amplifier (12), so as to form a negative driving buffer of the second channel load (32).

20. The dynamic acceleration driving method according to any one of claims 12 to 19, characterized in that: The Source enable signal EN_OP changes from a low level to a high level, and the positive Source amplifier (11) and the negative Source amplifier (12) start to work. At this time, the positive drive buffer and the negative drive buffer start to initially drive the first channel load (31) and the second channel load (32). After the Source enable signal EN_OP changes from a low level to a high level for a clock delay, the current direction of the output stage power tubes of the positive Source amplifier (11) and the negative Source amplifier (12) is basically determined, and the acceleration control signal TURBO changes from a low level to a high level, controlling the Source to enter the acceleration drive stage.

21. The dynamic acceleration driving method according to any one of claims 12 to 20, characterized in that: The acceleration control signal TURBO changes from a low level to a high level, controls the first selector (MUX1) and the second selector (MUX2) to select the positive polarity channel node EX_P1 to be connected to the reverse input end of the positive Source amplifier (11), thereby forming a positive polarity acceleration drive buffer, and controls the third selector (MUX3) and the fourth selector (MUX4) to select the negative polarity channel node EX_N1 to be connected to the reverse input end of the negative Source amplifier (12), thereby forming a negative polarity acceleration drive buffer; the positive polarity acceleration drive buffer and the negative polarity acceleration drive buffer are both in a phase under-stable state.

22. The dynamic acceleration driving method according to any one of claims 12 to 21, characterized in that: In the acceleration driving stage, when the acceleration control signal TURBO changes from a low level to a high level, the power tube current sampling and current limiting enable EN are turned on inside the positive Source amplifier (11) and the negative Source amplifier (12) circuits, and the sampling tube current is injected into the node A and the node B respectively. The overshoot voltage maintenance time generated by the Source acceleration driving buffer will be significantly prolonged, greatly enhancing the acceleration driving speed for the first channel load (31) and the second channel load (32). By adjusting the pulse width of the control acceleration signal TURBO, when the channel load capacitor voltage approaches or slightly exceeds the stable voltage, the acceleration signal TURBO immediately changes from a high level to a low level, and the current sampling and current limiting circuit enable are turned off. The acceleration driving stage of the Source for the first channel load (31) and the second channel load (32) is completed.

23. The dynamic acceleration driving method according to any one of claims 12 to 22, characterized in that: After the Source acceleration driving stage is completed, TURBO becomes a low level, and the first selector (MUX1) is controlled to connect the OUT_P signal with the inverting input terminal of the positive Source amplifier (11) to form a positive polarity stable driving buffer; the third selector (MUX3) is controlled to connect the OUT_N signal with the inverting input terminal of the negative Source amplifier (12) to form a negative polarity stable driving buffer. At this time, the Source enters the stable driving stage for driving the first channel load (31) and the second channel load (32). The Source positive polarity driving buffer and the Source negative polarity driving buffer are both in a phase stable state. Since the zero capacitance compensation has a large small signal bandwidth, the stable driving buffer quickly drives the first channel load (31) and the second channel load (32) to a stable voltage, completing the Source's stable driving stage for the first channel load (31) and the second channel load (32).

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