High electron mobility transistor epitaxial structure and method of fabricating the same

Abstract

The application provides a high electron mobility transistor epitaxial structure and a manufacturing method thereof, and comprises the following steps: providing a sapphire substrate; growing a first buffer layer doped with boron on the sapphire substrate; during the growth, the boron component in the reaction material is gradually reduced from a first preset value to 0 in a first preset time period, and the growth is continued for a second preset time period after the boron component is reduced to 0, so that in the first buffer layer, x gradually decreases, and the boron component gradually decreases to 0 from bottom to top; growing a second buffer layer of GaN without boron doping on the first buffer layer, the growth rate of the second buffer layer is lower than that of the first buffer layer, and the thickness of the second buffer layer is greater than that of the first buffer layer; and growing a GaN high resistance layer and a GaN epitaxial layer on the second buffer layer in sequence. Compared with the prior art, the application can effectively improve the defect density of the device, reduce the leakage current, and improve the stability and consistency of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to transistor epitaxial structures and their fabrication methods. Background Technology

[0002] Gallium nitride (GaN) has become a third-generation semiconductor material due to its advantages such as a large wide bandgap, low dielectric constant, high electron saturation velocity, spontaneous polarization, and thermal stability. AlGaN / GaN generates a two-dimensional electron gas with high electron density and high electron mobility at the material interface, resulting in high electron mobility transistors with significant advantages in high switching frequency, low on-resistance, high current density, and high operating temperature. Limited by the technology and cost of self-supporting substrates, GaN devices are mainly realized through heteroepitaxial growth. In the field of GaN-based power devices, Si substrates have advantages in terms of large size, process technology, and cost, and can also achieve the integration of microelectronic and optoelectronic devices, making them a candidate substrate material for GaN epitaxy and driving the commercialization of power devices. However, the large lattice mismatch (17%) and thermal mismatch (116%) between GaN and Si substrates, uncontrolled defect management, and high dislocation density lead to difficulties in epitaxial processes, making it difficult to suppress leakage current in the fabricated power devices, hindering the achievement of high breakdown voltage, and causing reliability and consistency issues. The mismatch dislocations of GaN and SiC substrates are only 3.5%, which can significantly reduce defects in the epitaxial layer, improve the quality of the epitaxial crystal, and reduce device leakage current. However, the high price of SiC substrates limits the large-scale mass production of GaN / SiC devices.

[0003] In comparison, GaN exhibits smaller lattice mismatch (16%) and thermal mismatch (25%) with sapphire substrates, lower substrate cost, and high insulating properties. Furthermore, the epitaxial growth technology of GaN materials is quite mature, easy to clean and process, and allows for stable large-size growth, making it a commonly used substrate for GaN material growth. It has also been commercialized in the field of light-emitting diodes (LEDs) and successfully achieved large-scale applications. However, the reliability and consistency of related devices still need further improvement.

[0004] Therefore, there is an urgent need for a transistor epitaxial structure and its fabrication method that can solve the above problems. Summary of the Invention

[0005] The purpose of this invention is to provide a high electron mobility transistor epitaxial structure and its fabrication method, which can effectively improve the defect density of the device, reduce leakage current, and improve the stability and consistency of the device.

[0006] To achieve the above objectives, the present invention provides a method for fabricating a high electron mobility transistor epitaxial structure, comprising: providing a sapphire substrate; growing a boron-doped first buffer layer on the sapphire substrate: during growth, the boron content in the reactive material is gradually reduced from a first preset value to 0 over a first preset time period, and after the boron content is reduced to 0, growth continues for a second preset time period, so that x gradually decreases in the first buffer layer and the boron content gradually decreases to 0 from bottom to top; growing a boron-free GaN second buffer layer on the first buffer layer, wherein the growth rate of the second buffer layer is lower than the growth rate of the first buffer layer, and the thickness of the second buffer layer is greater than the thickness of the first buffer layer; and sequentially growing a GaN high-resistivity layer and a GaN epitaxial stack on the second buffer layer.

[0007] Preferably, the first buffer layer is B, where x gradually decreases from bottom to top. x Q 1-x The first buffer layer is N, where element Q is a metallic element. Of course, the first buffer layer can also be other structures containing boron and nitrogen.

[0008] Specifically, element Q is aluminum or gallium, and the first buffer layer is B, where x gradually decreases from bottom to top. x Al 1-x N is a buffer layer, or B is a layer where x gradually decreases from bottom to top. x Ga 1-x N-buffer layer.

[0009] Preferably, when growing a boron-doped first buffer layer on the sapphire substrate, the V / III ratio is 1500, the first preset time is 5 to 25 minutes, the second preset time is 5 minutes, the first preset value is 0.6, the growth temperature is 850-1150 degrees Celsius, the growth pressure is 100-500 mbar, the growth rate is 100 nm / h to 300 nm / h, and the thickness of the first buffer layer after growth is 15-35 nm.

[0010] Preferably, when growing the second buffer layer, the growth temperature is 900 degrees Celsius, the growth pressure is 100 mbar, the growth rate is 2 μm / h, and the thickness of the second buffer layer after growth is 200-500 nm.

[0011] Preferably, the GaN high-resistivity layer is a C-doped GaN high-resistivity layer, and the GaN epitaxial stack consists of a GaN channel layer, a barrier layer, and a GaN cap layer grown sequentially on the GaN high-resistivity layer. The GaN high-resistivity layer can effectively suppress current from passing through the buffer layer, reduce leakage current, and improve device performance.

[0012] Specifically, when growing a C-doped GaN high-resistivity layer on the second buffer layer, ammonia and trimethylgallium are used as the nitrogen source and gallium source, respectively, and hexene is used as the dopant source. During growth, the growth temperature is slowly increased to 1000 degrees Celsius, and the growth gas pressure is slowly changed to 75 mbar. Ammonia, trimethylgallium, and hexene are introduced when the temperature and gas pressure change. After growth, the C doping concentration in the GaN high-resistivity layer is 5E18-1E19 cm⁻¹. -3 The thickness of the GaN high-resistivity layer is 500-1500nm.

[0013] Specifically, the sequential growth of a GaN channel layer, a barrier layer, and a GaN cap layer on the GaN high-resistivity layer includes: using ammonia and trimethylgallium as nitrogen and gallium sources, respectively, controlling the growth temperature at 1080 degrees Celsius and the growth pressure at 200 mbar, and growing the GaN channel layer on the GaN high-resistivity layer at a growth rate of 2.5 μm / h, with a thickness of 150-300 nm; and using ammonia, trimethylgallium, and trimethylaluminum as nitrogen, gallium, and aluminum sources, respectively, increasing the temperature from 1080 degrees Celsius to 1090 degrees Celsius, decreasing the growth pressure from 200 mbar to 50 mbar, and growing Al on the GaN channel layer at a growth rate of 0.8 μm / h. y Ga 1-y The barrier layer of N, wherein y ranges from 18% to 28% and has a thickness of 20-30 nm; the trimethylaluminum source is turned off while the barrier layer is being grown, and growth continues for a third preset duration to grow the GaN cap layer on the barrier layer, wherein the GaN cap layer has a thickness of 3-5 nm.

[0014] The present invention also provides a high electron mobility transistor epitaxial structure, comprising a sapphire substrate, a boron-doped first buffer layer, a boron-free GaN second buffer layer, a GaN high-resistivity layer, and a GaN epitaxial stack formed sequentially on the sapphire substrate; the boron composition of the first buffer layer gradually decreases from bottom to top, and a boron-free buffer layer of a predetermined thickness is formed on the top of the first buffer layer.

[0015] Preferably, the first buffer layer is B, where x gradually decreases from bottom to top. x Q 1-x N is a buffer layer, and element Q is a metallic element.

[0016] Specifically, element Q is aluminum or gallium, and the first buffer layer is B, where x gradually decreases from bottom to top. x Al 1-x N is a buffer layer, or B is a layer where x gradually decreases from bottom to top. x Ga 1-x N buffer layer, the top of the first buffer layer is an AlN layer or a GaN layer.

[0017] Preferably, the sapphire substrate has a thickness of 550-1000 μm, the first buffer layer has a thickness of 15-35 nm, and the second buffer layer has a thickness of 200-500 nm.

[0018] Preferably, the GaN high-resistivity layer is a C-doped GaN high-resistivity layer, and the GaN epitaxial stack consists of a GaN channel layer, a barrier layer, and a GaN cap layer grown sequentially on the GaN high-resistivity layer. The GaN high-resistivity layer can effectively suppress current from passing through the buffer layer, reduce leakage current, and improve device performance.

[0019] Specifically, the C doping concentration in the GaN high-resistivity layer is 5E18-1E19 cm⁻¹. -3 The thickness of the GaN high-resistivity layer is 500-1500nm.

[0020] Specifically, the barrier layer is Al y Ga 1-y N-barrier layer.

[0021] More specifically, the GaN channel layer has a thickness of 150-300 nm, and the Al y Ga 1-y The y range in the N barrier layer is 18% to 28%, and the thickness is 20-30 nm. The thickness of the GaN cap layer is 3-5 nm.

[0022] Compared with existing technologies, because the first buffer layer contains boron, its lattice mismatch with the sapphire substrate is extremely low, even lower than that between gallium nitride and sapphire. Therefore, this invention, by depositing a boron-doped first buffer layer on the sapphire substrate before epitaxial GaN, and controlling the ratio of boron in the growth of the first buffer layer, can achieve a buffer layer with strict lattice matching on the sapphire substrate. Then, the boron doping content is gradually reduced until it is zero, and finally a boron-free buffer structure is grown. Compared with directly growing GaN, this invention can significantly reduce lattice mismatch, improve the crystal quality of the epitaxial layer, thereby reducing dislocations and device leakage, improving the consistency of GaN high electron mobility transistors, and enhancing their performance under high current density and high voltage. Attached Figure Description

[0023] Figure 1 This is a flowchart of the fabrication method of the high electron mobility transistor epitaxial structure in Embodiment 1 of the present invention.

[0024] Figure 2 This is a structural diagram of the high electron mobility transistor epitaxial structure in Embodiment 1 of the present invention.

[0025] Figure 3This is a structural diagram of the high electron mobility transistor epitaxial structure in Embodiment 2 of the present invention. Detailed Implementation

[0026] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0027] Example 1:

[0028] refer to Figure 1 The present invention discloses a method for fabricating a high electron mobility transistor epitaxial structure, including steps S1 to S5.

[0029] S1, a sapphire substrate 10 is provided. In this embodiment, the thickness of the sapphire substrate 10 is 550-1000 μm. The diameter of the sapphire substrate 10 is 100 or 150 mm.

[0030] S2, a boron-doped first buffer layer 20 is grown on the sapphire substrate 10.

[0031] In step S2, during growth, the boron content in the reaction material is gradually reduced from a first preset value to 0 over a first preset time period. After the boron content reaches 0, growth continues for a second preset time period, so that in the first buffer layer 20, x gradually decreases, and the boron content gradually decreases to 0 from bottom to top. When growing the boron-doped first buffer layer 20 on the sapphire substrate 10, the V / III ratio is 1500, the first preset time period is 5 to 25 minutes, the second preset time period is 5 minutes, the first preset value x is 0.6, the growth temperature is 850-1150 degrees Celsius, the growth pressure is 100-500 mbar, the growth rate is 100 nm / h to 300 nm / h, and the thickness of the first buffer layer 20 after growth is 15-35 nm.

[0032] Specifically, in this embodiment, the first buffer layer 20 is B, where x gradually decreases from bottom to top. x Al 1-x The first buffer layer 20 has an N-type buffer layer, with an AlN layer on top. Alternatively, the first buffer layer 20 can also be any other structure containing boron and nitrogen. The first preset value is 0.6, the first preset duration is 25 minutes, and the second preset duration is 5 minutes.

[0033] B x Al 1-xDuring the growth of the N buffer layer: ammonia, triethylboron, and trimethylaluminum were used as the nitrogen source, boron source, and aluminum source, respectively, with a V / III ratio of 1500. The B component was initially fixed at 0.6, then linearly reduced to 0 over a 25-minute growth period. After reaching 0, AlN growth continued for 5 minutes. The growth temperature was fixed at 900 degrees Celsius, the growth pressure at 100 mbar, and the growth rate was controlled at 100 nm / h. In other words, throughout the entire production process, the growth rate gradually increased to around 100 nm / h, but did not exceed 100 nm / h. B x Al 1-x The thickness of the N buffer layer is 30 nm. The thickness of the AlN layer on top of the first buffer layer 20 is approximately 5 nm.

[0034] S3, a second buffer layer 30 of undoped boron GaN is grown on the first buffer layer 20. The growth rate of the second buffer layer 30 is lower than the growth rate of the first buffer layer 20, and the thickness of the second buffer layer 30 is greater than the thickness of the first buffer layer 20.

[0035] When growing the second buffer layer 30, ammonia and trimethylgallium were used as the nitrogen source and gallium source, respectively. The growth temperature was 900 degrees Celsius, the growth pressure was 100 mbar, and the growth rate was 2 μm / h. After growth, the thickness of the second buffer layer 30 was 200-500 nm. In this embodiment, the thickness of the second buffer layer 30 was 350 nm.

[0036] S4, a GaN high-resistivity layer 40 is sequentially grown on the second buffer layer 30.

[0037] The GaN high-resistivity layer 40 is a C-doped GaN high-resistivity layer 40. The GaN high-resistivity layer 40 can effectively suppress current from passing through the buffer layer, reduce leakage current, and improve device performance.

[0038] Specifically, when growing a C-doped GaN high-resistivity layer 40 on the second buffer layer 30, ammonia and trimethylgallium are used as the nitrogen source and gallium source, respectively, and hexene is used as the dopant source. During growth, the growth temperature is slowly increased to 1000 degrees Celsius, and the growth gas pressure is slowly changed to 75 mbar. Ammonia, trimethylgallium, and hexene are introduced when the temperature and gas pressure change. The C doping concentration can be obtained by SIMS testing. After growth, the C doping concentration in the GaN high-resistivity layer 40 is 5E18-1E19 cm⁻¹. -3 The GaN high-resistivity layer has a thickness of 500-1500nm.

[0039] S5, a GaN epitaxial stack 50 is grown on the GaN high-resistivity layer 40.

[0040] The GaN epitaxial stack 50 consists of a GaN channel layer 51, a barrier layer 52, and a GaN cap layer 53 sequentially grown on the GaN high-resistivity layer 40.

[0041] Specifically, the sequential growth of a GaN channel layer 51, a barrier layer 52, and a GaN cap layer 53 on the GaN high-resistivity layer 40 includes: using ammonia and trimethylgallium as nitrogen and gallium sources, respectively; controlling the growth temperature at 1080 degrees Celsius and the growth pressure at 200 mbar; and growing the GaN channel layer 51 on the first buffer layer 20 at a growth rate of 2.5 μm / h. The thickness of the GaN channel layer 51 is 150-300 nm. Then, using ammonia, trimethylgallium, and trimethylaluminum as nitrogen, gallium, and aluminum sources, respectively; increasing the temperature from 1080 degrees Celsius to 1090 degrees Celsius; decreasing the growth pressure from 200 mbar to 50 mbar; and growing Al on the GaN channel layer 51 at a growth rate of 0.8 μm / h. y Ga 1-y The barrier layer 52 of N has a y range of 18% to 28% and a thickness of 20-30 nm. The thickness of the barrier layer 52 can be measured by XRR, and the composition of the barrier layer 52 can be obtained by XRD. Under the conditions of growing the barrier layer 52, the trimethylaluminum source is turned off, and growth continues for a third preset time to grow the GaN cap layer 53 on the barrier layer 52. The thickness of the GaN cap layer 53 is 3-5 nm, and the thickness of the GaN cap layer 53 can be measured by XRR.

[0042] refer to Figure 1 and Figure 2 High electron mobility transistor epitaxial structures can be fabricated using the above method. This high electron mobility transistor epitaxial structure includes a sapphire substrate 10, a boron-doped first buffer layer 20, a boron-free GaN second buffer layer 30, a GaN high-resistivity layer, and a GaN epitaxial stack 50 sequentially formed on the sapphire substrate 10; the boron content of the first buffer layer 20 gradually decreases from bottom to top, and a boron-free buffer layer of a predetermined thickness is formed on top of the first buffer layer 20. The first buffer layer 20 has a boron content that gradually decreases from bottom to top. x Al 1-x N-layer buffer. The top of the first buffer layer 20 is an AlN layer.

[0043] The sapphire substrate 10 has a thickness of 550-1000 μm, the first buffer layer 20 has a thickness of 15-35 nm, and the second buffer layer 30 has a thickness of 200-500 nm. The GaN high-resistivity layer 40 is a C-doped GaN high-resistivity layer 40, and the GaN epitaxial stack 50 consists of a GaN channel layer 51, a barrier layer 52, and a GaN cap layer 53 sequentially grown on the GaN high-resistivity layer 40.

[0044] In this embodiment, the C doping concentration in the GaN high-resistivity layer 40 is 5E18-1E19 cm⁻¹. -3 The GaN high-resistivity layer 40 has a thickness of 500-1500 nm. The barrier layer 52 is Al. y Ga 1-y N-barrier layer 52. The thickness of the GaN channel layer 51 is 150-300 nm, and the Al... y Ga 1-y The y range in the N barrier layer 52 is 18% to 28%, and the thickness is 20-30 nm. The thickness of the GaN cap layer 53 is 3-5 nm.

[0045] Example 2:

[0046] refer to Figure 3 Unlike Embodiment 1, in this embodiment, the first buffer layer 20a is B, where x gradually decreases from bottom to top. x Ga 1-x The first buffer layer 20 has an N-layer buffer, with a GaN layer on top. The first preset value x is 0.6, the first preset duration is 15 minutes, and the second preset duration is 5 minutes.

[0047] B x Ga 1-x During the growth of the N buffer layer: ammonia, triethylboron, and trimethylaluminum were used as nitrogen source, boron source, and aluminum source, respectively, with a V / III ratio of 1500. The B composition was initially fixed at 0.6, and then linearly reduced to 0 over a growth period of 15 min. Finally, GaN was grown for 5 min, with the growth temperature fixed at 900 degrees Celsius, the growth pressure at 100 mbar, and the growth rate less than or equal to 300 nm / h.

[0048] The lattice mismatches of BN, AlN, and GaN with the sapphire substrate 10 are -8.9%, 13%, and 16%, respectively. It can be seen that if GaN is grown directly on the sapphire substrate 10, the high lattice mismatch will result in a high defect density, which will affect the device performance. The lattice mismatch between BN and sapphire is a negative value, while the lattice mismatch between AlN and GaN and sapphire is a positive value. Therefore, this invention achieves a strictly lattice-matched buffer layer on the sapphire substrate 10 by first depositing a boron-doped buffer layer (first buffer layer 20, 20a) on the sapphire substrate 10 before epitaxial GaN, and by controlling the B ratio during the growth of the first buffer layer 20, 20a. Then, the boron doping composition is gradually reduced until it is zero, and finally an AlN layer or GaN is grown directly. Compared with direct GaN growth, this invention can significantly reduce lattice mismatch, improve the crystal quality of the epitaxial layer, thereby reducing dislocations and device leakage current, improving the consistency of GaN high electron mobility transistors, and enhancing the operating performance under high current density and high voltage.

[0049] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for fabricating a high electron mobility transistor epitaxial structure, the method comprising: The application comprises the following steps: ​ a sapphire substrate is provided; a first buffer layer doped with boron is grown on the sapphire substrate; during the growth, the boron component in the reaction material is gradually reduced from a first preset value x to 0 in a first preset time period, and the growth is continued for a second preset time period after the boron component is reduced to 0, so that the x gradually decreases in the first buffer layer, and the boron component gradually decreases from bottom to top to 0; a second buffer layer of GaN without boron doping is grown on the first buffer layer, the growth rate of the second buffer layer is lower than that of the first buffer layer, and the thickness of the second buffer layer is greater than that of the first buffer layer; a GaN high resistance layer and a GaN epitaxial stack are sequentially grown on the second buffer layer.

2. The method of claim 1, wherein: The first buffer layer is B with x gradually decreasing from bottom to top x Q 1-x N buffer layer, element Q is a metal element.

3. The method of claim 2, wherein: Element Q is element aluminum or element gallium, the first buffer layer is B x Al 1-x N buffer layer or B with x gradually decreasing from bottom to top x Ga 1-x N buffer layer.

4. The method of claim 3, wherein: During the growth of the first buffer layer doped with boron on the sapphire substrate, the V / III ratio is 1500, the first preset time period is 5-25 minutes, the second preset time period is 5 minutes, the first preset value x is 0.6, the growth temperature is 850-1150 degrees Celsius, the growth pressure is 100-500 mbar, the growth rate is 100 nm / h to 300 nm / h, and the thickness of the first buffer layer after the growth is completed is 15-35 nm.

5. The method of claim 1, wherein: During the growth of the second buffer layer, the growth temperature is 900 degrees Celsius, the growth pressure is 100 mbar, the growth rate is 2 μm / h, and the thickness of the second buffer layer after the growth is completed is 200-500 nm.

6. The method of claim 1, wherein: The GaN high resistance layer is a C-doped GaN high resistance layer, and the GaN epitaxial stack is a GaN channel layer, a barrier layer and a GaN cap layer sequentially grown on the GaN high resistance layer.

7. The method of claim 6, wherein: In the growth of the C-doped GaN high resistance layer on the second buffer layer, ammonia and trimethyl gallium are used as nitrogen source and gallium source respectively, hexene is used as doping source, the growth temperature is slowly increased to 1000 degrees Celsius during growth, the growth pressure is slowly changed to 75 mbar, and ammonia, trimethyl gallium and hexene are started to be introduced when the temperature and pressure are changed. -3 The C-doping concentration in the GaN high resistance layer after growth is 5E18-1E19 cm-3, and the thickness of the GaN high resistance layer is 500-1500 nm.

8. The method of claim 6, wherein: The sequential growth of the GaN channel layer, the barrier layer and the GaN cap layer on the GaN high resistance layer specifically comprises: ammonia and trimethyl gallium are used as the nitrogen source and the gallium source respectively, the growth temperature is controlled at 1080 degrees Celsius, the growth pressure is controlled at 200 mbar, the GaN channel layer is grown on the GaN high resistance layer at a growth rate of 2.5 μm / h, and the thickness of the GaN channel layer is 150-300 nm; Growth of AlGaN barrier layer on the GaN channel layer at a growth rate of 0.8 μm / h under the condition of using ammonia, trimethyl gallium, trimethyl aluminum as nitrogen source, gallium source, aluminum source, respectively, raising the temperature from 1080 degrees Celsius to 1090 degrees Celsius, and lowering the growth pressure from 200 mbar to 50 mbar. y Ga 1-y N, the barrier layer, wherein the range of y is 18% to 28%, and the thickness is 20-30 nm. the trimethyl aluminum source is turned off under the conditions of growing the barrier layer, and the GaN cap layer is grown on the barrier layer for a third preset time period, and the thickness of the GaN cap layer is 3-5 nm.

9. A high electron mobility transistor epitaxial structure, characterized by: The high electron mobility transistor epitaxial structure is made by the method of any one of claims 1-8, comprising a sapphire substrate, a first buffer layer doped with boron, a second buffer layer of GaN without boron doping, a GaN high resistance layer and a GaN epitaxial stack sequentially formed on the sapphire substrate; the boron component of the first buffer layer gradually decreases from bottom to top, and a preset thickness of the buffer layer without boron is formed at the top of the first buffer layer.

10. The high electron mobility transistor epitaxial structure of claim 9, wherein: The first buffer layer is B with x gradually decreasing from bottom to top x Q 1-x N buffer layer, element Q is a metal element.

11. The high electron mobility transistor epitaxial structure of claim 10, wherein: Element Q is element aluminum or element gallium, the first buffer layer is B x Al 1-x N buffer layer or B with x gradually decreasing from bottom to top x Ga 1-x N buffer layer, the top of the first buffer layer is an AlN layer or a GaN layer.

12. The high electron mobility transistor epitaxial structure of claim 9, wherein: The thickness of the sapphire substrate is 550-1000 μm, the thickness of the first buffer layer is 15-35 nm, and the thickness of the second buffer layer is 200-500 nm.

13. The high electron mobility transistor epitaxial structure of claim 10, wherein: The GaN high resistance layer is a C-doped GaN high resistance layer, and the GaN epitaxial stack is a GaN channel layer, a barrier layer and a GaN cap layer sequentially grown on the GaN high resistance layer.

14. The high electron mobility transistor epitaxial structure of claim 13, wherein: The C doping concentration in the GaN high resistance layer is 5E18-1E19 cm -3 The thickness of the GaN high resistance layer is 500-1500 nm.

15. The high electron mobility transistor epitaxial structure of claim 13, wherein: The barrier layer is Al y Ga 1-y N barrier layer.

16. The high electron mobility transistor epitaxial structure of claim 15, wherein: The thickness of the GaN channel layer is 150-300 nm, the Al y Ga 1-y The range of y in the GaN barrier layer is 18-28%, the thickness is 20-30 nm, and the thickness of the GaN cap layer is 3-5 nm.

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