Pulse chip heat dissipation structure based on phase change material and TTSV structure and preparation method

Abstract

The present invention discloses a pulse chip heat dissipation structure based on a phase-change material and a TTSV structure, and a method for fabricating the structure. The method comprises: depositing a SiO2 hard mask on a silicon substrate; removing specific areas of the SiO2 hard mask through photolithography and etching until a predetermined etching window is formed on the surface of the silicon substrate; etching the exposed silicon substrate in the etching window to form a quadrangular pyramid-shaped heat dissipation through-silicon via (TSV); and sequentially depositing a first TiN barrier layer, a VO2 phase-change material layer, a second TiN barrier layer, a Cu seed layer, and a Cu filler layer on the TSV. The disclosed pulse chip heat dissipation structure based on a phase-change material and a TTSV structure and its fabrication method achieve efficient heat dissipation in pulsed, high-energy-density chips.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing, and in particular relates to a pulse chip heat dissipation structure based on phase change material and TTSV structure and a preparation method of the pulse chip heat dissipation structure based on phase change material and TTSV structure. Background Art

[0002] High-energy-density chips often generate heat not at a constant power level, but rather in pulses over short periods of time, followed by a period of dormancy. Therefore, it is crucial to conduct the heat generated during these periods away from the chip within a certain timeframe, thereby improving the chip's heat dissipation capabilities and thermal reliability.

[0003] Advances in system integration technology have enabled the realization of multi-layer stacking and increased integration, while also making high-density packaging play an increasingly important role in device manufacturing. However, with the significant increase in power density, chip heat dissipation has gradually become a major factor limiting chip reliability. Through-silicon via (TSV) technology is a circuit interconnection technology that interconnects chips by creating vertical conductions between chips and between wafers. Thermal through-silicon via (TTSV) applies this technology to chip heat dissipation and is gaining increasing attention due to its significant effect on heat dissipation. However, conventional TTSV structures have a small volume and density, and their heat storage / heat dissipation capacity is limited, making them unable to meet the needs of high-energy density heat dissipation. Increasing the volume of TTSV will lead to a decrease in the mechanical performance of the chip.

[0004] Therefore, further improvements are made to the above problems. Summary of the Invention

[0005] The main purpose of the present invention is to provide a pulse chip heat dissipation structure and preparation method based on phase change material and TTSV structure, so as to achieve efficient heat dissipation in pulsed high energy density chips.

[0006] To achieve the above objectives, the present invention provides a method for preparing a pulse chip heat dissipation structure based on phase change material and TTSV structure, comprising the following steps:

[0007] Step S1: depositing a SiO2 hard mask on a silicon substrate;

[0008] Step S2: removing specific areas of the SiO2 hard mask through photolithography and etching processes until a preset etching window is formed on the surface of the silicon substrate;

[0009] Step S3: etching the exposed silicon substrate in the etching window through an etching process to form a square pyramid-shaped heat dissipation through silicon via;

[0010] Step S4: depositing a first TiN barrier layer on the heat dissipation through silicon via;

[0011] Step S5: depositing a VO2 phase change material layer on the first TiN barrier layer;

[0012] Step S6: depositing a second TiN barrier layer on the VO2 phase change material layer;

[0013] Step S7: depositing a Cu seed layer on the second TiN barrier layer;

[0014] Step S8: Filling Cu on the Cu seed layer to obtain a Cu filling layer, and finally completing the preparation.

[0015] As a further preferred technical solution of the above technical solution, the thickness of the SiO2 hard mask is 300 nm.

[0016] As a further preferred technical solution of the above technical solution, the size of the etching window is 240 μm×240 μm.

[0017] As a further preferred technical solution of the above technical solution, in step S3, the depth of the heat dissipation silicon via is 120 μm, the etching solution used is TMAH solution with a concentration of 2.5 wt%-5 wt%, and the etching temperature is 80° C.-100° C.

[0018] As a further preferred technical solution of the above technical solution, TiN is deposited on the heat dissipation silicon via by magnetron sputtering or atomic layer deposition to form a first TiN barrier layer;

[0019] Depositing VO2 on top of the first TiN barrier layer by magnetron sputtering to form a VO2 phase change material layer;

[0020] Depositing TiN on the VO2 phase change material layer by magnetron sputtering or atomic layer deposition to form a second TiN barrier layer;

[0021] depositing Cu on the second TiN barrier layer by magnetron sputtering to form a Cu seed layer;

[0022] The Cu seed layer is filled with Cu by electroplating to fill the heat dissipation through silicon via.

[0023] To achieve the above objectives, the present invention also provides a pulse chip heat dissipation structure based on phase change material and TTSV structure, including a silicon substrate, a first TiN barrier layer, a VO2 phase change material layer, a second TiN barrier layer, a Cu seed layer and a Cu filling layer, which are stacked in sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of step S1.

[0025] Figure 2 is a schematic diagram of step S2.

[0026] Figure 3 is a schematic diagram of step S3.

[0027] Figure 4 This is a structural diagram of the pulse chip heat dissipation structure based on phase change material and TTSV structure.

[0028] Reference numerals include: 11: silicon substrate; 12: SiO2 hard mask; 41: first TiN barrier layer; 42: VO2 phase change material layer; 43: second TiN barrier layer; 44: Cu seed layer; 45: Cu filling layer. DETAILED DESCRIPTION

[0029] The following description is intended to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are for illustrative purposes only, and those skilled in the art will readily appreciate other obvious variations. The basic principles of the present invention defined in the following description may be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.

[0030] In the preferred embodiment of the present invention, those skilled in the art should note that the silicon substrate and the like involved in the present invention may be regarded as prior art.

[0031] Preferred embodiment.

[0032] like Figure 1-4 As shown, the present invention discloses a method for preparing a pulse chip heat dissipation structure based on phase change material and TTSV structure, comprising the following steps:

[0033] Step S1: Figure 1 As shown, a SiO2 hard mask 12 is deposited on a silicon substrate 11. The thickness of the silicon substrate 11 is 150 μm. The deposition method of the SiO2 hard mask layer is thermal oxidation, and the thickness is 300 nm.

[0034] Step S2: Figure 2 As shown, a specific area of ​​the SiO2 hard mask 12 is removed by photolithography and etching processes until a preset etching window is formed on the surface of the silicon substrate 11. The etching window size is 240 μm×240 μm, and the etching solution used is BHF solution;

[0035] Step S3: Figure 3As shown, the anisotropic etching properties of Si are utilized to etch the exposed silicon substrate in the etching window through an etching process, thereby forming a tetrahedral-shaped heat dissipation silicon via. It should be noted that, in order to ensure the anisotropic etching, the crystal orientation of the silicon substrate 11 is (100)

[0036] Step S4: Figure 4 As shown, a first TiN barrier layer 41 is deposited on the heat dissipation silicon via by magnetron sputtering or atomic layer deposition, with a thickness of 70 nm;

[0037] Step S5: Figure 4 As shown, a VO2 phase change material layer 42 is deposited on the first TiN barrier layer 41 by magnetron sputtering at a deposition temperature of 630°C and a thickness of 200 nm. It should be noted that in order to obtain a purer VO2 phase change material layer 42, the target material used is V2O5, and the oxygen partial pressure during the sputtering process is about 0.5%.

[0038] Step S6: Figure 4 As shown, a second TiN barrier layer 43 is deposited on the VO2 phase change material layer 42 by magnetron sputtering or atomic layer deposition, with a thickness of 70 nm;

[0039] Step S7: Figure 4 As shown, a Cu seed layer 44 is deposited on the second TiN barrier layer 43 by magnetron sputtering, with a thickness of 150 nm;

[0040] Step S8: Figure 4 As shown, Cu is filled on the Cu seed layer 44 to obtain a Cu filling layer 45. The filling method is electroplating, and the thickness is equivalent to the depth of the heat dissipation silicon via, which is about 120μm, and the preparation is finally completed.

[0041] Specifically, the thickness of the SiO2 hard mask 12 is 300 nm.

[0042] More specifically, the size of the etching window is 240 μm×240 μm.

[0043] Furthermore, in step S3, the depth of the heat dissipation silicon via is 120 μm, the outer opening side length is 240 μm, and the bottom side length is 70 μm; the etching solution used is TMAH solution with a concentration of 2.5wt%-5wt%, and the etching temperature is 80°C-100°C.

[0044] Furthermore, TiN is deposited on the heat dissipation through silicon via by magnetron sputtering or atomic layer deposition to form a first TiN barrier layer;

[0045] Depositing VO2 on top of the first TiN barrier layer by magnetron sputtering to form a VO2 phase change material layer;

[0046] Depositing TiN on the VO2 phase change material layer by magnetron sputtering or atomic layer deposition to form a second TiN barrier layer;

[0047] depositing Cu on the second TiN barrier layer by magnetron sputtering to form a Cu seed layer;

[0048] The Cu seed layer is filled with Cu by electroplating to fill the heat dissipation through silicon via.

[0049] The present invention also discloses a pulse chip heat dissipation structure based on phase change material and TTSV structure, including a silicon substrate, a first TiN barrier layer, a VO2 phase change material layer, a second TiN barrier layer, a Cu seed layer and a Cu filling layer, which are stacked in sequence.

[0050] Preferably, the thickness of the first TiN barrier layer is 70nm; the thickness of the VO2 phase change material layer is 200nm, and the sputtering temperature is 630°C; the thickness of the second TiN barrier layer is 70nm; the thickness of the Cu seed layer is 150nm; and the thickness of the Cu filling layer is 120μm.

[0051] For the present invention:

[0052] The heat dissipation method is as follows: a pyramid-shaped heat dissipation through silicon via array is prepared on the silicon substrate on the back of the chip by anisotropic etching, and a barrier layer and a phase change material layer are first deposited in the heat dissipation through silicon via to quickly store the heat during the heating cycle, and then a barrier layer is deposited again and filled with heat dissipation material with high thermal conductivity to dissipate the heat stored in the phase change material layer during the non-heating cycle. This method utilizes the phase change material to absorb the heat generated by the chip during the heat generation cycle, and the structure of the thermally conductive through silicon via to efficiently conduct the heat to the outside of the chip, thereby improving the heat dissipation performance. The present invention has the advantages of high heat dissipation efficiency, low process cost, and high process reliability, and greatly solves the heat dissipation problem of chips that generate heat in pulse form. The combination of VO2 phase change material and the new TTSV structure effectively increases the efficiency of heat dissipation of high energy density chips during pulses, while ensuring the stability of the chip's mechanical structure.

[0053] It is worth mentioning that the technical features such as the silicon substrate involved in the patent application of this invention should be regarded as prior art. The specific structure, working principle and possible control method and spatial arrangement method of these technical features can be selected by conventional means in the field and should not be regarded as the inventive point of this patent. This patent will not be further elaborated.

[0054] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent replacements for some of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a pulse chip heat dissipation structure based on phase change material and TTSV structure, characterized in that: The following steps are involved: Step S1: depositing a SiO2 hard mask on a silicon substrate; Step S2: removing specific areas of the SiO2 hard mask through photolithography and etching processes until a preset etching window is formed on the surface of the silicon substrate; Step S3: etching the exposed silicon substrate in the etching window through an etching process to form a square pyramid-shaped heat dissipation through silicon via; Step S4: depositing a first TiN barrier layer on the heat dissipation through silicon via; Step S5: depositing a VO2 phase change material layer on the first TiN barrier layer; Step S6: depositing a second TiN barrier layer on the VO2 phase change material layer; Step S7: depositing a Cu seed layer on the second TiN barrier layer; Step S8: Filling Cu on the Cu seed layer to obtain a Cu filling layer, and finally completing the preparation.

2. The method for preparing a pulse chip heat dissipation structure based on phase change material and TTSV structure according to claim 1, characterized in that: The thickness of the SiO2 hard mask is 300 nm.

3. The method for preparing a pulse chip heat dissipation structure based on phase change material and TTSV structure according to claim 1, characterized in that: The size of the etching window is 240 μm×240 μm.

4. The method for preparing a pulse chip heat dissipation structure based on phase change material and TTSV structure according to claim 1, characterized in that: In step S3, the depth of the heat dissipation through silicon via is 120 μm, the etching solution used is TMAH solution with a concentration of 2.5 wt % to 5 wt %, and the etching temperature is 80° C. to 100° C.

5. The method for preparing a pulse chip heat dissipation structure based on phase change material and TTSV structure according to claim 1, characterized in that: Depositing TiN on the heat dissipation through silicon via by magnetron sputtering or atomic layer deposition to form a first TiN barrier layer; Depositing VO2 on top of the first TiN barrier layer by magnetron sputtering to form a VO2 phase change material layer; Depositing TiN on the VO2 phase change material layer by magnetron sputtering or atomic layer deposition to form a second TiN barrier layer; depositing Cu on the second TiN barrier layer by magnetron sputtering to form a Cu seed layer; The Cu seed layer is filled with Cu by electroplating to fill the heat dissipation through silicon via.

6. A pulse chip heat dissipation structure based on phase change material and TTSV structure, applied to the preparation method of a pulse chip heat dissipation structure based on phase change material and TTSV structure according to any one of claims 1 to 5, characterized in that: The invention comprises a silicon substrate, a first TiN barrier layer, a VO2 phase change material layer, a second TiN barrier layer, a Cu seed layer and a Cu filling layer which are designed to be stacked in sequence.

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