Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, which comprises the following steps: providing a substrate, wherein the substrate comprises a chip area and a suspended area around the chip area, the suspended area supports a part to be connected to the substrate beyond the chip area on the substrate; forming a dielectric layer and a wiring layer in the dielectric layer on the substrate; wherein the first groove is formed in the suspended area before or after or at the same time when the dielectric layer is formed, and the height difference between the first groove and the surface of the chip area is within a set specification. The application can avoid the influence of the newly added suspended area outside the chip area on the stability of the photolithography process and the planarization process.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] For 2.5D packaging process, an interposer will have an overhang area in addition to a chip area. The overhang area on the interposer is used to expand the chip area, and compared with the interposer without the overhang area, the interposer with the overhang area can carry more chips, and the overhang area supports the part of the chip to be connected to the interposer which exceeds the chip area on the interposer.

[0003] Generally, the overhang area has no any pattern, so that in the production process of the interposer, the area where the overhang area is located will form a higher protrusion due to the load effect of the CMP process, and then affect the subsequent photolithography process; and due to the existence of the protrusion, the metal material (such as copper) at the corner of the bottom of the protrusion is not easy to be polished, and then the residual of the metal material is caused.

[0004] Therefore, how to avoid the influence of the overhang area on the photolithography process and the polishing process is a problem to be solved at present. SUMMARY

[0005] The present application aims to provide a semiconductor device and a manufacturing method thereof, so that the newly added overhang area outside the chip area can be avoided to affect the stability of the photolithography process and the planarization process.

[0006] To achieve the above-mentioned purpose, the present application provides a manufacturing method of a semiconductor device, comprising:

[0007] providing a substrate, the substrate comprising a chip area and an overhang area located around the chip area, the overhang area supporting the part of the chip to be connected to the substrate which exceeds the chip area on the substrate;

[0008] forming a dielectric layer and a wiring layer located in the dielectric layer on the substrate;

[0009] wherein, before and after forming the dielectric layer or at the same time, a first groove is formed in the overhang area, and the height difference between the first groove and the surface of the chip area is within a set specification.

[0010] Optionally, before forming the dielectric layer, the first groove is formed in the substrate located in the overhang area, and the first groove extends from the surface of the substrate to the inside of the substrate.

[0011] Optionally, the dielectric layer and the wiring layer are at least two layers;

[0012] After any one of the dielectric layers is formed, the first groove is formed in any one of the dielectric layers located in the suspended region.

[0013] Optionally, forming a dielectric layer on the substrate and a wiring layer located within the dielectric layer includes:

[0014] A dielectric layer is formed on the substrate;

[0015] A via is formed in the dielectric layer located in the chip region;

[0016] The through-hole is filled with a conductive material, which also extends to cover the surface of the dielectric layer.

[0017] The conductive material on the dielectric layer is removed using a planarization process to form a wiring layer in the via.

[0018] Optionally, before forming a dielectric layer and a wiring layer within the dielectric layer on the substrate, a conductive structure is formed within the substrate located in the chip region, and the wiring layer is electrically connected to the conductive structure.

[0019] Optionally, before forming the conductive structure within the substrate of the chip region, a second groove is formed within the substrate of the chip region, the second groove serving as an alignment mark.

[0020] The present invention also provides a semiconductor device, comprising:

[0021] The substrate includes a chip region and a suspended region surrounding the chip region, the suspended region supporting the portion of the chip region to be connected to the substrate that extends beyond the chip region on the substrate;

[0022] A dielectric layer and a wiring layer, wherein the dielectric layer is formed on the substrate and the wiring layer is formed within the dielectric layer;

[0023] The suspended area has a first groove, such that the height difference between the surface of the suspended area and the surface of the chip area is within a set specification.

[0024] Optionally, the first groove is formed within the substrate located in the suspended region, and the first groove extends from the surface of the substrate into the substrate.

[0025] Optionally, both the dielectric layer and the wiring layer have at least two layers; the first groove is formed in any one of the dielectric layers located in the suspended region.

[0026] Optionally, a conductive structure is formed within the substrate located in the chip region, and the wiring layer is electrically connected to the conductive structure.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] 1. The semiconductor device manufacturing method of the present invention includes: providing a substrate, the substrate including a chip region and a suspended region surrounding the chip region, the suspended region supporting a portion of the chip region to be connected to the substrate that extends beyond the chip region; forming a dielectric layer and a wiring layer within the dielectric layer on the substrate; wherein, before, during, or simultaneously with the formation of the dielectric layer, a first groove is formed in the suspended region, the height difference between the first groove and the surface of the chip region being within a predetermined specification. This allows the stability of the photolithography and planarization processes to be avoided by the newly added suspended region outside the chip region.

[0029] 2. The semiconductor device of the present invention includes: a substrate comprising a chip region and a suspended region surrounding the chip region, the suspended region supporting a portion of the chip region to be connected to the substrate extending beyond the chip region; a dielectric layer and a wiring layer, the dielectric layer being formed on the substrate and the wiring layer being formed within the dielectric layer; wherein the suspended region has a first groove, such that the height difference between the surface of the suspended region and the surface of the chip region is within a predetermined specification. This prevents the newly added suspended region outside the chip region from affecting the stability of the photolithography and planarization processes. Attached Figure Description

[0030] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0031] Figures 2a to 2k yes Figure 1 A schematic diagram of the manufacturing method of the semiconductor device shown;

[0032] Figure 3 This is a distribution diagram of the chip area and the floating area according to an embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of a raised area in a suspended region.

[0034] Among them, the appendix Figures 1 to 4 The annotations in the attached figures are explained as follows:

[0035] 101-Substrate; 102-First insulating layer; 11-Conductive structure; 111-Second insulating layer; 121-First groove; 122-Second groove; 131-First dielectric layer; 1311-First patterned photoresist layer; 141-First wiring layer; 1411-First via; 132-Second dielectric layer; 133-Third dielectric layer; 142-Second wiring layer; 1421-Second via. Detailed Implementation

[0036] The objects, advantages and features of the present application will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings in which:

[0037] One embodiment of the present application provides a method for manufacturing a semiconductor device, referring to Figure 1 , Figure 1 is a flow chart of the method for manufacturing a semiconductor device according to one embodiment of the present application, the method for manufacturing a semiconductor device comprises:

[0038] Step S1, providing a substrate, the substrate comprises a chip area and a suspension area around the chip area, the suspension area supports the part to be connected to the substrate beyond the chip area on the substrate;

[0039] Step S2, forming a dielectric layer and a wiring layer in the dielectric layer on the substrate; wherein, before or after forming the dielectric layer or at the same time, a first groove is formed in the suspension area, the height difference between the first groove and the surface of the chip area is within the set specification.

[0040] The method for manufacturing a semiconductor device provided by the embodiment will be described in more detail below, Figures 2a to 2k , Figure 3 and Figure 4 Figures 2a to 2k and Figure 4 are Figure 3 longitudinal section view along the direction of AA'.

[0041] According to step S1, a substrate is provided, the substrate comprises a chip area A1 and a suspension area A2 around the chip area A1, the suspension area A2 supports the part to be connected to the substrate beyond the chip area A1 on the substrate.

[0042] The substrate can be a single-layer structure or a multi-layer stacked structure, and the material of the substrate can be a semiconductor material or a non-semiconductor material.

[0043] In one embodiment, as shown in Figure 2a , the substrate comprises a substrate 101 and a first insulating layer 102 formed on the surface of the substrate 101.

[0044] ​The substrate 101 can be made of semiconductor materials such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors, and can also include layered substrates such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI) or silicon-on-silicon germanium, and can also include materials other than semiconductor materials, such as glass and the like.

[0045] The suspended area A2 can be located between some adjacent chip areas A1, as shown in Figure 3 The suspended area A2 can be located between some adjacent chip areas A1, as shown in

[0046] The substrate further includes a scribe lane area (not shown) surrounding the chip area A1 and located between the chip area A1 and the suspended area A2.

[0047] In an embodiment, the chip to be connected to the substrate can be a chip.

[0048] According to step S2, a dielectric layer and a wiring layer in the dielectric layer are formed on the substrate. Before or after the dielectric layer is formed, or simultaneously, a first recess 121 is formed in the suspended area A2, and the height difference between the surface of the chip area A1 and the first recess 121 is within a specified specification.

[0049] As shown in Figure 2c Before the dielectric layer and the wiring layer in the dielectric layer are formed on the substrate, a conductive structure 11 is formed in the substrate in the chip area A1, and the wiring layer is electrically connected to the conductive structure 11.

[0050] A second insulating layer 111 can be formed between the conductive structure 11 and the substrate. In an embodiment, the second insulating layer 111 also extends to the surface of the substrate.

[0051] In the embodiment shown in Figure 2c The step of forming the conductive structure 11 includes: first, etching the first insulating layer 102 and the substrate 101 to form a via; then, forming a second insulating layer 111 on the inner wall of the via, and the second insulating layer 111 also extends to the surface of the first insulating layer 102; then, depositing a conductive material in the via, and the conductive material also covers the second insulating layer 111 above the first insulating layer 102; then, using a planarization process (such as a chemical mechanical polishing process) to remove the conductive material outside the via, and the conductive material in the via serves as the conductive structure 11.

[0052] Due to the loading effect of the planarization process, the surface of the overhang region A2 is higher than the surface of the chip region Al. In one embodiment, before forming the conductive structure 11, the first recess 121 is formed in the substrate of the overhang region A2, as shown in FIG. 1C. The first recess 121 extends from the surface of the substrate into the substrate. The subsequently formed second insulating layer 111 or the dielectric layer can fill the first recess 121. Figure 2b When the second insulating layer 111 fills the first recess 121, the dielectric layer is formed on the second insulating layer 111; when the second insulating layer 111 does not fill the first recess 121, the dielectric layer fills the first recess 121. Figure 2c

[0053] The surface of the overhang region A2 and the surface of the chip region Al refer to the surface of the dielectric layer of the overhang region A2 and the surface of the dielectric layer of the chip region Al, respectively. Alternatively, the surface of the overhang region A2 and the surface of the chip region Al can refer to the surface of the substrate of the overhang region A2 and the surface of the substrate of the chip region Al, respectively.

[0054] The method for manufacturing the semiconductor device further comprises forming a second recess 122 in the substrate of the chip region Al, and the second recess 122 is used as an alignment mark.

[0055] Preferably, the first recess 121 and the second recess 122 are formed simultaneously before forming the conductive structure 11. The second recess 122 is used as an alignment mark, and the depth of the second recess 122 is generally tens of nanometers. The first recess 121 and the second recess 122 are formed simultaneously to make the depth of the first recess 121 the same as the depth of the second recess 122 in the same process. The subsequently formed second insulating layer 111 or the dielectric layer can fill the first recess 121 and the second recess 122, so that the height difference between the surface of the overhang region A2 and the surface of the chip region Al after the planarization process is within a specified range, thereby simplifying the process and saving costs. In other embodiments, the first recess 121 and the second recess 122 can not be formed simultaneously. For example, the second recess 122 is formed before forming the conductive structure 11, and the first recess 121 is formed after forming the conductive structure 11.

[0056] ​It is to be noted that the height difference between the surface of the overhang region A2 and the surface of the chip region A1 within the set specification includes: the surface of the overhang region A2 is flush with the surface of the chip region A1; or, the surface of the overhang region A2 is lower or higher than the surface of the chip region A1, and the height difference between the surface of the overhang region A2 and the surface of the chip region A1 is within the set specification.

[0057] As shown in Figures 2d to 2k The dielectric layer and the wiring layer in the dielectric layer are formed on the substrate. The dielectric material forming the dielectric layer or the conductive material forming the wiring layer is formed on the chip region A1 and the overhang region A2 of the substrate at the same time; after the formation of the wiring layer, the part of the conductive material in the chip region A1 is reserved to form the conductive layer, and the conductive material in the overhang region A2 is removed. When the substrate forms the conductive structure 11, the dielectric layer covers the conductive structure 11, and the wiring layer is electrically connected with the conductive structure 11.

[0058] If the dielectric layer and the wiring layer are both one layer, after the formation of the dielectric layer, the wiring layer is formed in the dielectric layer of the chip region A1. If the surface of the overhang region A2 is higher than the surface of the chip region A1, the first groove 121 is formed in the dielectric layer of the overhang region A2.

[0059] If the dielectric layer and the wiring layer are both at least two layers, after the formation of each layer of the dielectric layer, the wiring layer is formed in the dielectric layer of the chip region A1. If after the formation of any one layer of the dielectric layer, the surface of the overhang region A2 is higher than the surface of the chip region A1, the first groove 121 is formed in the any one layer of the dielectric layer of the overhang region A2. Or, the first groove 121 can also be formed in any at least two layers of the dielectric layer of the overhang region A2.

[0060] Taking the dielectric layer as two layers (i.e. the first dielectric layer 131 and the second dielectric layer 132) and the wiring layer as two layers (i.e. the first wiring layer 141 and the second wiring layer 142) as an example, the steps of forming the dielectric layer and the wiring layer in the dielectric layer on the substrate include:

[0061] The step of forming the first wiring layer 141 in the first dielectric layer 131 of the chip region A1 can include: first, as shown in Figure 2dAs shown, a first dielectric layer 131 is formed on the chip region A1 and the overhang region A2 of the substrate, the first dielectric layer 131 covers the conductive structure 11 and the second insulating layer 111, and if the first recess 121 and the second recess 122 are formed in the substrate, the first dielectric layer 131 can also fill the first recess 121 and the second recess 122; a first photoresist layer is formed on the first dielectric layer 131, and the first photoresist layer is patterned to form a first patterned photoresist layer 1311, as shown in Figure 2e As shown, the first patterned photoresist layer 1311 includes a pattern of the first wiring layer 141 located in the chip region A1; as shown in Figure 2f As shown, the first patterned photoresist layer 1311 is used as a mask to etch the first dielectric layer 131 of the chip region A1 to form a first via 1411 penetrating through the first dielectric layer 131; as shown in Figure 2g As shown, the first patterned photoresist layer 1311 is removed; a conductive material is formed in the first via 1411, and the conductive material covers the first dielectric layer 131; as shown in Figure 2h As shown, a planarization process (such as a chemical mechanical polishing process) is used to remove the conductive material on the first dielectric layer 131 to form a first wiring layer 141 in the first via 1411.

[0062] The step of forming the second wiring layer 142 in the second dielectric layer 132 of the chip region A1 can include: first, as shown in Figure 2i As shown, a second dielectric layer 132 is formed on the first dielectric layer 131, the second dielectric layer 132 covers the first wiring layer 141 located in the chip region A1 and the overhang region A2, and if the first recess 121 is formed in the first dielectric layer 131 of the overhang region A2, the second dielectric layer 132 can also fill the first recess 121; a second photoresist layer is formed on the second dielectric layer 132, and the second photoresist layer is patterned to form a second patterned photoresist layer (not shown), the second patterned photoresist layer includes a pattern of the second wiring layer 142 located in the chip region A1; as shown in Figure 2j As shown, the second patterned photoresist layer is used as a mask to etch the second dielectric layer 132 of the chip region A1 to form a second via 1421 in the second dielectric layer 132; a conductive material is formed in the second via 1421, and the conductive material covers the second dielectric layer 132; as shown in Figure 2k As shown, a planarization process (such as a chemical mechanical polishing process) is used to remove the conductive material on the second dielectric layer 132 to form a second wiring layer 142 in the second via 1421.

[0063] The first recess 121 can be formed in the first dielectric layer 131 of the overhang region A2 before or after or simultaneously with forming the first wiring layer 141 in the first dielectric layer 131 of the chip region Al. For example, the first patterned photoresist layer 1311 can further include the pattern of the first recess 121 in the overhang region A2. The step of forming the first patterned photoresist layer 1311 including the pattern of the first wiring layer 141 in the chip region Al and the pattern of the first recess 121 in the overhang region A2 can include: shielding the first photoresist layer of the overhang region A2 with a shield and performing an exposure process on the first photoresist layer of the chip region Al with a chip region mask; shielding the exposed first photoresist layer of the chip region Al with a shield and performing an exposure process on the first photoresist layer of the overhang region A2 with a first mask; and developing the exposed first photoresist layer of the chip region Al and the overhang region A2 to form the first patterned photoresist layer 1311. The first recess 121 can be formed by etching the first dielectric layer 131 of the overhang region A2 using the first patterned photoresist layer 1311. In other embodiments, the pattern of the first wiring layer 141 in the chip region Al and the pattern of the first recess 121 in the overhang region A2 can be formed in different layers of photoresist, respectively.

[0064] The first recess 121 can be formed in the second dielectric layer 132 of the overhang region A2 before or after or simultaneously with forming the second wiring layer 142 in the second dielectric layer 132 of the chip region Al. For example, the second patterned photoresist layer can further include the pattern of the first recess 121 in the overhang region A2. The step of forming the second patterned photoresist layer including the pattern of the second wiring layer 142 in the chip region Al and the pattern of the first recess 121 in the overhang region A2 can include: shielding the second photoresist layer of the overhang region A2 with a shield and performing an exposure process on the second photoresist layer of the chip region Al with a chip region mask; shielding the exposed second photoresist layer of the chip region Al with a shield and performing an exposure process on the second photoresist layer of the overhang region A2 with a first mask; and developing the exposed second photoresist layer of the chip region Al and the overhang region A2 to form the second patterned photoresist layer. The first recess 121 can be formed by etching the second dielectric layer 132 of the overhang region A2 using the second patterned photoresist layer. In other embodiments, the pattern of the second wiring layer 142 in the chip region Al and the pattern of the first recess 121 in the overhang region A2 can be formed in different layers of photoresist, respectively.

[0065] The chip area photo mask is designed according to the pattern of the wiring layer to be formed in the chip area, and the patterns of different wiring layers are different, and the chip area photo mask corresponding to the wiring layer can be different.

[0066] Since the chip area A1 is used for carrying chips and realizing conductive interconnections, the suspended area A2 is used for carrying chips, therefore, the chip area A1 is formed with conductive interconnection structures (including the conductive structure 11 and the wiring layers, etc.), and the suspended area A2 has less conductive interconnection structures, then, in the process of making the conductive interconnection structures, when the chip area A1 and the suspended area A2 are grinded by using a planarization process (for example, a chemical mechanical grinding process) (for example, when the conductive structure 11 is made, the conductive material outside the via is removed by grinding, when the first wiring layer 141 is made, the conductive material on the first dielectric layer 131 is removed by grinding, and when the second wiring layer 142 is made, the conductive material on the second dielectric layer 132 is removed by grinding), due to the load effect of the planarization process, when the chip area A1 is grinded to the target thickness, the suspended area A2 will be raised; and with the increase of the number of layers of the conductive interconnection structures and the number of layers of the insulating structures, the raised part will be higher and higher.

[0067] And when the developing process is performed, the exposed photoresist will be cleaned and removed; if the suspended area A2 has a raised part, and the height of the raised part exceeds the set specification (for example, the height difference between the top surface of the dielectric layer of the suspended area A2 and the top surface of the dielectric layer of the chip area A1 exceeds the set specification), it will cause the by-products generated by dissolution when the exposed photoresist is cleaned and removed to be blocked by the raised part and adhere near the raised part, that is, affect the ability of development, and further affect the making of the conductive interconnection structure near the raised part; and due to the existence of the raised part, the conductive material at the corner of the bottom of the raised part is not easy to be grinded off when the conductive material is grinded, and further causes the residue of the conductive material.

[0068] For example, Figure 4 For example, Figure 4 For example, Figure 2kCorresponding to the case where the first groove 121 is not formed, after the planarization process when the conductive structure 11 is made, after the planarization process when the first wiring layer 141 is made, and after the planarization process when the second wiring layer 142 is made, the protruding height of the overhang area A2 is h1, h2 and h3 in sequence, h1, h2 and h3 increase in sequence, the height h1 and h2 do not exceed the set specification, the height h3 exceeds the set specification, and after the third dielectric layer 133 is subsequently formed on the second dielectric layer 132, the protruding height of the overhang area A2 further increases to h4. Then, in the process of forming the third wiring layer (not shown) in the third dielectric layer 133, in the process of forming the patterned photoresist layer by performing exposure and development processes on the photoresist layer corresponding to the third wiring layer, the by-products generated by dissolving when cleaning the exposed photoresist are blocked by the protrusion with a height of h4, resulting in poor quality of the patterned photoresist layer after development, which further affects the quality of the third via hole (not shown) formed by etching in the third dielectric layer 133; and when making the third wiring layer, the conductive material at the bottom corner of the protrusion with a height of h4 is not easy to be polished off, which may cause residual conductive material.

[0069] In the present application, before or after the formation of the dielectric layer, if the surface of the overhang area A2 is higher than the surface of the chip area A1, by forming the first groove 121 in the overhang area A2, the height difference between the first groove 121 and the surface of the chip area A1 is within the set specification, so that the height difference between the surface of the overhang area A2 and the surface of the chip area A1 is within the set specification, that is, the overhang area A2 does not form a protrusion, or even if the overhang area A2 forms a protrusion, the height of the protrusion is within the set specification, which further avoids the by-products generated by dissolving when cleaning the exposed photoresist in the development process being blocked by the protrusion, that is, avoids affecting the development ability, and further avoids affecting the production of the conductive interconnection structure near the protrusion; and when polishing the conductive material, the conductive material in the overhang area A2 region can be polished off, avoiding causing residual conductive material.

[0070] For example, before the formation of the dielectric layer, the first groove 121 is formed in the substrate of the overhang area A2, as shown in Figure 2c After the conductive material outside the via hole is polished off when making the conductive structure 11, the protrusion of the overhang area A2 is removed due to the formation of the first groove 121 in the substrate of the overhang area A2, as shown in Figure 2h After the conductive material on the first dielectric layer 131 is polished off when making the first wiring layer 141, the first dielectric layer 131 above the first groove 121 has a protrusion with a height of h5, as shown in Figure 2iAs shown, after forming the second dielectric layer 132, the protruding height of the second dielectric layer 132 above the first recess 121 is increased to h6; as shown Figure 2k As shown, after grinding the conductive material on the second dielectric layer 132 to form the second wiring layer 142, the second dielectric layer 132 of the suspended area A2 has a protrusion with a height of h7, the height h7 is greater than the height h6, and the height h7 is within the set specification. Therefore, due to the formation of the first recess 121 in the base of the suspended area A2, the suspended area A2 does not form a protrusion, or even if the suspended area A2 forms a protrusion, the height of the protrusion is within the set specification.

[0071] In addition, the manufacturing method of the semiconductor device can further include: forming a pad (not shown) on the dielectric layer of the chip area A1, the pad being electrically connected to the wiring layer. The metal material forming the pad is formed on the chip area A1 and the suspended area A2 of the base at the same time; after forming the pad, the part of the metal material located in the chip area A1 is reserved to form the pad, and the metal material located in the suspended area A2 is removed.

[0072] The step of forming the pad can include: depositing a metal material on the dielectric layer; forming a third photoresist layer on the metal material; patterning the third photoresist layer to form a third patterned photoresist layer, the third patterned photoresist layer including a pattern for forming the pad in the chip area A1 and a pattern for removing the metal material in the same layer as the pad in the suspended area A2; etching the metal material with the third patterned photoresist layer as a mask to form a pad in the chip area A1 and remove the metal material in the same layer as the pad in the suspended area A2.

[0073] The patterning of the third photoresist layer to form the third patterned photoresist layer includes: shielding the third photoresist layer of the suspended area A2 with a shield, and performing an exposure process on the third photoresist layer of the chip area A1, the third photoresist layer of the chip area A1 after exposure including the pattern of the pad; shielding the third photoresist layer of the chip area A1 after the exposure process with a shield, and performing an exposure process on the third photoresist layer of the suspended area A2 with a first mask, the third photoresist layer of the suspended area A2 after exposure including the pattern for removing the metal material in the same layer as the pad; performing a developing process on the third photoresist layer of the chip area A1 and the suspended area A2 after the exposure process to form the third patterned photoresist layer.

[0074] In the embodiments of the present application, the photomask used for forming the first recess 121 and the photomask used for removing the metal material in the same layer as the suspended area A2 and the pad are the same photomask, i.e., the first photomask. The metal material in the same layer as the suspended area A2 and the pad is formed in the suspended area A2 at the same time when the metal material forming the pad is formed in the chip area A1. In different process stages, the same photomask is used to expose photoresist in different process stages to form a photoresist layer including the pattern of the first recess 121 and a photoresist layer used for removing the metal material in the same layer as the suspended area A2 and the pad, so that the photomask can be saved. In other embodiments, the photomask used for forming the first recess 121 and the photomask used for removing the metal material in the same layer as the suspended area A2 and the pad can be different photomasks.

[0075] The method for manufacturing the semiconductor device can further include:

[0076] Thinning the substrate 101 away from the surface of the first insulating layer 102 to expose one end of the conductive structure 11 away from the first insulating layer 102;

[0077] Welding the surface of the substrate 101 away from the first insulating layer 102 to a substrate (not shown) through external solder balls (not shown), and the conductive structure 11 is electrically connected to the external solder balls;

[0078] Pasting a chip (not shown) on the side of the dielectric layer away from the substrate 101, and the chip is electrically connected to the pad. The chip can be electrically connected to the pad through a hybrid bonding structure or a micro bump (not shown), and the type of the chip is not limited.

[0079] In summary, the method for manufacturing the semiconductor device provided by the present application includes: providing a substrate, the substrate includes a chip area and a suspended area around the chip area, the suspended area supports the part to be connected to the substrate beyond the chip area on the substrate; forming a dielectric layer and a wiring layer in the dielectric layer on the substrate; wherein the first recess is formed in the suspended area before or after or at the same time as the dielectric layer is formed, and the height difference between the first recess and the surface of the chip area is within a specified specification. The method for manufacturing the semiconductor device of the present application can avoid the influence of the newly added suspended area outside the chip area on the stability of the photolithography process and the planarization process.

[0080] An embodiment of the present application provides a semiconductor device, which can be manufactured by the above method, comprising: a substrate, the substrate comprising a chip area and a suspension area surrounding the chip area, the suspension area supporting a part to be connected to the substrate beyond the chip area on the substrate; a dielectric layer formed on the substrate and a wiring layer formed in the dielectric layer; wherein the suspension area is formed with a first groove, so that the height difference between the surface of the suspension area and the surface of the chip area is within a specified specification.

[0081] Hereinafter, the semiconductor device provided by the embodiment will be described in detail. Figure 2k Figure 3 The semiconductor device provided by the embodiment is described in detail as follows. Figure 2k Figure 3 is a schematic diagram of a longitudinal section along the direction of AA'.

[0082] The substrate comprises a chip area A1 and a suspension area A2 surrounding the chip area A1, the suspension area A2 supporting a part to be connected to the substrate beyond the chip area A1 on the substrate.

[0083] The substrate can be a single-layer structure or a multi-layer stacked structure, and the material of the substrate can be a semiconductor material or a non-semiconductor material.

[0084] In an embodiment, as shown in Figure 2k , the substrate comprises a substrate 101 and a first insulating layer 102 formed on the surface of the substrate 101.

[0085] The material of the substrate 101 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors, etc., and can also comprise a layered substrate such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI) or silicon germanium on insulator, and can also comprise other materials other than semiconductor materials, such as glass, etc.

[0086] The suspension area A2 can be located between part of the adjacent chip areas A1, as shown in Figure 3 , the suspension area A2 is located only at one of the opposite edges of the chip area A1; or the suspension area A2 can be located between all the adjacent chip areas A1, i.e. the suspension area A2 can surround the chip area A1.

[0087] The substrate further comprises a dicing lane area (not shown), which surrounds the chip area A1 and is located between the chip area A1 and the suspension area A2.

[0088] ​​In an embodiment, the chip to be connected to the substrate.

[0089] The conductive structure 11 is formed in the substrate of the chip area A1.

[0090] A second insulating layer 111 can be formed between the conductive structure 11 and the substrate. In an embodiment, the second insulating layer 111 also extends to the surface of the substrate.

[0091] In Figure 2k In the embodiment shown, the conductive structure 11 penetrates the first insulating layer 102 and enters the substrate 101, a second insulating layer 111 is formed between the conductive structure 11 and the first insulating layer 102 and the substrate 101, and the second insulating layer 111 also extends to the surface of the first insulating layer 102.

[0092] The dielectric layer is formed on the substrate and covers the conductive structure 11, and the wiring layer is formed in the dielectric layer of the chip area A1 and is electrically connected to the conductive structure 11.

[0093] The overhang area A2 is formed with a first recess 121, so that the height difference between the surface of the overhang area A2 and the surface of the chip area A1 is within a specified specification.

[0094] Wherein, the surface of the overhang area A2 and the surface of the chip area A1 respectively refer to the surface of the dielectric layer of the overhang area A2 and the surface of the dielectric layer of the chip area A1. Alternatively, the surface of the overhang area A2 and the surface of the chip area A1 can also respectively refer to the surface of the substrate of the overhang area A2 and the surface of the substrate of the chip area A1.

[0095] In Embodiment One, the first recess 121 is formed in the substrate of the overhang area A2, and the first recess 121 extends from the surface of the substrate into the substrate. The dielectric layer fills the first recess 121.

[0096] In Embodiment Two, if the dielectric layer and the wiring layer are both one layer, the first recess 121 is formed in the dielectric layer of the overhang area A2.

[0097] In Embodiment Three, if the dielectric layer and the wiring layer are both at least two layers, each layer of the wiring layer is formed in the corresponding dielectric layer of the chip area A1, and the first recess 121 is formed in any one layer of the dielectric layer of the overhang area A2. Alternatively, the first recess 121 can also be formed in any at least two layers of the dielectric layer of the overhang area A2.

[0098] It should be noted that the height difference between the surface located in the suspended area A2 and the surface located in the chip area A1 within the set specifications includes: the surface located in the suspended area A2 is flush with the surface located in the chip area A1; or, the surface located in the suspended area A2 is lower or higher than the surface located in the chip area A1, and the height difference between the surface located in the suspended area A2 and the surface located in the chip area A1 is within the set specifications.

[0099] A second groove (i.e.,) is formed in the substrate of the chip region A1. Figure 2b The second groove 122 shown in the figure is filled by the dielectric layer and serves as an alignment mark.

[0100] Preferably, the first groove 121 and the second groove 122 have the same depth, so that the first groove 121 and the second groove 122 can be manufactured simultaneously, thereby simplifying the process and saving costs. In other embodiments, the first groove 121 and the second groove 122 may have different depths, and the first groove 121 and the second groove 122 may not be manufactured simultaneously.

[0101] In one embodiment, if both the first groove 121 and the second groove 122 are formed before the conductive structure 11 is formed, the second insulating layer 111 may also fill the first groove 121 and the second groove 122 when the second insulating layer 111 is formed.

[0102] The first groove 121 and the second groove 122 may be formed only in the first insulating layer 102, or the first groove 121 and the second groove 122 may penetrate the first insulating layer 102 and enter the substrate 101.

[0103] Preferably, the area of ​​the first groove 121 is the same as that of the suspended area A2.

[0104] like Figure 2k As shown, taking two dielectric layers (i.e., a first dielectric layer 131 and a second dielectric layer 132) and two wiring layers (i.e., a first wiring layer 141 and a second wiring layer 142) as an example, the first groove 121 can be formed in the substrate of the suspended region A2, and / or the first groove 121 can be formed in the first dielectric layer 131 of the suspended region A2, and / or the first groove 121 can be formed in the second dielectric layer 132 of the suspended region A2.

[0105] Additionally, the semiconductor device may also include: a pad (not shown) formed on the dielectric layer of the chip region A1, the pad being electrically connected to the wiring layer.

[0106] In addition, one end of the conductive structure 11 away from the first insulating layer 102 can penetrate the substrate 101, and the surface of the substrate 101 away from the first insulating layer 102 is soldered to a substrate (not shown) by a soldering ball (not shown), and the conductive structure 11 is electrically connected to the soldering ball; a chip (not shown) is formed on the surface of the dielectric layer away from the substrate 101, and the chip is electrically connected to the pad. Wherein, the chip can be electrically connected to the pad by a hybrid bonding structure or a micro bump (not shown), and the type of the chip is not limited.

[0107] In summary, the semiconductor device provided by the application comprises: a substrate, the substrate comprises a chip area and a suspended area around the chip area, the suspended area supports the part to be connected to the substrate beyond the chip area on the substrate; a dielectric layer and a wiring layer, the dielectric layer is formed on the substrate, and the wiring layer is formed in the dielectric layer; wherein, the suspended area is formed with a first groove, so that the height difference between the surface of the suspended area and the surface of the chip area is within the specified specification. The semiconductor device of the application can avoid the influence of the newly added suspended area outside the chip area on the stability of the photolithography process and the planarization process.

[0108] The above description is only a description of the preferred embodiments of the application, and does not limit the scope of the application in any way. Any modification or modification made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a chip region and a suspended region surrounding the chip region, the suspended region supporting a portion of the chip region to be connected to the substrate that extends beyond the chip region on the substrate; A dielectric layer and a wiring layer located within the dielectric layer in the chip region are formed on the substrate; Specifically, a first groove is formed in the suspended area before, during, or simultaneously with the formation of the dielectric layer. The dielectric layer formed subsequently fills the first groove. The height difference between the first groove and the surface of the chip area is within a set specification, so that after the chip area and the suspended area are planarized during the formation of the wiring layer, the height difference between the surface of the suspended area and the surface of the chip area is within a set specification.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Before forming the dielectric layer, the first groove is formed on the substrate located in the suspended region, the first groove extending from the surface of the substrate into the substrate.

3. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Both the dielectric layer and the wiring layer have at least two layers; After any one of the dielectric layers is formed, the first groove is formed in any one of the dielectric layers located in the suspended region.

4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Forming a dielectric layer on the substrate and a wiring layer located within the dielectric layer includes: A dielectric layer is formed on the substrate; A via is formed in the dielectric layer located in the chip region; The through-hole is filled with a conductive material, which also extends to cover the surface of the dielectric layer. The conductive material on the dielectric layer is removed using a planarization process to form a wiring layer in the via.

5. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Before forming a dielectric layer and a wiring layer within the dielectric layer on the substrate, a conductive structure is formed within the substrate located in the chip region, and the wiring layer is electrically connected to the conductive structure.

6. The method for manufacturing a semiconductor device as described in claim 5, characterized in that, Before forming the conductive structure within the substrate located in the chip region, a second groove is formed within the substrate of the chip region, the second groove serving as an alignment mark.

7. A semiconductor device, characterized in that, include: The substrate includes a chip region and a suspended region surrounding the chip region, the suspended region supporting the portion of the chip region to be connected to the substrate that extends beyond the chip region on the substrate; A dielectric layer and a wiring layer, wherein the dielectric layer is formed on the substrate and the wiring layer is formed within the dielectric layer of the chip region; The suspended area has a first groove, which is filled by the dielectric layer formed subsequently. The height difference between the first groove and the surface of the chip area is within a set specification, so that after the chip area and the suspended area are planarized during the formation of the wiring layer, the height difference between the surface of the suspended area and the surface of the chip area is within the set specification.

8. The semiconductor device as claimed in claim 7, characterized in that, The first groove is formed within the substrate located in the suspended region, and the first groove extends from the surface of the substrate into the substrate.

9. The semiconductor device as claimed in claim 7, characterized in that, Both the dielectric layer and the wiring layer have at least two layers; the first groove is formed in any one of the dielectric layers located in the suspended region.

10. The semiconductor device as claimed in claim 7, characterized in that, A conductive structure is formed within the substrate located in the chip region, and the wiring layer is electrically connected to the conductive structure.

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