Chip failure analysis method and device and electronic equipment

Abstract

The invention relates to a chip failure analysis method and device and electronic equipment. The method comprises the following steps: providing a stacked packaging chip with a failure point; the stacked packaging chip comprises a substrate and a device layer arranged on the substrate; respectively carrying out hot spot positioning on the front surface and the back surface of the stacked packaging chip to obtain a hot spot positioning result aiming at a failure point; wherein the front surface is a surface on which a device layer is formed, and the back surface is opposite to the front surface; and based on the hot spot positioning result, starting to thin the substrate from the back surface, and performing failure reproduction processing in the thinning process until the position information of the failure point in the stacked packaging chip is determined. The failure analysis success rate can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip failure analysis method, device and electronic equipment. Background Art

[0002] Electronic products are currently developing towards miniaturization, high density, high reliability, and low power consumption. With the development of semiconductor technology, the development direction of chips is also miniaturization, high density, high reliability, and low power consumption. In order to reduce the size of chips, the industry uses multi-layer chip stacking packaging to stack multiple chip dies together to form a stacked package chip. However, the packaging structure of the stacked package chip is complex, and it is very difficult to find the physical location of the failure in the traditional chip failure method, and the success rate is not high. Summary of the invention

[0003] Based on this, it is necessary to provide a chip failure analysis method, device and electronic equipment to address the problem of low failure analysis success rate in the prior art.

[0004] In a first aspect, the present application provides a chip failure analysis method, the method comprising:

[0005] A stacked package chip with a failure point is provided; the stacked package chip comprises a substrate and a device layer arranged on the substrate;

[0006] The hotspots of the front and back sides of the stacked packaged chip are located respectively to obtain the hotspot location results for the failure point; wherein the front side is the side with the device layer formed, and the back side is opposite to the front side;

[0007] Based on the hotspot location results, the substrate is thinned from the back side, and failure reproduction processing is performed during the thinning process until the location information of the failure point in the stacked package chip is determined.

[0008] In one embodiment, a stacked package chip having a failure point is provided, comprising:

[0009] Conducting electrical analysis on the stacked packaged chips to obtain electrical analysis results;

[0010] When it is determined based on the electrical analysis result that the stacked package chip has a short circuit failure, the stacked package chip is regarded as a stacked package chip with a failure point.

[0011] In one embodiment, the electrical analysis result includes an IV curve; and the failure reproduction process includes reproducing the IV curve on a substrate hole or a metal line of each stop layer.

[0012] In one embodiment, the stacked package chip is manufactured based on a packaging process that matches the function of the HBM chip.

[0013] In one embodiment, the packaging process is a 3D packaging process or a 2.5D packaging process.

[0014] In one embodiment, the hotspot location on the back side of the stacked package chip is performed before the hotspot location on the front side of the stacked package chip.

[0015] In one embodiment, hotspot positioning is performed on the front and back sides of the stacked packaged chip to obtain hotspot positioning results for the failure point, including:

[0016] When the hot spot area is obtained by performing hot spot positioning on the back side, the hot spot positioning result is determined as a first positioning result indicating that the failure point is located in the lower part area of ​​the stacked package chip;

[0017] When the hot spot is located on the front side to obtain a hot spot area, the hot spot location result is determined as a second location result indicating that the failure point is located in the upper part of the stacked package chip.

[0018] In one embodiment, thinning the substrate from the back side based on the hot spot location result includes:

[0019] Based on the first positioning result, the substrate is ground using a first grinding process; the first grinding process includes grinding the substrate layer by layer;

[0020] Based on the second positioning result, a second grinding process is used to grind the substrate; the second grinding process includes grinding to a substrate layer related to the failure point according to the substrate design structure.

[0021] In one embodiment, failure reproduction processing is performed during the thinning process until the location information of the failure point in the stacked package chip is determined, including:

[0022] In the process of thinning the substrate to expose the device layer, if it is determined based on the failure reproduction process that there is an abnormal position corresponding to the hot spot area on the substrate, then the position information of the failure point is obtained based on the abnormal position;

[0023] In the process of thinning the substrate to expose the device layer, if it is determined based on the failure reproduction process that there is no abnormal position corresponding to the hot spot area on the substrate, the stacked packaged chip with the exposed device layer is positioned in the hot spot area to obtain the abnormal position corresponding to the hot spot area, and the position information of the failure point is obtained based on the abnormal position.

[0024] In one embodiment, obtaining location information of a failure point based on an abnormal location includes:

[0025] The abnormal position is scanned by an electron microscope to obtain the position information of the failure point.

[0026] In one embodiment, a stacked package chip with exposed device layers is subjected to positioning processing for a hot spot area to obtain an abnormal position corresponding to the hot spot area, including:

[0027] Perform X-ray scans on the hot spot area and the corresponding grains to confirm the failure relationship; the failure relationship indicates the correspondence between the failure point and the abnormal position;

[0028] The stacked packaged chips are cut based on the failure relationship to obtain abnormal positions.

[0029] In one embodiment, X-ray scanning is performed on the hot spot area and the related wafers to confirm the failure relationship, including:

[0030] When the X-ray is used to scan the area near the center of the hot spot in 3D mode to obtain failure information, the X-ray is used to scan the grain in 2D mode to obtain overall structural information;

[0031] The failure location is confirmed according to the package design data, the overall structure information and the failure information, so as to determine the failure relationship based on the failure location.

[0032] In a second aspect, the present application also provides a chip failure analysis device, the device comprising:

[0033] A chip providing module is used to provide a stacked package chip with a failure point; the stacked package chip includes a substrate and a device layer arranged on the substrate;

[0034] A hotspot positioning module is used to perform hotspot positioning on the front and back sides of the stacked packaged chip, respectively, to obtain hotspot positioning results for the failure point; wherein the front side is the side with the device layer formed, and the back side is opposite to the front side;

[0035] The failure analysis module is used to thin the substrate from the back side based on the hotspot location results and perform failure reproduction processing during the thinning process until the location information of the failure point in the stacked package chip is determined.

[0036] In a third aspect, the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0037] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0038] In a fifth aspect, the present application also provides a computer program product, including a computer program, which performs the steps of the above method when executed by a processor.

[0039] The above-mentioned chip failure analysis method, device and electronic device, for a stacked package chip with a failure point, respectively performs hotspot positioning on the front and back of the stacked package chip to obtain a hotspot positioning result for the failure point, and thins the substrate from the back based on the hotspot positioning result, and performs failure reproduction processing during the thinning process until the position information of the failure point in the stacked package chip is determined; wherein the stacked package chip includes a substrate and a device layer arranged on the substrate, the front side is a side with a device layer formed, and the back side is opposite to the front side. The present application performs hotspot positioning on both the front and back sides of the chip to make a preliminary judgment on the position of the failure point in the chip, and then determines the position information of the failure point in the chip during the substrate thinning process, which can improve the success rate of failure analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 This is a traditional failure analysis flow chart;

[0042] Figure 2 A schematic diagram of a process flow of a chip failure analysis method in one embodiment;

[0043] Figure 3 A schematic diagram of a structure of stacked packaged chips in one embodiment;

[0044] Figure 4 A schematic diagram of a process for providing a stacked packaged chip with a failure point in one embodiment;

[0045] Figure 5 A schematic diagram of a process for determining an abnormal position in one embodiment;

[0046] Figure 6 A schematic diagram of a process for determining a failure relationship in an embodiment;

[0047] Figure 7 A schematic diagram of a specific process of a chip failure analysis method in an embodiment;

[0048] Figure 8 A schematic diagram of a hotspot positioning result in one embodiment;

[0049] Fig. 9 A schematic diagram of scanning a hot spot area in one embodiment;

[0050] Fig.10 A schematic diagram of obtaining failure relations through scanning in one embodiment;

[0051] Fig.11 A schematic diagram of locating an abnormal position in one embodiment;

[0052] Fig.12 A schematic diagram of an optical microscope photograph of an abnormal position in one embodiment;

[0053] Fig.13 A schematic diagram of a scanning electron microscope photograph of an abnormal location in one embodiment. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0056] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0057] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0058] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0060] Existing chip failure analysis technologies can be divided into non-destructive analysis and destructive analysis of chips, and these two types of analysis include electrical analysis and physical analysis. In traditional solutions, after a chip failure occurs, non-destructive analysis is first performed based on the failure phenomenon. After confirming that the chip has no external damage, electrical testing is usually performed; after the electrical test confirms the failure, circuit analysis and hotspot location are performed; after the hotspot location confirms the failure location, destructive analysis is introduced to cut, grind, and delayer the chip, and finally find the physical location that caused the failure.

[0061] However, if Figure 1As shown, the prior art immediately conducts destructive slice analysis after discovering that the chip is short-circuited between pins and locating the failure hotspot. However, for stacked packaged chips, the packaging structure is complex, the number of chip micro-bumps is huge, and there are many stacking levels. After obtaining the chip hotspot location, it is very difficult to directly conduct destructive slice analysis and finally find the physical location of the failure, and the success rate is not high. It should be noted that Figure 1 ATE in this article refers to the automated test equipment used for chip testing, and IV testing refers to current-voltage characteristic testing.

[0062] Based on the above-mentioned traditional technology, the embodiment of the present application proposes a chip failure analysis method. Aiming at the failure phenomenon, it combines non-destructive and destructive analysis methods, reasonably optimizes the FA (Failure Analysis) analysis process, prepares high-quality FA samples, and improves the success rate of FA analysis. Among them, the present application is applicable to chip failure analysis of stacked packaged chips. Exemplarily, the stacked packaged chips may include but are not limited to 2.5D / 3D packaged HBM (High Bandwidth Memory) chips. It should be noted that the beneficial effects brought about by the embodiment of the present application or the technical problems solved are not limited to this one, but may also be other implicit or related problems. For details, please refer to the description of the following embodiments.

[0063] Before introducing the specific embodiments of the present application, the professional terms involved in the present application are explained first:

[0064] HBM: High Bandwidth Memory.

[0065] ATE: Automatic Test Equipment, automatic test equipment.

[0066] FA: Failure Analysis.

[0067] TIM: Thermal Interface Material, thermal interface material.

[0068] ASIC: Application-Specific Integrated Circuit.

[0069] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0070] In an exemplary embodiment, Figure 2 As shown, a chip failure analysis method is provided, and the method is applied to the chip failure analysis of stacked packaged chips as an example for description, including the following steps 202 to 206. Among them:

[0071] Step 202 , providing a stacked package chip having a failure point; the stacked package chip includes a substrate and a device layer disposed on the substrate.

[0072] The embodiments of the present application can locate the failure point after a failure occurs inside a stacked package chip; wherein, the stacked package chip with a failure point may refer to a stacked package chip having a failure structure in the corresponding chip area, optionally, the chip area may include the substrate and the area where the device layer is located, and the failure structure may include a failure pin, such as a short-circuit pin corresponding to a chip short-circuit failure.

[0073] Specifically, it is possible to determine whether the chip has a failure point by conducting an electrical analysis on the stacked packaged chip. For example, the electrical analysis is used to confirm whether a chip short circuit failure has occurred. It is understandable that the above electrical analysis and failure point determination can also take other forms, not limited to the forms mentioned in the above embodiments. The present application provides a stacked packaged chip with a failure point as a chip to be analyzed, so as to improve the success rate of chip failure analysis by preparing high-quality failure analysis samples.

[0074] In the embodiment of the present application, the stacked package chip may include a substrate and a device layer disposed on the substrate, wherein the substrate may refer to a package substrate. Optionally, the device layer is related to the function of the stacked package chip, for example, the device layer may refer to various structures such as an integrated circuit layer, a microstructure or a sensor layer stacked on the substrate that can realize various signal detection, control, storage, physical quantity conversion and other functions.

[0075] For example, taking a HBM chip in a 2.5D package as an example, Figure 3 As shown, the device layer may include an interposer 302 and a chip located on the interposer 302, wherein the chip may include an integrated circuit chip (such as an ASIC chip) and a memory stack. The memory stack may include multiple memory chips and a logic chip. The memory chip is stacked on the logic chip and connected to the logic chip. Figure 3 In the embodiment, the chips are placed side by side on top of the interposer 302, and interconnected through the micro bumps 304 (ubump) of the chips and the wiring in the interposer 302. The interposer 302 interconnects the upper and lower layers through through silicon vias (TSV), and then is soldered to the package substrate 300 through solder balls 306 (C4).

[0076] It can be understood that the above-mentioned stacked package chip can also adopt other structural forms, not limited to the forms mentioned in the above embodiments, as long as it can achieve the corresponding functions of the stacked package. Among them, the memory chip can be a memory semiconductor chip, and the memory semiconductor chip can be a volatile memory semiconductor chip (such as a dynamic random access memory (DRAM). The substrate in the embodiment of the present application is a carrier of the semiconductor package. The packaging substrate can be made using an existing packaging substrate manufacturing process. The packaging substrate can include a ball grid array packaging substrate. Regarding the material and type of the substrate, the embodiment of the present application does not make specific restrictions.

[0077] Step 204 , performing hotspot location on the front and back sides of the stacked packaged chip, respectively, to obtain hotspot location results for the failure point; wherein the front side is a side with a device layer formed thereon, and the back side is opposite to the front side.

[0078] Specifically, in the case of obtaining a stacked package chip with a failure point, the present application proposes to perform hotspot positioning on the front and back of the stacked package chip respectively to obtain a hotspot positioning result for the failure point, and the hotspot positioning result can represent the preliminary judgment result of the position of the failure point in the stacked package chip, for example, there is a failure structure in the upper part of the stacked package chip, or there is a failure structure in the lower part of the stacked package chip. It can be understood that the front of the stacked package chip is a side with a device layer formed, and the back is opposite to the front.

[0079] In some embodiments, the hotspot is located on the back of the stacked packaged chip without destroying the structure of the stacked packaged chip. However, the hotspot is located on the front of the stacked packaged chip, which may destroy the structure of the stacked packaged chip. For example, the chip package has a metal cover. Before the hotspot is located on the front, the metal cover and TIM glue must be removed. It is understandable that when the stacked packaged chip is a bare chip, the metal cover does not need to be removed. Furthermore, regardless of whether the hotspot area is obtained by hotspot location on the back of the stacked packaged chip, the present application will perform hotspot location on the front of the stacked packaged chip, and vice versa.

[0080] By locating hot spots on both the front and back sides of the stacked packaged chip with a failure point and optimizing the chip failure analysis process, the embodiment of the present application can preliminarily determine the approximate location of the failure point, laying the foundation for subsequently determining the location information of the failure point to improve the success rate of the analysis.

[0081] Step 206 , thinning the substrate from the back side based on the hotspot location result, and performing failure reproduction processing during the thinning process until the position information of the failure point in the stacked package chip is determined.

[0082] Specifically, when the hotspot positioning results are obtained, the substrate can be thinned starting from the back side of the stacked packaged chip; wherein, the method of thinning the substrate is related to the results after the above-mentioned hotspot positioning of the front and back sides, that is, the present application is based on the hotspot positioning results to thin the substrate starting from the back side.

[0083] It can be understood that by locating the hot spots on the front and back of the stacked packaged chip and determining the approximate location of the failure point, different grinding methods can be used to thin the substrate from the back, thereby optimizing the substrate grinding process and improving the success rate of failure analysis. It should be noted that the embodiments of the present application do not limit the grinding method, as long as the function of thinning the substrate can be achieved.

[0084] Furthermore, the present application performs failure reproduction processing during the substrate thinning process until the location information of the failure point in the stacked package chip is determined. The failure reproduction may refer to the process of reproducing the failure data to avoid the situation where the failure point may be destroyed during the substrate thinning process, thereby ensuring the accuracy of the failure point location and improving the success rate of chip failure analysis.

[0085] The above chip failure analysis method can significantly improve the success rate of failure analysis by locating hot spots on both the front and back sides of the chip to make a preliminary judgment on the position of the failure point in the chip, and then determine the position information of the failure point in the chip through failure reproduction processing during the substrate thinning process.

[0086] In an exemplary embodiment, Figure 4 As shown, step 202 includes steps 302 to 304. Among them:

[0087] Step 302 , performing electrical analysis on the stacked packaged chips to obtain electrical analysis results.

[0088] Specifically, the present application can perform electrical analysis on the stacked packaged chips to obtain electrical analysis results, wherein the electrical analysis can include ATE testing and / or IV testing. It can be understood that the present application does not limit the specific test type of the electrical analysis.

[0089] Step 304 : when it is determined based on the electrical analysis result that the stacked package chip has a short circuit failure, the stacked package chip is regarded as a stacked package chip with a failure point.

[0090] Specifically, the embodiments of the present application are applicable to chip short circuit failures. Regarding determining the existence of short circuit failures in stacked packaged chips based on electrical analysis results, for example, when low resistance failures between pins are found in ATE testing, IV testing can be performed to confirm short circuit failures. For another example, taking the stacked packaged chip as an HBM chip as an example, after the short circuit occurs between the pins of the HBM particles through ATE testing and IV testing, it is determined that a chip short circuit failure occurs.

[0091] The embodiment of the present application determines the stacked packaged chips with failure points through electrical analysis, thereby ensuring the quality of failure analysis samples and improving the success rate of chip failure analysis.

[0092] In practical applications, the failure reproduction processing of the embodiments of the present application is related to a test process for determining whether a stacked packaged chip has a failure point. In one embodiment, the electrical analysis result may include an IV curve; the failure reproduction processing includes reproducing the IV curve on the substrate hole or metal wire of each stop layer.

[0093] Specifically, in the process of substrate thinning, the embodiments of the present application avoid the damage of the failure point by the substrate thinning process by reproducing the failure data of the detected failure point. Taking the hot spot location on the back of the stacked packaged chip to obtain the hot spot area as an example, for the stacked packaged chip with a failure point, the hot spot location of the chip back (i.e., the substrate surface) can be performed by Thermography according to the current and voltage of the IV test, and then the located hot spot area can be paid attention to in the process of substrate thinning, and the failure IV curve can be reproduced on the substrate hole or metal line on each stop layer.

[0094] For example, taking the thinning of the substrate by grinding as an example, the substrate can be ground to a stop layer during grinding, that is, grinding is stopped when grinding to the stop layer, and then the failure IV curve is reproduced on the substrate hole or metal wire on each stop layer. It can be understood that, taking the substrate as a packaging substrate as an example, the packaging substrate may include metal wires, and the metal wires may be arranged in the packaging substrate. Furthermore, the packaging substrate may also include substrate holes running through it, and then the failure IV curve can be reproduced in the substrate holes or metal wires on each stop layer during the substrate thinning process.

[0095] In one embodiment, the stacked package chip is manufactured based on a packaging process that matches the function of the HBM chip.

[0096] Specifically, the stacked package chip of the embodiment of the present application can be manufactured based on a packaging process that matches the function of the HBM chip, that is, the stacked package chip can adopt the HBM chip.

[0097] In one embodiment, the packaging process is a 3D packaging process or a 2.5D packaging process.

[0098] Specifically, the present application is applicable to the short-circuit failure of HBM chips in 2.5D / 3D packaging. For the HBM chip particles in 2.5D / 3D packaging with complex packaging structure, a large number of chip micro-bumps, and a large number of stacking levels, the present application can target the failure phenomenon, combine non-destructive and destructive analysis methods, reasonably optimize the FA analysis process, prepare high-quality FA samples, and improve the success rate of FA analysis.

[0099] Regarding hotspot location on the front and back of the stacked packaged chip, respectively, to obtain hotspot location results for the failure point, the present application proposes a corresponding failure analysis strategy, which can further improve the success rate of failure analysis. In one embodiment, the execution order of hotspot location on the back of the stacked packaged chip is before the hotspot location on the front of the stacked packaged chip.

[0100] Specifically, the present application proposes a sequential requirement for the execution order of hotspot positioning, wherein the execution order of hotspot positioning on the back of the stacked packaged chip is before the hotspot positioning on the front of the stacked packaged chip, that is, the hotspot positioning is performed on the back of the stacked packaged chip first, and then the hotspot positioning is performed on the front of the stacked packaged chip, so as to avoid damaging the chip structure as much as possible and determine the approximate location of the failure point by non-destructive analysis means. It should be noted that regardless of whether the hotspot area is located on the back or not, the embodiments of the present application will perform hotspot positioning on the front of the stacked packaged chip.

[0101] In addition, hotspot location on the back side of the stacked packaged chip is performed preferentially, which is more suitable for low-resistance short-circuit failure analysis of the chip, and further reduces the difficulty of finding the physical location of the failure, thus ensuring the success rate of the failure analysis.

[0102] In some embodiments, hotspot positioning is performed on the front and back sides of the stacked packaged chip to obtain hotspot positioning results for the failure point, including:

[0103] When the hot spot area is obtained by performing hot spot positioning on the back side, the hot spot positioning result is determined as a first positioning result indicating that the failure point is located in the lower part area of ​​the stacked package chip;

[0104] When the hot spot is located on the front side to obtain a hot spot area, the hot spot location result is determined as a second location result indicating that the failure point is located in the upper part of the stacked package chip.

[0105] Specifically, when the hotspot is located on the back side to obtain a hotspot area, the hotspot location result can be determined to be a first location result, and the first location result indicates that the failure point is located in the lower part of the stacked package chip. When the hotspot is located on the front side to obtain a hotspot area, the hotspot location result can be determined to be a second location result, and the second location result indicates that the failure point is located in the upper part of the stacked package chip.

[0106] It can be understood that by distinguishing whether the failure point is located in the upper area or the lower area of ​​the stacked packaged chip, the present application can make a preliminary judgment on the position of the failure point on the Z axis of the chip based on hotspot positioning on both the front and back sides of the chip, thereby improving the success rate of failure analysis.

[0107] In one embodiment, thinning the substrate from the back side based on the hot spot location result includes:

[0108] Based on the first positioning result, the substrate is ground using a first grinding process; the first grinding process includes grinding the substrate layer by layer;

[0109] Based on the second positioning result, a second grinding process is used to grind the substrate; the second grinding process includes grinding to a substrate layer related to the failure point according to the substrate design structure.

[0110] Specifically, when the hotspot location result is the first location result, that is, it is determined that the failure point is located in the lower part of the stacked package chip (there is a hotspot area on the back of the chip), the first grinding process can be used to grind the substrate, for example, grinding the substrate layer by layer. Exemplarily, the first grinding process can be to grind and thin the package substrate layer by layer.

[0111] When the hotspot location result is the second location result, that is, it is determined that the failure point is located in the upper area of ​​the stacked package chip (there is no hotspot area on the back of the chip), the second grinding process can be used to grind the substrate, for example, grinding to the substrate layer related to the failure point according to the substrate design structure. For example, taking the failure structure as a failed pin as an example, the second grinding process can be grinding to the substrate layer involved in the failed pin, for example, grinding to the substrate layer related to the short-circuit pin according to the substrate design structure.

[0112] Furthermore, during the grinding process, attention needs to be paid to the located hot spot areas. For example, the substrate structure can be checked under a high-resolution optical microscope to see if there are any abnormalities in the hot spot areas that may cause short circuit failures, and the failure data (such as IV curves) can be reproduced on the substrate holes or metal wires on each stop layer to determine whether physical abnormalities corresponding to electrical failures are found on the substrate.

[0113] By coordinating different hotspot positioning results and using different substrate grinding processes, the present application can avoid damaging the failure point, optimize the failure analysis process, and improve the success rate of failure analysis. It should be noted that the present application does not limit the specific grinding process, as long as the function of thinning the substrate can be achieved. For example, the above-mentioned grinding process can reduce the thickness of the substrate to expose the device layer or the substrate layer involved in the failed pin. In an exemplary embodiment, the substrate can be thinned using a thinning process such as a mechanical process.

[0114] In one embodiment, failure reproduction processing is performed during the thinning process until the location information of the failure point in the stacked package chip is determined, including:

[0115] In the process of thinning the substrate to expose the device layer, if it is determined based on the failure reproduction process that there is an abnormal position corresponding to the hot spot area on the substrate, then the position information of the failure point is obtained based on the abnormal position;

[0116] In the process of thinning the substrate to expose the device layer, if it is determined based on the failure reproduction process that there is no abnormal position corresponding to the hot spot area on the substrate, the stacked packaged chip with the exposed device layer is positioned in the hot spot area to obtain the abnormal position corresponding to the hot spot area, and the position information of the failure point is obtained based on the abnormal position.

[0117] Specifically, in the process of thinning the substrate to expose the device layer, it is necessary to pay attention to the located hot spot area, and determine whether the corresponding abnormal position is found on the substrate through failure reproduction processing. If there is no abnormal position on the substrate, it is further determined whether the abnormal position is in the device layer of the stacked packaged chip. Among them, the above-mentioned abnormal position can be understood as a physical abnormality corresponding to the electrical failure, that is, an abnormal physical position.

[0118] For example, taking thinning the substrate by grinding as an example, thinning the substrate to expose the device layer can be understood as grinding the substrate to a target thickness, which can be the thickness of the substrate, for example, the substrate is thinned to the first layer (L1).

[0119] Optionally, if it is determined based on the failure reproduction process that there is an abnormal position corresponding to the hot spot area on the substrate, the position information of the failure point can be obtained based on the abnormal position, that is, it is determined that the failure point is located in the substrate. If it is determined based on the failure reproduction process that there is no abnormal position corresponding to the hot spot area on the substrate, the stacked package chip with the device layer exposed can be positioned for the hot spot area until the abnormal position corresponding to the hot spot area is obtained, and the position information of the failure point is obtained based on the abnormal position.

[0120] In the process of thinning the substrate, the present application further determines the specific location of the failure point by confirming whether the failure point is located on the substrate, thereby optimizing the failure analysis process. Among them, grinding and thinning the substrate before determining whether the failure point is in the device layer can further improve the success rate of failure analysis, and performing the location analysis of the specific location of the failure point before cutting the chip can obtain an abnormal position judgment that is smaller than the hot spot area.

[0121] Regarding obtaining the location information of the failure point based on the abnormal location, in one embodiment, obtaining the location information of the failure point based on the abnormal location includes:

[0122] The abnormal position is scanned by an electron microscope to obtain the position information of the failure point.

[0123] Specifically, when the abnormal position is obtained, the abnormal position can be scanned by an electron microscope to obtain the position information of the failure point, thereby completing the chip failure analysis. For example, scanning the abnormal position by an electron microscope can be photographing the abnormal position by a high-resolution optical microscope and a scanning electron microscope, and this application is not limited to this.

[0124] In an exemplary embodiment, a stacked package chip with exposed device layers is subjected to positioning processing for a hot spot area to obtain an abnormal position corresponding to the hot spot area, such as Figure 5 As shown, it may include steps 402 to 404, wherein:

[0125] Step 402 , perform X-ray scanning on the hot spot area and the corresponding grains respectively to confirm the failure relationship; the failure relationship indicates the corresponding relationship between the failure point and the abnormal position.

[0126] Specifically, for stacked packaged chips with exposed device layers, the present application confirms the failure relationship by performing X-ray scanning on the hot spot area and the corresponding grains respectively, and the failure relationship can represent the correspondence between the failure point and the abnormal position.

[0127] Among them, after thinning the substrate, by performing X-ray scanning (X-ray scanning) on ​​the hot spot area, the specific position corresponding to the failure point in the hot spot area can be confirmed, and by performing X-ray scanning on the grains corresponding to the hot spot area, the overall structure can be confirmed. Then, based on the specific position corresponding to the failure point in the hot spot area and the overall structure, the correspondence between the failure point and the abnormal position is obtained, that is, the correspondence between the failure phenomenon and the abnormal position is confirmed.

[0128] Step 404 , cutting the stacked packaged chips based on the failure relationship to obtain abnormal positions.

[0129] Specifically, after the failure relationship is obtained, the stacked package chip can be cut according to the failure relationship to obtain the abnormal position. The stacked package chip can be cut by slicing the chip in cross section to obtain the abnormal point.

[0130] In the embodiment of the present application, thinning the substrate before X-ray scanning can not only simplify the analysis process and cost (because the failure point may be in the substrate layer), improve the success rate of failure analysis, but also greatly improve the clarity of X-ray imaging, and can ensure the quality of X-ray imaging. In addition, the present application performs X-ray scanning before cutting the chip, and can obtain a judgment of the failure point location that is smaller than the hot spot area.

[0131] In one embodiment, if Figure 6 As shown, step 402 may include steps 502 to 504. Among them:

[0132] Step 502 , when the X-ray is used to scan the area near the center of the hot spot area in 3D mode to obtain failure information, the X-ray is used to scan the grain in 2D mode to obtain overall structural information.

[0133] Specifically, the embodiment of the present application uses X-rays to scan the area near the center of the hot spot area in a 3D mode, wherein using X-rays to scan in a 3D mode may refer to performing a 3D X-ray scan.

[0134] For example, the area near the center of the hot spot area can refer to a small area of ​​the hot spot center area (referred to as the small area). The present application can improve the clarity of 3D-X-ray by scanning the area near the center of the hot spot area. Optionally, the area size of the area near the center can be selected according to demand, for example, the area size can be 2mm*2mm*2mm, and the present application does not limit the specific value of this area size.

[0135] Furthermore, the failure information may indicate that an abnormality is found in a 3D X-ray scan, such as confirming the position of the failure point corresponding to the hot spot area. When the failure information is obtained, X-rays may be used to scan the grains in 2D mode to obtain the overall structural information, wherein scanning in 2D mode using X-rays may refer to performing a 2D X-ray scan. Taking the stacked package chip using an HBM chip as an example, the grain may refer to an HBM particle, that is, the embodiment of the present application may perform a 2D X-ray scan and take a picture of the entire HBM particle involved.

[0136] Optionally, the overall structural information may refer to an overall diagram representing the overall structure of the grain, such as an overall diagram corresponding to a 2D X-ray. By acquiring failure information and an overall diagram, the embodiment of the present application can more accurately confirm the location of the failure point and improve the success rate of failure analysis. Among them, thinning the substrate before X-ray scanning can not only simplify the analysis process and cost, but also greatly improve the clarity of 3D X-ray imaging.

[0137] Step 504 , confirming the failure position according to the package design data, the overall structure information and the failure information, so as to determine the failure relationship based on the failure position.

[0138] Specifically, when the overall structure information and the failure information are obtained, the failure position can be confirmed according to the package design data, the overall structure information and the failure information, so as to determine the failure relationship based on the failure position.

[0139] The failure location may refer to the specific location of the failure point, such as pin information, etc. Furthermore, the package design data may be a package design document. After confirming the failure information (finding the abnormal location) through 3D X-ray scanning, the overall view of the 2D X-ray may be referred to the package design document to find the pin information involved in the abnormal location, and then confirm the corresponding relationship between the failure point (failure phenomenon) and the abnormal location.

[0140] The above chip failure analysis method performs 3D X-ray before cutting the chip, which can obtain abnormal position judgment smaller than the hot spot area. The substrate is ground and thinned before 3D X-ray, which improves the success rate of failure analysis and ensures the imaging quality of 3D X-ray.

[0141] In order to further illustrate the solution of the present application, a specific example is given below, taking a stacked package chip using a 2.5D / 3D packaged HBM chip and performing a short circuit failure analysis as an example. Figure 7 As shown, the chip failure analysis process may include: after the 2.5D / 3D packaged chip confirms that the short circuit occurs between the pins of the HBM particles through ATE and IV testing (such as IV probe), when the resistance value is small, the back side of the chip (i.e., the substrate surface) can be thermographed for hot spot location based on the current and voltage of the IV probe; regardless of whether a hot spot is obtained on the back side, the hot spot location must be performed again on the front side of the chip. If the chip package has a metal cover, the metal cover and TIM (Thermal interface material) glue must be removed before front positioning.

[0142] Based on the results of the above two hotspot positioning, Figure 7 As shown, the substrate is ground layer by layer (for example, the package substrate is thinned by plane grinding layer by layer), or the substrate layer involved in the failed pin is ground (for example, the substrate layer related to the short-circuited pin is ground according to the substrate design structure). During the grinding process, attention is paid to the located hot spot area to confirm whether physical anomalies corresponding to the electrical failure are found on the substrate (for example, the substrate structure can be checked under a high-resolution optical microscope to see whether there are anomalies in the hot spot area that cause short-circuit failure), and the failure IV curve of the above IV test is reproduced on the substrate holes or metal wires on each stop layer.

[0143] When the substrate is thinned to expose the device layer, if no abnormality is found, the chip after the substrate is thinned is scanned by X-ray, and a small area (e.g. 2mm*2mm*2mm) of the hot spot center area is scanned by 3D X-ray, and the HBM particles involved are scanned and photographed by 2D X-ray as a whole. After the 3D X-ray scan finds an abnormality, the overall image of the 2D X-ray can be compared with the package design document to find the pin information involved in the abnormal position, confirm the corresponding relationship between the failure phenomenon and the abnormal position, confirm the failure position, and then cut the chip to find the abnormal position (e.g., slice the chip into a cross section and cut out the abnormal point), take photos of the abnormal position with an optical microscope and an electron microscope, and the analysis is completed.

[0144] Among them, take the short-circuit pin VDDA_25_MEN (pin name) as an example, Figure 8 The following is the hotspot location result of the short-circuit pin short circuit ( Figure 8 The two boxes in the figure can represent HBM particles. Figure 8 Taking the hot spot area on the left as an example, the area near the center of the HBM hot spot area is scanned by 3D X-ray, as shown in Fig. 9 As shown in Figure 1, a micro bump (ubump) on the HBM die was found to be abnormal. Fig.10 As shown in the figure, the positional relationship between abnormal micro-bumps and C4 bumps can be found through 2D & 3D X-ray images. Fig.11 As shown in Figure 1, the abnormal micro-bump (VDDA_25_MEN) can be found in the package design document. In addition, after cutting the chip, the abnormal position is found, such as Fig.12 Shown is a high-resolution optical microscopy image of the abnormal location. Fig.13 This is a scanning electron microscope image of the abnormal location.

[0145] The above-mentioned chip failure analysis method combines non-destructive and destructive analysis methods, such as hot spot positioning, substrate grinding, IV measurement, and X-ray, etc., to reasonably optimize the FA analysis process, prepare high-quality FA samples, and improve the success rate of FA analysis for failure phenomena. Among them, the embodiment of the present application performs hot spot positioning on both the front and back sides of the chip to make a preliminary judgment on the position of the failure point on the Z axis of the chip. 3D X-ray is performed before cutting the chip to obtain an abnormal position judgment that is smaller than the hot spot range. The substrate is ground and thinned before 3D X-ray to improve the success rate of failure analysis and ensure the imaging quality of 3D X-ray.

[0146] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0147] Based on the same inventive concept, the embodiment of the present application also provides a chip failure analysis device for implementing the chip failure analysis method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more chip failure analysis device embodiments provided below can refer to the limitations of the chip failure analysis method above, and will not be repeated here.

[0148] In an exemplary embodiment, a chip failure analysis device is provided, comprising:

[0149] A chip providing module is used to provide a stacked package chip with a failure point; the stacked package chip includes a substrate and a device layer arranged on the substrate;

[0150] A hotspot positioning module is used to perform hotspot positioning on the front and back sides of the stacked packaged chip, respectively, to obtain hotspot positioning results for the failure point; wherein the front side is the side with the device layer formed, and the back side is opposite to the front side;

[0151] The failure analysis module is used to thin the substrate from the back side based on the hotspot location results and perform failure reproduction processing during the thinning process until the location information of the failure point in the stacked package chip is determined.

[0152] In one of the embodiments, the chip provides a module for performing electrical analysis on the stacked packaged chip to obtain an electrical analysis result; and when it is determined based on the electrical analysis result that the stacked packaged chip has a short circuit failure, the stacked packaged chip is treated as a stacked packaged chip with a failure point.

[0153] In one embodiment, the electrical analysis result includes an IV curve; and the failure reproduction process includes reproducing the IV curve on a substrate hole or a metal line of each stop layer.

[0154] In one embodiment, the stacked package chip is manufactured based on a packaging process that matches the function of the HBM chip.

[0155] In one embodiment, the packaging process is a 3D packaging process or a 2.5D packaging process.

[0156] In one embodiment, the hotspot location on the back side of the stacked package chip is performed before the hotspot location on the front side of the stacked package chip.

[0157] In one of the embodiments, the hotspot locating module is used to, when hotspot locating is performed on the back side to obtain a hotspot area, determine the hotspot locating result as a first locating result indicating that the failure point is located in the lower part of the stacked package chip; and when hotspot locating is performed on the front side to obtain a hotspot area, determine the hotspot locating result as a second locating result indicating that the failure point is located in the upper part of the stacked package chip.

[0158] In one embodiment, the failure analysis module is used to grind the substrate using a first grinding process based on a first positioning result; the first grinding process includes grinding the substrate layer by layer; and based on a second positioning result, grind the substrate using a second grinding process; the second grinding process includes grinding to a substrate layer related to a failure point according to a substrate design structure.

[0159] In one of the embodiments, the failure analysis module is used to obtain the position information of the failure point based on the abnormal position if it is determined based on the failure reproduction process that there is an abnormal position corresponding to the hot spot area in the substrate during the process of thinning the substrate to expose the device layer; and is used to perform positioning processing on the stacked packaged chips of the exposed device layer with respect to the hot spot area to obtain the abnormal position corresponding to the hot spot area, and obtain the position information of the failure point based on the abnormal position if it is determined based on the failure reproduction process that there is no abnormal position corresponding to the hot spot area in the substrate during the process of thinning the substrate to expose the device layer.

[0160] In one embodiment, the failure analysis module is used to scan the abnormal position with an electron microscope to obtain the position information of the failure point.

[0161] In one embodiment, the failure analysis module includes:

[0162] A scanning module is used to perform X-ray scanning on the hot spot area and the corresponding grains respectively to confirm the failure relationship; the failure relationship indicates the corresponding relationship between the failure point and the abnormal position;

[0163] The cutting module is used to cut the stacked packaged chips based on the failure relationship to obtain abnormal positions.

[0164] In one of the embodiments, the scanning module is used to scan the area near the center of the hot spot area in a 3D mode using X-rays to obtain failure information, and to scan the grains in a 2D mode using X-rays to obtain overall structural information; and to confirm the failure position according to the packaging design data, the overall structural information and the failure information, so as to determine the failure relationship based on the failure position.

[0165] Each module in the above chip failure analysis device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in an electronic device in the form of hardware, or can be stored in a memory in an electronic device in the form of software, so that the processor can call and execute the operations corresponding to each module.

[0166] In one embodiment, an electronic device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0167] It can be understood that the above-mentioned electronic device can be a server, a terminal device, or a chip failure analysis system, which can include but is not limited to an ATE test device, an IV test device, and the like.

[0168] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0169] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0170] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0171] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0172] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip failure analysis method, characterized in that: The method comprises: A stacked package chip having a failure point is provided; the stacked package chip comprises a substrate and a device layer arranged on the substrate; Performing hotspot location on the front and back sides of the stacked packaged chip respectively to obtain a hotspot location result for the failure point; wherein the front side is a side on which the device layer is formed, and the back side is opposite to the front side; The substrate is thinned from the back side based on the hotspot positioning result, and a failure reproduction process is performed during the thinning process until the position information of the failure point in the stacked package chip is determined.

2. The method according to claim 1, characterized in that Provides stacked packaged chips with failure points, including: Performing electrical analysis on the stacked packaged chip to obtain an electrical analysis result; When it is determined based on the electrical analysis result that the stacked package chip has a short circuit failure, the stacked package chip is used as the stacked package chip with a failure point.

3. The method according to claim 2, characterized in that The electrical analysis result includes an IV curve; and the failure reproduction process includes reproducing the IV curve on a substrate hole or a metal line of each stop layer.

4. The method according to claim 1, characterized in that: The stacked package chip is manufactured based on a packaging process that matches the function of the HBM chip.

5. The method according to claim 4, characterized in that The packaging process is a 3D packaging process or a 2.5D packaging process.

6. The method according to claim 1, characterized in that The hotspot positioning on the back side of the stacked package chip is performed before the hotspot positioning on the front side of the stacked package chip.

7. The method according to any one of claims 1 to 6, characterized in that: Performing hotspot location on the front and back sides of the stacked packaged chip respectively to obtain a hotspot location result for the failure point includes: When a hot spot area is obtained by performing hot spot positioning on the back surface, the hot spot positioning result is determined as a first positioning result indicating that the failure point is located in a lower part of the stacked package chip; When a hotspot area is obtained by performing hotspot positioning on the front side, the hotspot positioning result is determined as a second positioning result indicating that the failure point is located in an upper region of the stacked package chip.

8. The method according to claim 7, characterized in that Thinning the substrate from the back side based on the hot spot location result includes: Based on the first positioning result, grinding the substrate using a first grinding process; the first grinding process includes grinding the substrate layer by layer; Based on the second positioning result, the substrate is ground using a second grinding process; the second grinding process includes grinding to a substrate layer related to the failure point according to a substrate design structure.

9. The method according to claim 7, characterized in that: Performing failure reproduction processing during the thinning process until the position information of the failure point in the stacked package chip is determined includes: In the process of thinning the substrate until the device layer is exposed, if it is determined based on the failure reproduction process that an abnormal position corresponding to the hot spot area exists on the substrate, then obtaining the position information of the failure point based on the abnormal position; In the process of thinning the substrate to expose the device layer, if it is determined based on the failure reproduction process that there is no abnormal position on the substrate corresponding to the hot spot area, the stacked packaged chip exposing the device layer is positioned in the hot spot area to obtain the abnormal position corresponding to the hot spot area, and the position information of the failure point is obtained based on the abnormal position.

10. The method according to claim 9, characterized in that Obtaining the location information of the failure point based on the abnormal location includes: The abnormal position is scanned by an electron microscope to obtain the position information of the failure point.

11. The method according to claim 9, characterized in that The performing positioning processing on the stacked package chip exposing the device layer with respect to the hot spot area to obtain the abnormal position corresponding to the hot spot area includes: Performing X-ray scanning on the hot spot area and the corresponding grains respectively to confirm the failure relationship; the failure relationship represents the corresponding relationship between the failure point and the abnormal position; The stacked packaged chips are cut based on the failure relationship to obtain the abnormal position.

12. The method according to claim 11, characterized in that Perform X-ray scans on the hot spot area and related wafers to confirm the failure relationship, including: When the X-ray is used to scan the area near the center of the hot spot area in a 3D mode to obtain failure information, the X-ray is used to scan the grain in a 2D mode to obtain overall structural information; The failure position is confirmed according to the package design data, the overall structure information and the failure information, so as to determine the failure relationship based on the failure position.

13. A chip failure analysis device, characterized in that: The device comprises: A chip providing module, used for providing a stacked package chip with a failure point; the stacked package chip comprises a substrate and a device layer arranged on the substrate; A hotspot positioning module, used to perform hotspot positioning on the front and back sides of the stacked packaged chip, respectively, to obtain a hotspot positioning result for the failure point; wherein the front side is a side on which the device layer is formed, and the back side is opposite to the front side; A failure analysis module is used to thin the substrate from the back side based on the hotspot positioning result, and perform failure reproduction processing during the thinning process until the position information of the failure point in the stacked package chip is determined.

14. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 12 are implemented.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 12 are implemented.

16. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 12 are implemented.

Images