Substrate for flip-chip bonding and semiconductor package structure

Abstract

A substrate for flip-chip bonding and a semiconductor package structure are provided. The substrate includes a substrate body including a first surface and a second surface opposite to each other in a thickness direction, and including a central region and a peripheral region away from the central region, and a plurality of substrate connectors disposed on the first surface of the substrate body and spaced apart from each other in a first direction, where the first direction is parallel to the first surface, at least one of a width in the first direction and a height in the thickness direction of the plurality of substrate connectors varies according to a gap between a semiconductor chip bonded to the substrate and the substrate connectors.

Description

Technical Field

[0001] The present disclosure relates to a substrate and a semiconductor package structure for flip chip bonding. Background Art

[0002] In recent years, as consumer electronics have developed towards miniaturization, lightness, and low energy consumption, chip packaging has also developed towards miniaturization and lightness. In a flip chip packaging structure, the chip can be mounted on a substrate such as a printed circuit board (PCB) in the form of a flip chip. For example, the connection terminals of the chip can face the substrate and be connected to the connectors of the substrate so that the chip can be electrically connected to the substrate. Generally, solder such as solder balls or any other material that can achieve electrical connection can be used as the connection terminals of the chip, and any other similar structures of the substrate such as traces or conductive connection pads can be used as connectors of the substrate.

[0003] When the chip is flip-chip connected to the substrate, the chip in the flip-chip package structure will warp, and as the package structure becomes smaller and thinner, the warping gap between the chip and the substrate becomes larger and larger. In addition, due to the warping of the chip or the inconsistent warping between the chip and the substrate, it is easy for the chip connection terminal of the chip to fail to contact with the connector of the substrate or to have poor contact, which eventually forms electrical connection defects such as disconnection or cold soldering between the chip connection terminal and the connector of the substrate, which in turn leads to a decrease in the yield of electrical characteristics and affects product reliability. Summary of the invention

[0004] The present disclosure provides a substrate and a semiconductor package structure capable of improving cold solder joints and / or disconnections caused by large chip / substrate warping gaps in a semiconductor package structure.

[0005] The present disclosure also provides a semiconductor package structure for achieving warpage correction.

[0006] The present disclosure also provides a method for improving the non-wetting defect caused by a large warpage gap between a chip and a substrate in a flip-chip package.

[0007] The present disclosure also provides a method for improving the problem that the chip connection terminals cannot be well aligned with the substrate connection parts due to chip offset in flip-chip packaging.

[0008] According to one aspect of the present disclosure, a substrate for flip chip bonding may include: a substrate body, including a first surface and a second surface opposite to each other in a thickness direction, and including a central area and a peripheral area away from the central area, a plurality of substrate connectors, arranged on the first surface of the substrate body and spaced apart from each other in a first direction, wherein the first direction is parallel to the first surface, and wherein at least one of the width in the first direction and the height in the thickness direction of the plurality of substrate connectors varies according to the gap between a semiconductor chip bonded to the substrate and the substrate connector.

[0009] In an embodiment, assuming that both ends of a semiconductor chip disposed on a substrate are warped toward the substrate, the width of a substrate connector arranged in a central area may be smaller than the width of a substrate connector arranged in a peripheral area, and the substrate connector may be used to contact the semiconductor chip to achieve electrical connection.

[0010] In an embodiment, assuming that both ends of a semiconductor chip disposed on a substrate are warped in a direction away from the substrate, the width of a substrate connector arranged in a central area may be greater than the width of a substrate connector arranged in a peripheral area, and the substrate connector may be used to contact the semiconductor chip to achieve electrical connection.

[0011] In an embodiment, assuming that both ends of a semiconductor chip disposed on a substrate are warped toward the substrate, the height of the substrate connector arranged in the central area may be greater than the height of the substrate connector arranged in the peripheral area, and the substrate connector may be used to contact the semiconductor chip to achieve electrical connection.

[0012] In an embodiment, the substrate connection member includes a first substrate connection member and a second substrate connection member adjacent to the first substrate connection member, and the width range of the second substrate connection member is determined according to the following formula 1: Formula 1 Sqrt(Gap1 / Gap2)×W1≤W2≤Gap1 / Gap2×W1 Gap1 refers to the gap between the first substrate connector and the chip connection terminal of the semiconductor chip corresponding to the first substrate connector, W1 refers to the width of the first substrate connector in the first direction, Gap2 refers to the gap between the second substrate connector and the chip connection terminal of the semiconductor chip corresponding to the second substrate connector, and W2 refers to the width of the second substrate connector in the first direction.

[0013] In an embodiment, the substrate connection member includes a first substrate connection member and a second substrate connection member adjacent to the first substrate connection member, and the height range of the second substrate connection member is determined according to the following formula 2: H2=H1-(Gap1-Gap2) Gap1 refers to the gap between the first substrate connector and the chip connection terminal of the semiconductor chip corresponding to the first substrate connector, H1 refers to the height of the first substrate connector, Gap2 refers to the gap between the second substrate connector and the chip connection terminal of the semiconductor chip corresponding to the second substrate connector, and H2 refers to the height of the second substrate connector.

[0014] In an embodiment, the substrate may include a printed circuit board.

[0015] In an embodiment, the substrate connector may include a trace disposed in the substrate.

[0016] In an embodiment, the substrate connector has an H-shape or a cross-shape.

[0017] According to one aspect of the present disclosure, a semiconductor package structure includes a substrate and a semiconductor chip bonded to the substrate in a flip-chip form. The substrate may include: a substrate body, including a first surface and a second surface opposite to each other in a thickness direction, and including a central area and a peripheral area surrounding the central area, a plurality of substrate connectors, arranged on the first surface of the substrate body, and spaced apart from each other in a first direction, wherein the first direction is parallel to the first surface. The width of the plurality of substrate connectors in the first direction varies according to the gap between the semiconductor chip bonded to the substrate and the substrate connector. Assuming that both ends of the semiconductor chip arranged on the substrate are warped toward the substrate, the width of the substrate connector arranged in the central area is smaller than the width of the substrate connector arranged in the peripheral area, and the substrate connector is used to contact the semiconductor chip to achieve electrical connection. The semiconductor chip may include a chip body and a chip connection terminal arranged on a surface of the chip body opposite to the substrate, wherein the height of the chip connection terminal contacting the substrate connector arranged in the central area in the thickness direction is greater than the height of the chip connection terminal contacting the substrate connector arranged in the peripheral area in the thickness direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects and features of the present invention will become more apparent through the following description in conjunction with the accompanying drawings, in which: Figure 1 is a schematic diagram showing a substrate according to one or more exemplary embodiments; Figure 2 is a schematic diagram showing a package structure according to one or more exemplary embodiments; Figure 3 is a schematic cross-sectional view showing a semiconductor packaging structure in the prior art; Figure 4 and Figure 5 a plan view showing an arrangement of a plurality of substrate connectors arranged on a first surface of a substrate; and Figure 6 and Figure 7 Schematic diagrams of packaging structures according to one or more exemplary embodiments are shown. DETAILED DESCRIPTION

[0019] Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and these embodiments will fully convey the concept of the embodiments of the present invention to those of ordinary skill in the art. In the following detailed description, a number of specific details are set forth by way of example to provide a full understanding of the relevant teachings. However, it should be clear to those skilled in the art that the present teachings can be practiced without such details. In other cases, well-known methods, steps, and components are described at a relatively high level without details to avoid unnecessarily obscuring aspects of the present teachings. The same reference numerals in the accompanying drawings represent the same elements, and therefore their descriptions will not be repeated. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0020] For ease of explanation, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, the elements described as "under" or "beneath" or "below" other elements or features will then be oriented as "above" the other elements or features. Therefore, the example terms "under" and "below" can cover both above and below orientations.

[0021] In addition, in this specification, the phrase "on a plane" or "plan view" means viewing the target portion from the top, and the phrase "on a cross section" means viewing a cross section formed by vertically cutting the target portion from the side. In addition, the "vertical direction" indicates the up and down direction in the cross-sectional view.

[0022] Although terms such as "first", "second", and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, the first member, first component, first region, first layer, or first portion referred to in the examples may also be referred to as the second member, second component, second region, second layer, or second portion.

[0023] The present invention will now be described more fully hereinafter with reference to the accompanying drawings.

[0024] Figure 1 is a schematic diagram showing a substrate according to one or more exemplary embodiments. Figure 1 According to one or more exemplary embodiments, the substrate 100 may include a circuit board such as a printed circuit board (PCB), an injection molded circuit board, and / or a stamped circuit board (SCB). The substrate 100 is described in detail below mainly by taking a printed circuit board as an example.

[0025] The substrate 100 may include a substrate body 110, a substrate connection terminal 120 below the substrate body 110, and a substrate connector 130 above the substrate body 110. The substrate body 110 may include a circuit pattern portion and an insulating material portion formed therein. The substrate body 110 may include a plurality of circuit pattern portions so that a predetermined function may be performed. The plurality of circuit pattern portions may be formed in a plurality of layers of the substrate body 110, and / or at least some of the plurality of circuit pattern portions may be formed in the same layer, and others may be formed in one or more other layers. The circuit pattern portion may be formed by an etching method of photolithography or by a process such as plating, and may be electrically connected to another circuit pattern portion by, for example, a via through the insulating material portion.

[0026] The substrate body 110 may include a first surface 111 and a second surface 112 opposite to each other. In an exemplary embodiment, the first surface 111 of the substrate body 110 may be an upper surface or a top surface of the substrate body 110, and the second surface 112 of the substrate body 110 may be a lower surface or a bottom surface of the substrate body 110. When viewed on a plane defined by the first direction D1 and the second direction D2, the first surface 111 and the second surface 112 of the substrate body 110 may extend substantially along the plane, and may be spaced apart from each other in a third direction D3. In some example embodiments, the third direction D3 may represent a thickness direction of the substrate body 110, and the third direction D3 may intersect the first direction D1 and the second direction D2 with each other.

[0027] The substrate connector 130 may be disposed on the first surface 111 of the substrate body 110, and the substrate connection terminal 120 may be disposed on the second surface 112 of the substrate body 110. A solder resist may be disposed on both the first surface 111 and the second surface 112 of the substrate body 110, and the solder resist has a plurality of openings that expose the substrate connector 130 and the substrate connection terminal 120, respectively. The materials of the solder resist disposed on the first surface 111 and the second surface 112 of the substrate body 110 may be the same as or different from each other. The solder resist may be formed using a photosensitive material, and the solder resist may have a thermal fixing property and / or a photocuring property.

[0028] The substrate connector 130 and the substrate connection terminal 120 may be electrically connected to the circuit pattern portion of the substrate body 110 through the corresponding openings of the solder mask portion. In one or more example embodiments, the circuit pattern portion of the substrate body 110 may be formed by one or more conductive paths formed or arranged in the substrate body 110 and one or more conductive vias passing through the insulating material portion of the substrate body 110, but example embodiments are not limited thereto and may be formed by any other suitable connection structure known to those skilled in the art.

[0029] The substrate connector 130 may be used to connect to the semiconductor chip 200 (eg, see Figure 2 ) is electrically connected. The substrate connector 130 may be disposed on the upper surface 111 of the substrate body 110. That is, the substrate connector 130 may protrude from the upper surface of the substrate body 110. In one or more example embodiments, the substrate connector 130 may include a metal material or be formed of a metal material. For example, the substrate connector 130 may include copper (Cu) or be formed of copper (Cu), but is not limited thereto. In one or more embodiments, the substrate connector 130 may be a trace, a conductive connection pad, or a conductive connection pad. For example, the substrate connector 130 may be a copper trace.

[0030] The substrate connection terminal 120 may be used to connect the semiconductor package structure 1000 (see Figure 2 ) is electrically connected to the outside of the semiconductor package structure 1000. The substrate connection terminal 120 may be attached to the second surface 112 of the substrate body 110. In one or more embodiments, the substrate connection terminal 120 may include solder or be formed of solder. For example, the substrate connection terminal 120 may be a solder ball. However, as understood by those of ordinary skill in the art, the embodiments are not limited thereto.

[0031] The plurality of substrate connection terminals 120 may be disposed on the second surface 112 of the substrate body 110 according to a predetermined distribution. The predetermined distribution of the plurality of substrate connection terminals 120 may be based on the semiconductor package structure 1000 (see Figure 2) varies depending on the specifications of the external components to be connected to it.

[0032] In example embodiments, the substrate 100 may include a plurality of substrate connectors 130. The plurality of substrate connectors 130 may be arranged on the first surface 111 of the substrate body 110 in a predetermined distribution. For example, the plurality of substrate connectors 130 may be arranged on the first surface 111 of the substrate body 110 corresponding to the plurality of chip connection terminals 230 of the semiconductor chip 200 to be described later, so as to allow each of the plurality of chip connection terminals 230 to be electrically connected to the circuit pattern portion inside the substrate body 110 through the corresponding substrate connector 130. In example embodiments, the plurality of substrate connectors 130 may be spaced apart from each other on the first surface 111 of the substrate body 110. For example, the plurality of substrate connectors 130 may be spaced apart from each other on the first surface 111 of the substrate body 110 at equal intervals or unequal intervals.

[0033] The first surface 111 of the substrate body 110 may include a central area CA and a peripheral area PA away from the central area, wherein the central area CA is located at the center of the first surface 111. The center of the first surface 111 of the substrate body 110 may refer to an area that may correspond to the center of the semiconductor chip 200 to be connected to the substrate 100, and the edge of the first surface 111 of the substrate body 110 may refer to an area corresponding to the edge of the semiconductor chip 200 to be connected to the substrate 100. The substrate connector 130 may be provided in the central area CA and the peripheral area PA on the first surface 111. Although Figure 1, it is shown that only one substrate connector 130 is provided in the central area CA, but it is not limited thereto, for example, a plurality of substrate connectors 130 may be provided in the central area CA. In addition, a plurality of substrate connectors 130 may be provided in the peripheral area PA on the first surface 111. The width W1 of the substrate connector 130 provided in the central area CA in the first direction D1 may be smaller than the width W3 of the substrate connector 130 provided in the peripheral area PA in the first direction D1. In other words, the plurality of substrate connectors 130 arranged on the first surface 111 along the first direction D1 may have different widths in the first direction D1, wherein the widths of the plurality of substrate connectors 130 in the first direction D1 may gradually increase in a direction from the center of the first surface 111 along the first direction D1 toward the edge of the first surface 111. For example, the width of the substrate connector 130 located at the center of the first surface 111 may be smaller than the width of the substrate connector 130 located at the edge of the first surface 111, and the width of the substrate connector 130 located between the center of the first surface 111 and the edge of the first surface 111 may be larger than the width of the substrate connector 130 located at the center and smaller than the width of the substrate connector 130 located at the edge. That is, the width of the substrate connector 130 located in the central area CA is the smallest, and the width of the substrate connector 130 located in the peripheral area PA (e.g., located at the edge of the first surface 111) is the largest.

[0034] In an example embodiment, a plurality of substrate connectors 130 may be disposed in the central area CA of the first surface 111, and the widths of the plurality of substrate connectors 130 disposed in the central area CA may be different from each other. For example, the widths of the plurality of substrate connectors 130 located in the central area CA may gradually increase from the center of the central area CA to the edge of the central area CA. That is, the width of the substrate connector 130 located at the center of the central area CA is smaller than the width of the substrate connector 130 located at the edge of the central area CA. Figure 2 The width of the substrate connector 130 is described in further detail.

[0035] In addition, although Figure 1 It is not shown, but the height of the substrate connector 130 disposed in the central area CA of the first surface 111 in the third direction D3 may be greater than the height of the substrate connector 130 in the peripheral area PA in the third direction D3, and the width of the substrate connector 130 located in the central area CA in the first direction D1 may be less than the width of the substrate connector 130 located in the peripheral area PA in the first direction D1. Figure 2 is a schematic diagram illustrating a semiconductor package structure according to one or more exemplary embodiments. Figure 3is a schematic cross-sectional view showing a semiconductor packaging structure in the prior art. Figure 2 As shown in FIG. 1 , a semiconductor package structure 1000 may include a substrate 100 and a semiconductor chip 200 flip-chip connected to the substrate 100 .

[0036] The semiconductor chip 200 may be disposed on the first surface 111 of the substrate body 110 in a flip-chip form. The semiconductor chip 200 may include a chip body 210, a conductive chip pad 220 bonded to the chip body 210, and a chip connection terminal 230 bonded to the conductive chip pad 220.

[0037] The chip body 210 may include a semiconductor material, such as but not limited to silicon (Si), germanium (Ge) or silicon germanium (SiGe). The chip body 210 may have circuits and related connection structures formed therein for performing logic functions, storage functions and / or any other suitable functions known to those of ordinary skill in the art. The chip body 210 may be a bare die, such as an unpackaged wafer. The chip body 210 may be any suitable type of bare die, such as but not limited to a logic die, a memory die, or any other suitable structure known to those of ordinary skill in the art. The chip body 210 may have a first surface 211 and a second surface 212 opposite to each other in a third direction D3, wherein the first surface 211 faces the substrate 100. As used herein, the third direction D3 may also be the thickness direction of the chip body 210.

[0038] The conductive chip pad 220 may be disposed on the first surface 211 of the chip body 210 and electrically connected to a circuit formed inside the chip body 121. The conductive chip pad 220 may be exposed on the first surface 211 of the chip body 210. The conductive chip pad 220 may include a metal material or be formed by a metal material. For example, the conductive chip pad 220 may include a metal, a metal alloy and / or a conductive metal nitride. In one or more embodiments, the conductive chip pad 220 may have a single layer or multilayer structure. In one or more embodiments, the conductive chip pad 220 may be a conductive bump.

[0039] The chip connection terminal 230 may be disposed on the conductive chip pad 220 so that the conductive chip pad 220 is placed between the chip connection terminal 230 and the chip body 210. The chip connection terminal 230 may be connected to the conductive chip pad 220 and electrically connected to the internal circuit of the chip body 210 via the conductive chip pad 220. In one or more example embodiments, the chip connection terminal 230 may include solder or be formed by solder. For example, the chip connection terminal 230 may be a solder formed on a bump and used for bump connection. In some example embodiments, as shown, the chip connection terminal 230 may have a spherical shape. However, the shape of the chip connection terminal 230 is not limited thereto, for example, the chip connection terminal 230 may have any other suitable shape known to those of ordinary skill in the art. The semiconductor chip 200 may be electrically connected to the substrate 100 through the chip connection terminal 230 and the conductive chip pad 220. The chip connection terminal 230 of the semiconductor chip 200 may be combined with and electrically connected to the substrate connector 130 of the substrate 100.

[0040] Figure 3 The semiconductor chip 200A and the substrate 100A shown in FIG. 1 have the same specifications as the semiconductor chip 200 and the substrate 100 in the exemplary embodiment. That is, except Figure 3 In addition to the substrate connection member 130A and the chip connection terminal 230A of the semiconductor chip 200A shown in FIG. Figure 3 The semiconductor chip 200A and the substrate 100A are respectively Figure 1 and Figure 2 The semiconductor chip 200 and the substrate 100 shown in FIG. 1 are the same.

[0041] exist Figure 3 In the semiconductor package structure shown in , a plurality of substrate connectors 130A arranged on the first surface 111 of the substrate body 110 have the same width in the first direction D1, and a plurality of chip connection terminals 230A of the semiconductor chip 200A have the same height in the third direction D3.

[0042] During the packaging process, the semiconductor chip 200A is mounted on the substrate 100A with a certain pressure and the cooperation of the flux, and the semiconductor chip 200A may be warped to a certain extent during the packaging process. Figure 3 As shown in FIG. 1 , both side edges of the semiconductor chip 200A are bent toward the substrate 100A, while the center of the semiconductor chip 200A is arched toward a direction away from the substrate 100A (i.e., the third direction D3) (hereinafter referred to as warpage case 1). In other cases, the semiconductor chip 200A may be warped in the same manner as in FIG. Figure 3For example, the two side edges of the semiconductor chip 200A are bent away from the substrate 100A, while the center of the semiconductor chip 200A is arched toward the substrate 100A (hereinafter referred to as warpage situation 2). The following mainly describes the warpage situation 1 as an example.

[0043] In the case of warpage situation 1, there will be gaps between at least some of the chip connection terminals 230A of the semiconductor chip 200A and the substrate connection members 130A corresponding to the at least some of the chip connection terminals 230A of the substrate 100A, and the gaps are different from each other, wherein the gap between the chip connection terminal 230A at the center of the semiconductor chip 200A and the substrate connection member 130A corresponding thereto is the largest. In this case, the chip connection terminal 230A cannot be well contacted with the substrate connection member 130A, resulting in a cold solder joint or a non-contact situation between the chip connection terminal 230A and the substrate connection member 130A.

[0044] You can Figure 2 The position where the gap between the chip connection terminal 230A and the substrate connection member 130A in the prior art is the largest is referred to as the center of the central area CA of the substrate 100 mentioned above.

[0045] In an exemplary embodiment, in order to reduce or avoid the situation of cold soldering or failure to contact between the chip connection terminal and the substrate connection member, as shown in FIG. Figure 1 and Figure 2 As shown in , the width of the substrate connector 130 is increased, and / or the height of the substrate connector 130 is increased. Hereinafter, the width of the substrate connector 130 refers to the width of the substrate connector 130 in the first direction D1. For example, among the plurality of substrate connectors 130 arranged on the first surface 111 of the substrate body 110, the width of the substrate connector 130 may increase from the substrate connector 130 located in the central area CA toward the substrate connectors 130 located on both sides of the first surface 111. That is, among the plurality of substrate connectors 130 arranged on the first surface 111 of the substrate body 110, the width of the substrate connector 130 may increase in the first direction D1 from the substrate connector 130 arranged in the center of the central area CA, and increase in the direction opposite to the first direction D1 from the substrate connector 130 arranged in the center of the central area CA.

[0046] In an exemplary embodiment, the width of the substrate connector 130 may be determined according to the gap between the substrate connector 130 and the chip connection terminal 230. As shown in the following equation 1, the width W2 of the substrate connector 130 next to the substrate connector 130 at the center of the central area CA may be within the following range.

[0047] Formula 1 W2= Sqrt(Gap1 / Gap2)×W1 ~ Gap1 / Gap2×W1 Gap1 refers to the gap between the substrate connector 130 arranged at the center of the central area CA and the chip connection terminal 230 corresponding thereto, Gap2 refers to the gap between the substrate connector 130 adjacent to the substrate connector 130 at the center of the central area CA and the chip connection terminal 230 corresponding to the substrate connector 130, and W1 refers to the width of the substrate connector 130 arranged at the center of the central area CA, wherein the width W1 of the substrate connector 130 arranged at the center of the central area CA may be a pre-designed width.

[0048] That is, based on the above formula 1, the width W2 of the substrate connector 130 adjacent to the substrate connector 130 at the center of the central area CA may be greater than or equal to Sqrt(Gap1 / Gap2)×W1 and less than or equal to Gap1 / Gap2×W1.

[0049] Likewise, the width of each substrate connection member 130 disposed on the upper surface 111 of the substrate body 110 may be determined based on the above Formula 1.

[0050] The chip connection terminals 230 can be respectively arranged on the corresponding substrate connection parts 130. Since the volume of the chip connection terminals 230 is fixed during the welding packaging process, when the width of the substrate connection parts 130 connected to the chip connection terminals 230 is small, the area of ​​the corresponding chip connection terminals 230 in contact with the substrate connection parts 130 becomes smaller, and the height of the chip connection terminals 230 becomes larger. For example, for the substrate connection parts 130 located at the center of the central area CA of the substrate 100, the width of the substrate connection parts 130 can be reduced, so that the area of ​​the chip connection terminals 230 connected to the substrate connection parts 130 in contact with the substrate connection parts 130 is reduced, and then the height of the chip connection terminals 230 will be large. Therefore, the chip connection terminals 230 can be better in contact with the substrate connection parts 130, thereby overcoming the problems of cold solder joints caused by warping.

[0051] Similarly, based on the above formula 1, it can be known that for the warpage situation 1, the width of each substrate connector 130 located in the peripheral area PA of the substrate 100 is greater than the width of each substrate connector 130 located in the central area CA. Therefore, since the width of the substrate connector 130 in the peripheral area PA is greater than the width of the substrate connector 130 in the central area CA as a whole, the problem that the chip connection terminal 230 is offset out of the substrate connector 130 due to the offset of the semiconductor chip 200 (that is, the chip connection terminal 230 cannot be well aligned with the substrate connector 130 due to the offset of the semiconductor chip 200) can be overcome.

[0052] Although it has been described above that the widths of the plurality of substrate connectors 130 in the first direction D1 may gradually increase from the center of the first surface 111 along the first direction D1 toward the edge of the first surface 111, it is not limited thereto. For example, the widths of the substrate connectors 130 do not have to gradually change, as long as the widths of the substrate connectors 130 in the central area CA are smaller than the widths of the substrate connectors 130 in the peripheral area PA as a whole.

[0053] In addition, only the warping situation 1 is described in detail above, and the warping situation 2 is also applicable to the above formula 1. In other words, the above formula 1 can also be used to determine the width of the substrate connector in the warping situation 2.

[0054] The width of the substrate connector 130 can be designed in various forms. The width of the substrate connector 130 can be increased as a whole or in a local area. Figure 4 and Figure 5 1 is a plan view showing an arrangement of a plurality of substrate connectors 130 arranged on the first surface 111 of the substrate body 110, wherein: Figure 2 It can be along Figure 4 and Figure 5 A cross-sectional view taken along line AA'.

[0055] The width W2 of the substrate connector 130 may be increased as a whole, but is not limited thereto. Figure 4 and Figure 5 As shown in , alternatively, only the width of the area of ​​the substrate connection member 130 contacting the chip connection terminal 230 may be increased. For example, the substrate connection member 130 may increase the width of the area contacting the chip connection member in an H shape and / or a cross shape.

[0056] although Figure 4 and 5Only the substrate connectors 130 located at the two side edges of the substrate are shown to have an H shape, a cross shape, etc., but the present application is not limited to this. For example, the substrate connectors 130 arranged on the substrate body can all have an H shape, a cross shape, etc.

[0057] Figure 6 and Figure 7 Schematic diagrams of packaging structures according to one or more exemplary embodiments are shown.

[0058] In addition to the substrate connector and chip connection terminals Figure 2 In addition to the differences shown in Figure 6 and Figure 7 The package structure shown in Figure 2 The structures shown in FIG. 1 are the same, and the same reference numerals are used to represent the same components.

[0059] In an exemplary embodiment, for warpage case 1 (see Figure 6 ), the widths of the substrate connectors 130B are the same as each other, and the heights (e.g., the heights in the third direction D3) of the chip connection terminals 230B are the same as each other. The heights of the substrate connectors 130B may be different. For example, the height H1 of the substrate connector 130B arranged at the center of the central area CA is greater than the height H2 of the substrate connector 130 adjacent thereto, and the height H2 is greater than the height H3 of the substrate connector 130 located at the edge of the first surface 111.

[0060] The height H2 of the substrate connector 130 may be determined based on the height H1 of the substrate connector 130 adjacent thereto near the central area CA and the gaps Gap1 and Gap2 described above, for example, referring to the following Formula 2.

[0061] Formula 2 H2= H1-(Gap1-Gap2) Gap1 refers to the gap between the substrate connector 130B arranged at the center of the central area CA and the chip connection terminal 230B corresponding thereto, and Gap2 refers to the gap between the substrate connector 130B next to the substrate connector 130B at the center of the central area CA and the chip connection terminal 230B corresponding to the substrate connector 130B. H1 refers to the height of the substrate connector 130B arranged at the center of the central area CA, wherein the height H1 of the substrate connector 130B arranged at the center of the central area CA may be a pre-designed height.

[0062] Similarly, the height of each substrate connector 130B arranged on the upper surface 111 of the substrate body 110 can be determined based on the above formula 2. The height of the substrate connector in the area with a small warpage gap (e.g., the peripheral area) is less than the height of the substrate connector in the area with a large warpage gap (e.g., the central area), which can overcome the cold solder joint and disconnection caused by the warpage gap, thereby achieving a good connection.

[0063] Similarly, for Figure 7 The warping situation 2 shown in FIG. 1 is also applicable to the above formula 2. That is, the above formula 2 can also be used to determine the height of the substrate connection member 130C in the warping situation 2.

[0064] like Figure 7 As shown in , the height of the substrate connector 130C in the third direction D3 in the region where the warpage gap is small (eg, the central region CA) is smaller than that in the region where the warpage gap is large (eg, the peripheral region PA).

[0065] Although the above exemplary embodiments describe only the adjustment of the width and height of the substrate connector separately, in exemplary embodiments the width and height of the substrate connector may be adjusted simultaneously to reduce various problems caused by warping.

[0066] That is, in an exemplary embodiment, the width of the substrate connector in the region with a large warping gap may be adjusted to be smaller than the width of the substrate connector in the region with a small warping gap, and the height of the substrate connector in the region with a large warping gap may be adjusted to the height of the substrate connector in the region with a large warping gap. For example, in the case of warping situation 1, the width of the substrate connector in the central region in the first direction may be smaller than the width of the substrate connector in the peripheral region in the first direction, and the height of the substrate connector in the central region in the third direction may be greater than the height of the substrate connector in the peripheral region in the third direction. In the case of warping situation 2, the width of the substrate connector in the central region in the first direction may be greater than the width of the substrate connector in the peripheral region in the first direction, and the height of the substrate connector in the central region in the third direction may be smaller than the height of the substrate connector in the peripheral region in the third direction.

[0067] An exemplary embodiment provides a substrate for flip chip bonding and a chip packaging structure in which a chip is disposed on the substrate in a flip-chip form. The widths of a plurality of substrate connectors disposed on a substrate body of the substrate may be different, and / or the heights of the substrate connectors may be different, thereby overcoming a cold solder joint and / or disconnection caused by a warpage gap between a semiconductor chip and the substrate.

[0068] While the invention has been shown and described with reference to the particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the claims and their equivalents.

Claims

1. A substrate for flip chip bonding, the substrate comprising: a substrate body including a first surface and a second surface opposite to each other in a thickness direction and including a central region and a peripheral region away from the central region, A plurality of substrate connectors are disposed on the first surface of the substrate body and are spaced apart from each other in a first direction, wherein the first direction is parallel to the first surface, At least one of a width in the first direction and a height in the thickness direction of the plurality of substrate connectors varies according to a gap between the semiconductor chip bonded to the substrate and the substrate connector.

2. The substrate according to claim 1, wherein Assuming that both ends of the semiconductor chip disposed on the substrate are warped toward the substrate, the substrate connector arranged in the central area has a width smaller than that of the substrate connector arranged in the peripheral area, and the substrate connector is used to contact the semiconductor chip to achieve electrical connection.

3. The substrate according to claim 1, wherein Assuming that both ends of the semiconductor chip arranged on the substrate are warped in a direction away from the substrate, the width of the substrate connector arranged in the central area is greater than the width of the substrate connector arranged in the peripheral area, and the substrate connector is used to contact the semiconductor chip to achieve electrical connection.

4. The substrate according to claim 1, wherein Assuming that both ends of the semiconductor chip disposed on the substrate are warped toward the substrate, the height of the substrate connectors arranged in the central area is greater than that of the substrate connectors arranged in the peripheral area, and the substrate connectors are used to contact the semiconductor chip to achieve electrical connection.

5. The substrate according to claim 1, wherein The substrate connection member includes a first substrate connection member and a second substrate connection member adjacent to the first substrate connection member, and the width range of the second substrate connection member is determined according to the following formula 1: Formula 1 Sqrt(Gap1 / Gap2)×W1≤W2≤Gap1 / Gap2×W1 Gap1 refers to the gap between the first substrate connector and the chip connection terminal of the semiconductor chip corresponding to the first substrate connector, W1 refers to the width of the first substrate connector in the first direction, Gap2 refers to the gap between the second substrate connector and the chip connection terminal of the semiconductor chip corresponding to the second substrate connector, and W2 refers to the width of the second substrate connector in the first direction.

6. The substrate according to claim 1, wherein The substrate connecting member includes a first substrate connecting member and a second substrate connecting member adjacent to the first substrate connecting member, and the height range of the second substrate connecting member is determined according to the following formula 2: H2=H1-(Gap1-Gap2) Gap1 refers to the gap between the first substrate connector and the chip connection terminal of the semiconductor chip corresponding to the first substrate connector, H1 refers to the height of the first substrate connector, Gap2 refers to the gap between the second substrate connector and the chip connection terminal of the semiconductor chip corresponding to the second substrate connector, and H2 refers to the height of the second substrate connector.

7. The substrate according to claim 1, wherein The substrate includes a printed circuit board.

8. The substrate according to claim 1, wherein The substrate connector includes traces disposed in the substrate.

9. The substrate according to claim 1, wherein The substrate connection member has an H shape or a cross shape.

10. A semiconductor package structure, comprising the substrate as claimed in claim 2 and a semiconductor chip bonded to the substrate in a flip-chip form, the semiconductor chip comprising a chip body and chip connection terminals arranged on a surface of the chip body opposite to the substrate, wherein: The height of the chip connection terminals in contact with the substrate connection members arranged in the central region in the thickness direction is greater than the height of the chip connection terminals in contact with the substrate connection members arranged in the peripheral region in the thickness direction.

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