Short circuit protection circuit for power tubes

Abstract

The application discloses a short-circuit protection circuit for a power tube, comprising: a first comparator, configured to generate a valid first comparison signal when a sampling voltage of the power tube is greater than a first reference voltage; a voltage compensation circuit, configured to generate a triangular wave signal after the first comparison signal is valid, and superimpose the triangular wave signal with the first reference voltage to generate a second reference voltage; a second comparator, configured to generate a valid second comparison signal when the sampling voltage is greater than the second reference voltage; and a latch circuit, configured to generate a short-circuit fault signal when the second comparison signal is valid. The short-circuit protection circuit can provide corresponding anti-peak pulse time according to the size of the peak pulse on the external power tube, effectively avoid the false triggering caused by the load transient, improve the response speed of the short-circuit protection, and improve the safety and stability of the circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and more particularly, to a short-circuit protection circuit for power transistor. BACKGROUND

[0002] One of the main applications of power transistor such as IGBT (Insulated Gate Bipolar Transistor) is as a switching device for turning on and off the load. However, as a switching device for turning on and off the load, the power transistor is relatively fragile, and in many use cases, the power transistor can be burned out by the excessive current and rapid heating due to internal short circuit of the load or other abnormal conditions. For example, when the power transistor is short-circuited to the ground or power supply, the current can increase to 30A within 100ns, so it is particularly important to protect the power transistor.

[0003] Figure 1 A short-circuit protection circuit for power transistor in the prior art needs a long deglitch time to avoid false triggering during load transient, which includes a comparator 110 and a delay circuit 120. The comparator 110 is used to compare the sampling voltage Vsen representing the drain-source voltage difference of the power transistor with the reference voltage Vref to generate a comparison signal SC to the delay circuit 120. When the power transistor has a short-circuit event, the sampling voltage Vsen rises, and when the sampling voltage Vsen is greater than the reference voltage Vref, the comparator 110 outputs a high-level comparison signal SC. Since during the load transient, the sampling voltage Vsen can also be greater than the reference voltage Vref, in order to avoid false triggering, the delay circuit 120 will only trigger the short-circuit fault signal Fault to turn off the power transistor after the sampling voltage Vsen is greater than the reference voltage Vref for a period of time.

[0004] The deglitch time of the short-circuit protection circuit in the prior art is fixed. If the delay time is set too large, not only will the response of the short-circuit protection become slow, but also more power loss will be caused, and if the delay time is set too small, the false triggering caused by load transient cannot be effectively avoided. SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide a short-circuit protection circuit for power transistor, which can provide corresponding deglitch time according to the size of the spike pulse on the power transistor, not only can effectively avoid false triggering caused by load transient, but also can improve the response speed of the short-circuit protection, and improve the safety and stability of the circuit.

[0006] According to an aspect of the present application, there is provided a short-circuit protection circuit for a power transistor, comprising: a first comparator configured to compare a sampling voltage representing a drain-source voltage difference of the power transistor with a first reference voltage and generate a valid first comparison signal if the sampling voltage is greater than the first reference voltage; a voltage compensation circuit configured to generate a triangular wave signal after the first comparison signal is valid and superimpose the triangular wave signal with the first reference voltage to generate a second reference voltage; a second comparator configured to compare the sampling voltage with the second reference voltage and generate a valid second comparison signal if the sampling voltage is greater than the second reference voltage; and a latch circuit configured to generate a short-circuit fault signal if the second comparison signal is valid.

[0007] Optionally, an enabling time of the voltage compensation circuit is delayed by a first time with respect to a valid edge of the first comparison signal, and an enabling time of the second comparator is delayed by a second time with respect to the enabling time of the voltage compensation circuit.

[0008] Optionally, further comprising: a logic circuit configured to generate a first enable signal and a second enable signal according to the first comparison signal, the first enable signal being configured to control an enabling and disabling of the voltage compensation circuit, and the second enable signal being configured to control an enabling and disabling of the second comparator.

[0009] Optionally, a valid edge of the first enable signal is delayed by the first time with respect to a valid edge of the first comparison signal, and a valid edge of the second enable signal is synchronized with a non-valid edge of the first enable signal.

[0010] Optionally, the voltage compensation circuit comprises: a bias current source connected in series between an on-chip power supply voltage and a reference ground, a first switch having a control terminal configured to receive the first enable signal, and a first capacitor, and a first resistor having a first end connected with the first reference voltage and a second end connected with an intermediate node of the first switch and the first capacitor, wherein a conduction state of the first switch is controlled by the first enable signal, and a charging process of the first capacitor by the bias current source is controlled to obtain the second reference voltage at the intermediate node of the first switch and the first capacitor.

[0011] Optionally, further comprising: a reference voltage generation circuit configured to generate the first reference voltage according to an off-chip power supply voltage.

[0012] Optionally, the reference voltage generation circuit comprises: a second resistor and a third resistor connected in series between the off-chip power supply voltage and the reference ground, and an intermediate node of the second resistor and the third resistor being configured to generate the first reference voltage.

[0013] Optionally, the first resistor has a resistance value greater than the resistance values of the second resistor and the third resistor.

[0014] In summary, the short-circuit protection circuit for power tubes according to the embodiments of the present application can provide corresponding anti-peak pulse time according to the size of the peak pulse on the external power tube, which not only can effectively avoid the false triggering caused by the load transient, but also can improve the response speed of the short-circuit protection and the safety and stability of the circuit. In addition, the short-circuit protection circuit according to the embodiments of the present application can quickly react when a long-duration large peak pulse occurs in the power tube, and can timely turn off the power tube, thereby improving the safety of the system. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 A short-circuit protection circuit for power tubes according to the prior art.

[0017] Figure 2 A short-circuit protection circuit for power tubes according to an embodiment of the present application.

[0018] Figure 3a and Figure 3b are two working waveform diagrams of the short-circuit protection circuit according to the embodiments of the present application, respectively. DETAILED DESCRIPTION

[0019] Various embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the various drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale.

[0020] It should be understood that, in the following description, "circuitry" can include a single or multiple combinations of hardware circuitry, programmable circuitry, state machine circuitry, and / or elements that can store instructions for execution by programmable circuitry. When an element or circuitry is referred to as being "coupled" to another element or "coupled between" two elements, it can be directly coupled or connected to the other element or there can be intervening elements between the elements, and the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements between the two.

[0021] Meanwhile, certain terms used in the present patent specification and claims are terms of art destine to have a broad meaning as is usually understood by those who are skilled in the art. Those who are skilled in the art will understand that the same component can be referred to by different names depending on the context in which it is used. The present patent specification and claims are not intended to be limited to the specific names of components used herein, but are intended to include all such components that function in a similar manner as those specifically named.

[0022] The present application will be further described below with reference to the accompanying drawings and examples.

[0023] Figure 2 A short-circuit protection circuit 200 for a power switch chip is provided in an embodiment of the present application, wherein the part on the left of the dashed line is located outside the power switch chip, and the part on the right of the dashed line is located inside the power switch chip. As shown in FIG. 2, the short-circuit protection circuit 200 of the present embodiment comprises a reference voltage generating circuit 210 located outside the power switch chip, and a comparator 220, a logic circuit 230, a voltage compensation circuit 240, a comparator 250 and a latch circuit 260 located inside the power switch chip. Figure 2

[0024] The reference voltage generating circuit 210 is configured to generate a reference voltage Vref1 representing an initial threshold value for short-circuit detection. Further, the reference voltage generating circuit 210 comprises resistors R2 and R3 connected in series between an external power supply voltage VDDIO and a reference ground, and an intermediate node of the resistors R2 and R3 is configured to output the reference voltage Vref1. Further, in actual applications, one skilled in the art can adjust the voltage division ratio of the resistors R2 and R3 as needed to adjust the voltage value of the reference voltage Vref1. For example, the external power supply voltage VDDIO is provided by an IO power supply (Input / Output Power Supply), which is the voltage level used when the chip interacts with external devices for data exchange, and is directly related to the performance and stability of the chip.

[0025] The comparator 220 is configured to compare a sampling voltage Vsen representing the drain-source voltage difference of the power transistor with the reference voltage Vref1, and generate a valid (e.g., high level) comparison signal SC when the sampling voltage Vsen is greater than the reference voltage Vref1. For example, the comparator 220 has a positive input terminal, a negative input terminal and an output terminal, the positive input terminal is connected to the sampling voltage Vsen, the negative input terminal is connected to the reference voltage Vref1, and the output terminal is configured to provide the comparison signal SC.

[0026] ​The logic circuit 230 is configured to generate an enable signal EN1 and EN2 according to the comparison signal SC. For example, the enable signal EN1 is configured to control the opening and closing of the voltage compensation circuit 240, and the enable signal EN2 is configured to control the opening and closing of the comparator 250. Specifically, the logic circuit 230 is configured to generate the enable signal EN1 at a first time t1 after the active edge (e.g., rising edge) of the comparison signal SC from low to high, and generate the enable signal EN2 at a second time t2 after the active edge of the enable signal EN1.

[0027] The voltage compensation circuit 240 is configured to generate a triangular wave signal according to the enable signal EN1, and superimpose the triangular wave signal with a reference voltage Vref1 to generate a reference voltage Vref2. Specifically, the voltage compensation circuit 240 includes a bias current source Ibias, a switch S1, a resistor R1, and a capacitor C1, wherein the bias current source Ibias, the switch S1, and the capacitor C1 are connected in series between the internal power supply voltage VDD and the reference ground, the control terminal of the switch S1 is configured to receive the enable signal EN1, the first terminal of the resistor R1 is connected to the middle node of the resistors R2 and R3 to receive the reference voltage Vref1, and the second terminal of the resistor R1 is connected to the middle node of the switch S1 and the capacitor C1. Wherein, the enable signal EN1 controls the conduction state of the switch S1 to control the charging and discharging process of the capacitor C1 by the bias current source Ibias, so as to obtain the triangular wave signal at the first terminal of the capacitor C1, and superimpose the triangular wave signal with the reference voltage Vref1 to generate the reference voltage Vref2 at the first terminal of the capacitor C1. Further, the resistance value of the resistor R1 is greater than the resistance value of the resistors R2 and R3, so as to avoid the current output by the bias current source Ibias from entering the external resistors R2 and R3 to cause the reference voltage Vref1 to rise, and improve the detection accuracy and stability of the circuit.

[0028] The comparator 250 is configured to compare the sampling voltage Vsen with the reference voltage Vref2 according to the enable signal EN2, and generate an active (e.g., high level) comparison signal SCP when the sampling voltage Vsen is greater than the reference voltage Vref2.

[0029] The latch circuit 260 is configured to generate an active (e.g., high level) short-circuit fault signal Fault when the comparison signal SCP changes from low to high. For example, the latch circuit 260 can be implemented by a monostable trigger (e.g., RS latch), which is configured to set the short-circuit fault signal Fault to high when the comparison signal SCP changes from low to high.

[0030] Figure 3a and Figure 3b are respectively two working waveform diagrams of the short-circuit protection circuit of the embodiment, wherein Figure 3a shows the working waveform of the short-circuit protection circuit of the embodiment when the spike pulse on the sampling voltage Vsen is large, Figure 3b shows the working waveform of the short-circuit protection circuit of the embodiment when the spike pulse on the sampling voltage Vsen is small. As Figure 3a and 3b shown, first, the sampling voltage Vsen of the drain-source voltage difference of the external power tube is compared with the reference voltage Vref1 through the comparator 220, when it is detected that the sampling voltage Vsen is greater than the reference voltage Vref1, the comparison signal SC becomes high level. The logic circuit 230 delays the first time t1 after detecting the rising edge of the comparison signal SC, and makes the enable signal EN1 high level, and then makes the switch S1 conductive, charges the capacitor C1 through the bias current source Ibias, and makes the reference voltage Vref2 gradually rise. In the embodiment, the high level pulse width of the enable signal EN1 is equal to the second time t2, after the time t2, the enable signal EN1 becomes low level, the switch S1 is disconnected, the capacitor C1 is discharged to the ground through the resistors R1 and R3, and the reference voltage Vref2 gradually decreases during the discharging process. At the same time, the logic circuit 230 makes the enable signal EN2 high level after detecting the falling edge of the enable signal EN1, and turns on the comparator 250, so the time t1+t2 is the basic deglitch time of the short-circuit protection circuit of the embodiment. During the discharging process of the capacitor C1, the sampling voltage Vsen is compared with the reference voltage Vref2 through the comparator 250, if the duration of the spike pulse is short, the sampling voltage Vsen is less than the reference voltage Vref2 during the capacitor discharging process, the comparison signal SCP output by the comparator 250 is low level, and the short-circuit fault signal Fault is set to low level by the latch circuit 260, so that this part of the spike pulse on the power tube can be filtered out, and the circuit does not trigger the short-circuit protection; if the duration of the spike pulse is long, the sampling voltage Vsen is greater than the reference voltage Vref2 during the capacitor discharging process, the comparison signal SCP output by the comparator 250 is high level, and the short-circuit fault signal Fault is set to high level by the latch circuit 260, so that the external power tube is turned off through the control module inside the chip, to play the role of short-circuit protection.

[0031] In addition, as Figure 3a shown, when the spike pulse on the external power tube is large, the delay time from the detection of the sampling voltage Vsen overvoltage by the comparator 220 to the high level of the short-circuit fault signal Fault is T1, as Figure 3bAs shown, when the peak pulse on the external power tube is small, the delay time for detecting that the sampling voltage Vsen overvoltage to the short-circuit fault signal Fault is set to high level from the comparator 220 is T2, and the time T1 is less than the time T2. Therefore, the short-circuit protection circuit for the power tube according to the embodiment of the application can provide corresponding anti-peak pulse time according to the size of the peak pulse on the external power tube, so as to not only effectively avoid the false triggering caused by the load transient, but also improve the response speed of the short-circuit protection, and improve the safety and stability of the circuit.

[0032] In summary, the short-circuit protection circuit for the power tube according to the embodiment of the application can provide corresponding anti-peak pulse time according to the size of the peak pulse on the external power tube, so as to not only effectively avoid the false triggering caused by the load transient, but also improve the response speed of the short-circuit protection, and improve the safety and stability of the circuit. In addition, the short-circuit protection circuit according to the application can quickly react when the power tube appears a large peak pulse with long duration, and can timely turn off the power tube, thereby improving the safety of the system.

[0033] It should be noted that, in this document, the terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or other elements inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0034] According to the above description of the embodiments of the application, these embodiments do not describe all the details, and do not limit the application to only the specific embodiments. Obviously, according to the above description, many modifications and changes can be made. The embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the application, so that those skilled in the art can well utilize the application and make modifications and uses based on the application. The protection scope of the application should be defined by the scope of the claims of the application.

Claims

1. A short-circuit protection circuit for a power transistor, comprising: a first comparator configured to compare a sample voltage representing a drain-source voltage difference of the power transistor with a first reference voltage and generate a valid first comparison signal if the sample voltage is greater than the first reference voltage; a voltage compensation circuit configured to generate a triangular wave signal after the first comparison signal is valid and superimpose the triangular wave signal with the first reference voltage to generate a second reference voltage; a second comparator configured to compare the sample voltage with the second reference voltage and generate a valid second comparison signal if the sample voltage is greater than the second reference voltage; a latch circuit configured to generate a short-circuit fault signal when the second comparison signal is valid; and a logic circuit configured to generate a first enable signal and a second enable signal according to the first comparison signal, wherein the first enable signal is used to control turning on and off of the voltage compensation circuit, and the second enable signal is used to control turning on and off of the second comparator, wherein a turning on time of the voltage compensation circuit is delayed by a first time with respect to a valid edge of the first comparison signal, and a turning on time of the second comparator is delayed by a second time with respect to the turning on time of the voltage compensation circuit. a valid edge of the first enable signal is delayed by the first time with respect to the valid edge of the first comparison signal, and a valid edge of the second enable signal is synchronized with an invalid edge of the first enable signal.

2. The short circuit protection circuit of claim 1, wherein, the voltage compensation circuit comprises:

3. The short circuit protection circuit of claim 2, wherein, a bias current source, a first switch and a first capacitor connected in series between an on-chip power supply voltage and a reference ground, a control terminal of the first switch being configured to receive the first enable signal; and a first resistor having a first end connected to the first reference voltage and a second end connected to a middle node of the first switch and the first capacitor, wherein the first enable signal is used to control a conduction state of the first switch and control a charging process of the first capacitor by the bias current source, so as to obtain the second reference voltage at the middle node of the first switch and the first capacitor. further comprising:

4. The short circuit protection circuit of claim 3, wherein, a reference voltage generation circuit configured to generate the first reference voltage according to an off-chip power supply voltage. the reference voltage generation circuit comprises:

5. The short circuit protection circuit of claim 4, wherein, a second resistor and a third resistor connected in series between the off-chip power supply voltage and the reference ground, a middle node of the second resistor and the third resistor being configured to generate the first reference voltage. a resistance value of the first resistor is greater than resistance values of the second resistor and the third resistor.

6. The short circuit protection circuit of claim 5, wherein, ​

Images