A low-power power-on reset circuit

Abstract

The present application relates to a low-power power-on reset circuit, which realizes low-power and high-stability power-on reset and power-on detection functions by utilizing the hysteresis characteristics of the Schmitt trigger and combining the complementary control of PMOS and NMOS transistors. It not only provides the necessary reset delay, but also helps to reduce the power consumption of the circuit during the startup process. At the same time, in order to further improve the performance, a voltage detection hysteresis function is provided to provide an additional protection mechanism to prevent low voltage caused by power supply fluctuations. Compared with the prior art, the low-power characteristics of CMOS transistors are utilized to significantly reduce the overall power consumption of the power-on reset circuit. Through precise voltage detection and delay control, the stability of the circuit reset is ensured. The optimized voltage detection module improves the response speed of the circuit to power supply changes. The circuit design is simple and easy to be compatible with existing integrated circuit processes.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design and relates to a low-power power-on reset circuit. Background Art

[0002] The rapid development of electronic devices is driving increasing demands on power management. Power-on reset (POR) circuits, as a crucial component of electronic systems, are responsible for providing an initial state for the circuit when the power is applied or the system is reset. In integrated circuit design, power-on reset circuits play a crucial role, ensuring that the system initializes safely and stably when the power is applied or reset. However, existing POR circuits generally fail to effectively reduce power consumption in standby mode, resulting in shortened battery life. Some POR circuits do not respond quickly enough to power changes, affecting system startup speed. Power fluctuations or noise can easily cause traditional POR circuits to falsely trigger, reducing system reliability. Some complex POR circuits are difficult to integrate with existing integrated circuit processes, limiting their application. As energy efficiency requirements for electronic devices continue to increase, traditional POR circuits, due to their inherent power consumption, are no longer able to meet the demands of modern low-power designs. Summary of the Invention

[0003] In response to the problems existing in the above-mentioned traditional methods, the present invention proposes two low-power power-on reset circuits, which can quickly and stably provide a reset signal when the power is powered on, while significantly reducing power consumption.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, a low-power power-on reset circuit is provided, comprising a voltage detection module and a quantized delay module, wherein the quantized delay module comprises an intermediate delay unit and a two-stage Schmitt trigger, wherein two input terminals of the two-stage Schmitt trigger are respectively connected to a first power supply voltage and a second power supply voltage, an output terminal of the first-stage Schmitt trigger is connected to a first control terminal of the intermediate delay unit, an output terminal of the intermediate delay unit is connected to a control terminal of a second-stage Schmitt trigger, and an output terminal of the second-stage Schmitt trigger is used to provide a stable reset signal;

[0006] The voltage detection module includes a current mirror, an NMOS transistor pair with a proportional aspect ratio, a voltage divider resistor unit, and a startup load capacitor. The input end of the current mirror is connected to the first power supply voltage, the output end of the current mirror is connected to the input end of the NMOS transistor pair, the control end of the current mirror is connected to the second control end of the intermediate delay unit, the output end of the NMOS transistor pair is grounded through the voltage divider resistor unit, the control end of the voltage divider resistor unit is connected to the first control end of the intermediate delay unit, the gate of the startup load capacitor is respectively connected to the output end of the current mirror and the control end of the first-stage Schmitt trigger, the source of the startup load capacitor is connected to the first power supply voltage, and the drain of the startup load capacitor is connected to the input end of the intermediate delay unit;

[0007] The voltage-dividing resistor unit is used to provide a variable voltage divider for the voltage detection module. The quantized delay module is used to perform digital logic conversion based on the output result of the voltage detection module. The intermediate delay unit is used to generate a microsecond delay by charging the capacitor.

[0008] On the other hand, another low-power power-on reset circuit is also provided, including a voltage detection module and a quantized delay module, the quantized delay module including an intermediate delay unit and a two-stage Schmitt trigger, the two input terminals of the two-stage Schmitt trigger being respectively connected to a first power supply voltage and a second power supply voltage, the output terminal of the first-stage Schmitt trigger being connected to a first control terminal of the intermediate delay unit, the output terminal of the intermediate delay unit being connected to a control terminal of a second-stage Schmitt trigger, and the output terminal of the second-stage Schmitt trigger being used to provide a stable reset signal;

[0009] The voltage detection module includes a current mirror, an NMOS transistor pair with a proportional aspect ratio, a voltage divider resistor unit, and a startup load capacitor. The input end of the current mirror is connected to the first power supply voltage, the output end of the current mirror is connected to the input end of the NMOS transistor pair, the control end of the current mirror is connected to the second control end of the intermediate delay unit, the output end of the NMOS transistor pair is grounded through the voltage divider resistor unit, the gate of the startup load capacitor is respectively connected to the output end of the current mirror and the control end of the first-stage Schmitt trigger, the source of the startup load capacitor is connected to the first power supply voltage, and the drain of the startup load capacitor is connected to the input end of the intermediate delay unit.

[0010] The voltage-dividing resistor unit is used to provide voltage division for the voltage detection module, the quantization delay module is used to perform digital logic conversion based on the output result of the voltage detection module, and the intermediate delay unit is used to generate microsecond delay through capacitor charging.

[0011] One of the above technical solutions has the following advantages and beneficial effects:

[0012] The above-mentioned low-power power-on reset circuit realizes low-power and high-stability power-on reset and power-on detection functions by utilizing the hysteresis characteristics of the Schmitt trigger and combining the complementary control of PMOS and NMOS transistors. It not only provides the necessary reset delay, but also helps to reduce the power consumption of the circuit during the startup process. At the same time, in order to further improve the performance, a voltage detection hysteresis function is provided to provide an additional protection mechanism to prevent low voltage caused by power supply fluctuations. Compared with the existing technology, the low-power characteristics of CMOS transistors are utilized to significantly reduce the overall power consumption of the power-on reset circuit. Through precise voltage detection and delay control, the stability of the circuit reset is ensured. The optimized voltage detection module improves the circuit's response speed to power supply changes. The circuit design is simple and easily compatible with existing integrated circuit processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 1 is a schematic structural diagram of a low-power power-on reset circuit in one embodiment;

[0015] Figure 2 FIG. 4 is a schematic structural diagram of another low-power power-on reset circuit in an embodiment. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0018] It should be noted that reference to "embodiments" in this document means that the specific features, structures or characteristics described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The presentation of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. Those skilled in the art will appreciate that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. "Connection" can be a direct connection between two devices, or an indirect connection between two devices through other devices.

[0019] The following describes the embodiments of the present invention in detail with reference to the accompanying drawings in which the embodiments of the present invention are shown.

[0020] Given the above limitations of existing POR circuits, the electronics industry urgently needs a new low-power POR circuit that has the following characteristics:

[0021] Low power consumption: While ensuring fast response and high stability, the power consumption of the circuit is significantly reduced.

[0022] Fast response: The circuit can quickly respond to power supply changes, shortening the system startup time.

[0023] High stability: It has good anti-interference ability and reduces the possibility of false triggering.

[0024] Easy to integrate: compatible with modern integrated circuit technology, easy to use in various electronic devices.

[0025] While some designs on the market attempt to reduce power consumption through circuit optimization, these designs often sacrifice reset accuracy or increase circuit complexity. This paper addresses the shortcomings of existing POR circuits by proposing a novel low-power power-on reset circuit. This circuit design aims to reduce energy consumption while maintaining fast response and high reliability to meet the high-performance and fast startup requirements of modern electronic systems. Through its innovative circuit structure and control strategy, it significantly reduces power consumption while ensuring stable system operation, providing electronic devices with longer battery life and faster startup performance.

[0026] In one embodiment, Figure 1As shown, a low-power power-on reset circuit 100 is provided, which can include a voltage detection module 11 and a quantized delay module. The quantized delay module includes an intermediate delay unit 13 and a two-stage Schmitt trigger. The two input terminals of the two-stage Schmitt trigger are respectively connected to a first power supply voltage (VDD) and a second power supply voltage (VSS). The output terminal of the first-stage Schmitt trigger 15 is connected to the first control terminal of the intermediate delay unit 13. The output terminal of the intermediate delay unit 13 is connected to the control terminal of the second-stage Schmitt trigger 17. The output terminal of the second-stage Schmitt trigger 17 is used to provide a stable reset signal (VPOR).

[0027] The voltage detection module 11 includes a current mirror 111, an NMOS transistor pair 113 with a proportional aspect ratio, a voltage divider resistor unit 115, and a startup load capacitor PM2. The input of the current mirror 111 is connected to a first power supply voltage, the output of the current mirror 111 is connected to the input of the NMOS transistor pair 113, and the control terminal of the current mirror 111 is connected to the second control terminal of the intermediate delay unit 13. The output of the NMOS transistor pair 113 is grounded via the voltage divider resistor unit 115, and the control terminal of the voltage divider resistor unit 115 is connected to the first control terminal of the intermediate delay unit 13. The gate of the startup load capacitor PM2 is connected to the output of the current mirror 111 and the control terminal of the first-stage Schmitt trigger 15, respectively. The source of the startup load capacitor PM2 is connected to the first power supply voltage, and the drain of the startup load capacitor PM2 is connected to the input of the intermediate delay unit 13. The voltage divider resistor unit 115 is used to provide a variable voltage divider for the voltage detection module 11. The quantization delay module is used to perform digital logic conversion based on the output of the voltage detection module 11. The intermediate delay unit 13 is used to generate a microsecond delay by charging a capacitor.

[0028] It can be understood that the internal structure of the two-stage Schmitt trigger can be as follows Figure 1 As shown, the main circuit of each stage of the Schmitt trigger is the same and adopts the existing Schmitt trigger circuit structure.

[0029] The above-mentioned low-power power-on reset circuit 100 realizes low-power and high-stability power-on reset and power-on detection functions by utilizing the hysteresis characteristics of the Schmitt trigger and combining the complementary control of PMOS and NMOS transistors. It not only provides the necessary reset delay, but also helps to reduce the power consumption of the circuit during the startup process. At the same time, in order to further improve the performance, a voltage detection hysteresis function is provided to provide an additional protection mechanism to prevent low voltage caused by power supply fluctuations. Compared with the prior art, the low-power characteristics of CMOS transistors are utilized to significantly reduce the overall power consumption of the power-on reset circuit. Through precise voltage detection and delay control, the stability of the circuit reset is ensured. The optimized voltage detection module 11 improves the circuit's response speed to power supply changes. The circuit design is simple and easily compatible with existing integrated circuit processes.

[0030] In one embodiment, Figure 1 As shown, further, current mirror 111 includes transistors PM0 and PM1. NMOS transistor pair 113 includes transistors NM0 and NM1. Voltage divider resistor unit 115 includes resistors R0, R1, R2, and NM2. The sources of PM0 and PM1 are both connected to the first power supply voltage. The gate of PM0 is connected to the gate of PM1, the drain of PM1 is connected to the gate of startup load capacitor PM2, and the gate of PM1 is connected to the second control terminal of intermediate delay unit 13. The drain of PM0 is connected to one end of resistor R0, and the other end of resistor R0 is connected to the drain of NM0, the gate of NM0, and the gate of NM1, respectively. The source of NM0 is connected to one end of resistor R2 and the drain of NM2, respectively, through resistor R1. The source of NM1, the source of NM2, and the other end of resistor R2 are all grounded. The gate of NM2 is connected to the first control terminal of intermediate delay unit 13.

[0031] In one embodiment, Figure 1 As shown, the intermediate delay unit 13 further includes transistors PM3, PM4, NM3, NM4, and PM5. The gate of PM3 (i.e., the second control terminal of the intermediate delay unit 13) is connected to the gate of PM1. The sources of PM3 and PM5 are both connected to the drain of the startup load capacitor PM2. The drain of PM3 is connected to the source of PM4. The gate of PM4 (i.e., the first control terminal of the intermediate delay unit 13) is respectively connected to the gate of NM3 and the output terminal of the first-stage Schmitt trigger 15. The drain of PM4 is connected to the source of NM3. The drain of NM3 and the source of NM4 are both grounded. The gate of PM5 is respectively connected to the control terminal of the second-stage Schmitt trigger 17, the drain of PM4, and the gate of NM4. The drain of PM5 is connected to the first bias terminal of the second-stage Schmitt trigger 17. The drain of NM4 is connected to the second bias terminal of the second-stage Schmitt trigger 17.

[0032] It should be noted that if Figure 1 As shown, the low-power power-on reset circuit 100 mainly includes two key parts: a voltage detection module 11 and a quantization delay module. The voltage detection module 11 includes a current mirror 111, two NMOS transistor pairs 113 with proportional width-to-length ratios (i.e., NM0 and NM1 transistors, , Indicates the width-to-length ratio of the NM0 tube, Indicates the width-to-length ratio of the NM1 tube, kis the proportional coefficient), resistors R0, R1, and R2, and startup load capacitor PM2. Resistors R0, R1, and R2 form a voltage divider network to provide a variable voltage divider. Current mirror 111 consists of two PMOS transistors (PM0 and PM1). The quantized delay module includes two Schmitt triggers (ST) and an intermediate delay circuit.

[0033] The circuit operating principle of the low-power power-on reset circuit 100 may be as follows:

[0034] When the power supply voltage VDD starts to rise from 0, when the power supply voltage VDD is relatively low, the PMOS and NMOS transistors cannot be fully turned on. At this time, the source voltage of the PM1 transistor follows the power supply voltage VDD due to the charging of the startup load capacitor PM2. This ensures that the entire circuit remains in the output reset state when the power supply voltage VDD is relatively low.

[0035] As the power supply voltage VDD increases, both PM0 and NM0 transistors are turned on and the current flowing through branch 1 I Also increases and satisfies the following formula:

[0036] (1)

[0037] in, , , Indicates the threshold voltage of the PMOS tube, Indicates the threshold voltage of the NMOS tube, W represents the transistor width, L represents the transistor length, Represents the electron mobility of the NM0 tube, represents the electron mobility of PM0 tube, represents the gate oxide capacitance, R 0 represents the resistance value of resistor R0, R 1 represents the resistance value of resistor R1, R 2 represents the resistance value of resistor R2, V DD Indicates the value of the power supply voltage VDD.

[0038] The gate voltage of NM1 tube is:

[0039] (2)

[0040] Among them, when the NM2 tube is turned on, the voltage divider resistance value ; When NM2 tube is closed, the voltage divider resistance value .

[0041] Because the current mirror 111 composed of PM0 and PM1 tubes makes the current of branch 1 and branch 2I Keeping them equal, in order to make NM1 work in the saturation region, the gate voltage required by NM1 is:

[0042] (3)

[0043] When the current is relatively small and Sometimes, there are At this time, the voltage at point A is higher than the voltage at point B, and the voltage detection module 11 continues to output a high level.

[0044] when Sometimes, there are At this time, the voltage at point A is equal to the voltage at point B, and branch 1 becomes the input signal source for dividing the power supply voltage VDD, while the NM1 tube and the PM1 tube form a common-source amplifier with a large gain.

[0045] when Sometimes, there are At this time, the voltage at point A is lower than the voltage at point B, and the output of the voltage detection module 11 flips to a low level.

[0046] Therefore, as the power supply voltage VDD increases, the current flowing through branch 1 and branch 2 increases accordingly. When the voltage rises again, the output of the voltage detection module 11 will become a low level.

[0047] The quantized delay module converts the output result of the voltage detection module 11 into digital logic. At the same time, the intermediate delay unit 13 generates tens of (microseconds) delay, and when the power supply voltage VDD is relatively low, Figure 1 When point C in the circuit outputs a high level, resistor R2 is short-circuited. At this point, a higher power supply voltage VDD is required to flip the output of voltage detection module 11. Meanwhile, when power supply voltage VDD is relatively high and point C outputs a low level, resistor R2 is connected to branch 1. At this point, a lower power supply voltage is required to flip the output of voltage detection module 11. Therefore, the output of voltage detection module 11 achieves a hysteresis voltage effect.

[0048] In one embodiment, Figure 2 As shown, another low-power power-on reset circuit 200 is also provided, comprising a voltage detection module 11 and a quantized delay module. The quantized delay module includes an intermediate delay unit 13 and a two-stage Schmitt trigger. The two input terminals of the two-stage Schmitt trigger are respectively connected to a first power supply voltage and a second power supply voltage. The output terminal of the first-stage Schmitt trigger 15 is connected to the first control terminal of the intermediate delay unit 13. The output terminal of the intermediate delay unit 13 is connected to the control terminal of the second-stage Schmitt trigger 17. The output terminal of the second-stage Schmitt trigger 17 is used to provide a stable reset signal.

[0049] The voltage detection module 11 includes a current mirror 111, an NMOS transistor pair 113 with a proportional aspect ratio, a voltage divider resistor unit 115, and a startup load capacitor PM2. The input of the current mirror 111 is connected to a first power supply voltage, the output of the current mirror 111 is connected to the input of the NMOS transistor pair 113, and the control terminal of the current mirror 111 is connected to the second control terminal of the intermediate delay unit 13. The output of the NMOS transistor pair 113 is grounded via the voltage divider resistor unit 115. The gate of the startup load capacitor PM2 is connected to the output of the current mirror 111 and the control terminal of the first-stage Schmitt trigger 15, respectively. The source of the startup load capacitor PM2 is connected to the first power supply voltage, and the drain of the startup load capacitor PM2 is connected to the input of the intermediate delay unit 13. The voltage divider resistor unit 115 is used to provide a divided voltage for the voltage detection module 11. The quantized delay module is used to perform digital logic conversion based on the output of the voltage detection module 11. The intermediate delay unit 13 is used to generate a microsecond delay by charging a capacitor.

[0050] It is understandable that Figure 2 As shown, this embodiment provides another Figure 1 The circuit shown is a variant design for low power supply voltage, in which resistor R0 is used to provide voltage division. The operating principle of the low-power power-on reset circuit 200 in this embodiment can be understood similarly to the operating principle of the low-power power-on reset circuit 100 in the above embodiment, with the only difference being that variable voltage division is achieved by connecting or disconnecting resistor R0, which will not be repeated here.

[0051] The above-mentioned low-power power-on reset circuit 200 realizes low-power and high-stability power-on reset and power-on detection functions by utilizing the hysteresis characteristics of the Schmitt trigger and combining the complementary control of PMOS and NMOS transistors. It not only provides the necessary reset delay, but also helps to reduce the power consumption of the circuit during the startup process. At the same time, in order to further improve the performance, a voltage detection hysteresis function is provided to provide an additional protection mechanism to prevent low voltage caused by power supply fluctuations. Compared with the prior art, the low-power characteristics of CMOS transistors are utilized to significantly reduce the overall power consumption of the power-on reset circuit. Through precise voltage detection and delay control, the stability of the circuit reset is ensured. The optimized voltage detection module 11 improves the circuit's response speed to power supply changes. The circuit design is simple and easily compatible with existing integrated circuit processes.

[0052] In one embodiment, Figure 2As shown, current mirror 111 includes transistors PM0 and PM1. NMOS transistor pair 113 includes transistors NM0 and NM1. Voltage divider resistor unit 115 includes resistor R0. The sources of both PM0 and PM1 are connected to a first power supply voltage. The gate of PM0 is connected to the gate of PM1. The drain of PM0 is connected to the drain of NM0, the gate of NM0, and the gate of NM1, respectively. The source of NM0 is connected to one end of resistor R0 and the gate of PM0, respectively. The drain of NM1 is connected to the drain of PM1, the drain of PM1 is connected to the gate of startup load capacitor PM2, and the gate of PM1 is connected to the second control terminal of intermediate delay unit 13. The source of NM1 and the other end of resistor R0 are both grounded.

[0053] In one embodiment, Figure 2 As shown, the intermediate delay unit 13 includes transistors PM3, PM4, NM3, NM4, and PM5. The gate of PM3 is connected to the gate of PM1. The sources of PM3 and PM5 are both connected to the drain of the startup load capacitor PM2. The drain of PM3 is connected to the source of PM4. The gate of PM4 is connected to the gate of NM3 and the output of the first-stage Schmitt trigger 15. The drain of PM4 is connected to the source of NM3. The drain of NM3 and the source of NM4 are both grounded. The gate of PM5 is connected to the control terminal of the second-stage Schmitt trigger 17, the drain of PM4, and the gate of NM4. The drain of PM5 is connected to the first bias terminal of the second-stage Schmitt trigger 17, and the drain of NM4 is connected to the second bias terminal of the second-stage Schmitt trigger 17.

[0054] It can be understood that the detailed explanation of each component of the low power power-on reset circuit 200 can be understood by referring to the explanation of the low power power-on reset circuit 100 in the above embodiment, and will not be repeated here.

[0055] In actual design applications, the PMOS transistors, NMOS transistors, resistors, and Schmitt triggers can be selected and arranged to achieve the design goals of low power consumption and fast response. According to the predetermined power supply voltage threshold and system requirements, the resistance ratio of the voltage divider resistor network is adjusted. The entire low-power power-on reset circuit is integrated and tested according to the designed circuit structure to ensure that it correctly performs the power-on reset function within the specified voltage range.

[0056] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0057] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that variations and improvements can be made by those skilled in the art without departing from the spirit of the present application, all of which fall within the scope of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A low-power power-on reset circuit, characterized in that: The invention comprises a voltage detection module and a quantization delay module, wherein the quantization delay module comprises an intermediate delay unit and a two-stage Schmitt trigger, wherein the two input terminals of the two-stage Schmitt trigger are respectively connected to a first power supply voltage and a second power supply voltage, the output terminal of the first-stage Schmitt trigger is connected to a first control terminal of the intermediate delay unit, the output terminal of the intermediate delay unit is connected to a control terminal of the second-stage Schmitt trigger, and the output terminal of the second-stage Schmitt trigger is used to provide a stable reset signal; The voltage detection module includes a current mirror, an NMOS transistor pair with a proportional aspect ratio, a voltage divider resistor unit, and a startup load capacitor. The input end of the current mirror is connected to the first power supply voltage, the output end of the current mirror is connected to the input end of the NMOS transistor pair, the control end of the current mirror is connected to the second control end of the intermediate delay unit, the output end of the NMOS transistor pair is grounded through the voltage divider resistor unit, the control end of the voltage divider resistor unit is connected to the first control end of the intermediate delay unit, the gate of the startup load capacitor is respectively connected to the output end of the current mirror and the control end of the first-stage Schmitt trigger, the source of the startup load capacitor is connected to the first power supply voltage, and the drain of the startup load capacitor is connected to the input end of the intermediate delay unit; The voltage-dividing resistor unit is used to provide a variable voltage divider for the voltage detection module, the quantized delay module is used to perform digital logic conversion according to the output result of the voltage detection module, and the intermediate delay unit is used to generate a microsecond delay by charging a capacitor.

2. A low-power power-on reset circuit according to claim 1, characterized in that: The current mirror includes a PM0 transistor and a PM1 transistor, the NMOS transistor pair includes an NM0 transistor and an NM1 transistor, and the voltage divider resistor unit includes a resistor R0, a resistor R1, a resistor R2, and an NM2 transistor; The sources of the PM0 transistor and the PM1 transistor are both connected to the first power supply voltage, the gate of the PM0 transistor is connected to the gate of the PM1 transistor, the drain of the PM1 transistor is connected to the gate of the startup load capacitor, and the gate of the PM1 transistor is connected to the second control terminal of the intermediate delay unit; The drain of the PM0 tube is connected to one end of the resistor R0, and the other end of the resistor R0 is respectively connected to the drain of the NM0 tube, the gate of the NM0 tube and the gate of the NM1 tube. The source of the NM0 tube is respectively connected to one end of the resistor R2 and the drain of the NM2 tube through the resistor R1. The source of the NM1 tube, the source of the NM2 tube and the other end of the resistor R2 are all grounded. The gate of the NM2 tube is connected to the first control end of the intermediate delay unit.

3. A low-power power-on reset circuit according to claim 2, characterized in that: The intermediate delay unit includes a PM3 transistor, a PM4 transistor, an NM3 transistor, an NM4 transistor, and a PM5 transistor. The gate of the PM3 transistor is connected to the gate of the PM1 transistor. The source of the PM3 transistor and the source of the PM5 transistor are both connected to the drain of the startup load capacitor. The drain of the PM3 transistor is connected to the source of the PM4 transistor. The gate of the PM4 transistor is respectively connected to the gate of the NM3 transistor and the output end of the first-stage Schmitt trigger. The drain of the PM4 transistor is connected to the source of the NM3 transistor. The drain of the NM3 transistor and the source of the NM4 transistor are both grounded. The gate of the PM5 tube is respectively connected to the control end of the second-stage Schmitt trigger, the drain of the PM4 tube and the gate of the NM4 tube, the drain of the PM5 tube is connected to the first bias end of the second-stage Schmitt trigger, and the drain of the NM4 tube is connected to the second bias end of the second-stage Schmitt trigger.

4. A low-power power-on reset circuit, characterized in that: The invention comprises a voltage detection module and a quantization delay module, wherein the quantization delay module comprises an intermediate delay unit and a two-stage Schmitt trigger, wherein the two input terminals of the two-stage Schmitt trigger are respectively connected to a first power supply voltage and a second power supply voltage, the output terminal of the first-stage Schmitt trigger is connected to a first control terminal of the intermediate delay unit, the output terminal of the intermediate delay unit is connected to a control terminal of the second-stage Schmitt trigger, and the output terminal of the second-stage Schmitt trigger is used to provide a stable reset signal; The voltage detection module includes a current mirror, an NMOS transistor pair with a proportional aspect ratio, a voltage divider resistor unit, and a startup load capacitor, wherein the input end of the current mirror is connected to the first power supply voltage, the output end of the current mirror is connected to the input end of the NMOS transistor pair, the control end of the current mirror is connected to the second control end of the intermediate delay unit, the output end of the NMOS transistor pair is grounded through the voltage divider resistor unit, the gate of the startup load capacitor is respectively connected to the output end of the current mirror and the control end of the first-stage Schmitt trigger, the source of the startup load capacitor is connected to the first power supply voltage, and the drain of the startup load capacitor is connected to the input end of the intermediate delay unit; The voltage-dividing resistor unit is used to provide the divided voltage of the voltage detection module, the quantization delay module is used to perform digital logic conversion according to the output result of the voltage detection module, and the intermediate delay unit is used to generate a microsecond delay by charging the capacitor.

5. A low-power power-on reset circuit according to claim 4, characterized in that: The current mirror includes a PM0 transistor and a PM1 transistor, the NMOS transistor pair includes an NM0 transistor and an NM1 transistor, and the voltage dividing resistor unit includes a resistor R0; The sources of the PM0 tube and the PM1 tube are both connected to the first power supply voltage, the gate of the PM0 tube is connected to the gate of the PM1 tube, the drain of the PM0 tube is respectively connected to the drain of the NM0 tube, the gate of the NM0 tube and the gate of the NM1 tube, the source of the NM0 tube is respectively connected to one end of the resistor R0 and the gate of the PM0 tube, the drain of the NM1 tube is connected to the drain of the PM1 tube, the drain of the PM1 tube is connected to the gate of the startup load capacitor, the gate of the PM1 tube is connected to the second control end of the intermediate delay unit, and the source of the NM1 tube and the other end of the resistor R0 are both grounded.

6. The low-power power-on reset circuit according to claim 5, characterized in that: The intermediate delay unit includes a PM3 transistor, a PM4 transistor, an NM3 transistor, an NM4 transistor, and a PM5 transistor. The gate of the PM3 transistor is connected to the gate of the PM1 transistor. The source of the PM3 transistor and the source of the PM5 transistor are both connected to the drain of the startup load capacitor. The drain of the PM3 transistor is connected to the source of the PM4 transistor. The gate of the PM4 transistor is respectively connected to the gate of the NM3 transistor and the output end of the first-stage Schmitt trigger. The drain of the PM4 transistor is connected to the source of the NM3 transistor. The drain of the NM3 transistor and the source of the NM4 transistor are both grounded. The gate of the PM5 tube is respectively connected to the control end of the second-stage Schmitt trigger, the drain of the PM4 tube and the gate of the NM4 tube, the drain of the PM5 tube is connected to the first bias end of the second-stage Schmitt trigger, and the drain of the NM4 tube is connected to the second bias end of the second-stage Schmitt trigger.

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