Method for protecting transistor, protection circuit and control circuit

Abstract

The invention discloses a method for protecting a transistor, a protection circuit and a control circuit. The protection circuit comprises a first protection circuit; one end of the first protection circuit is connected with the driving signal output end of the driving circuit, and the other end is connected with the driving end of the to-be-driven transistor; the first protection circuit is used for sharing the charging voltage of the driving end capacitor of the transistor to be driven when the driving voltage provided by the driving circuit enables the first voltage of the first protection circuit not to reach the first working voltage; when the driving voltage provided by the driving circuit enables the first voltage to reach the first working voltage, entering a first conduction state, and controlling the conduction or turn-off of the to-be-driven transistor according to the driving voltage in the first conduction state; and under the condition that the transistor to be driven is conducted, when the driving voltage provided by the driving circuit enables the second voltage of the first protection circuit to reach the second working voltage, the first protection circuit enters a first turn-off state, and the transistor to be driven is controlled to be turned off or conducted after entering the first turn-off state.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a method for protecting a transistor, a protection circuit and a control circuit. Background Art

[0002] GaN HEMT devices are increasingly being used in various power products due to their superior high-frequency performance and high switching energy conversion efficiency. Currently, commercial HEMT devices are all devices that work on the principle of two-dimensional electron gas channel. Among them, GaN HEMT devices are generally divided into two types: normally off, that is, enhancement-mode HEMT devices, and normally on, that is, depletion-mode HEMT devices. For most applications, normally off devices are desired. The current mainstream implementation methods of enhancement-mode HEMT devices include P-type GaN gate, groove gate, and Si MOSFET plus normally on GaN HEMT device cascade structure. For normally on devices, negative voltage output drive circuits are usually used to drive, while for normally closed devices, although conventional drive chips can be used to drive, the voltage of the drive signal needs to be customized, and negative voltage shutdown protection circuits are also required. For the cascade structure, the driver chip actually drives Si MOSFET, so the threshold voltage, dv / dt, di / dt and other performance are basically the same as Si MOSFET, but GaN HEMT devices with this structure cannot fully play the advantages of HEMT devices. For GaN HEMT normally-off devices with P-type GaN gate or groove gate structure, due to the physical characteristics of the device itself, it is usually very different from Si MOSFET in terms of threshold voltage, dv / dt, di / dt and other performances. For example, the gate threshold voltage is generally lower and the maximum gate withstand voltage is also lower than that of general Si MOSFET. Therefore, most mature driver chips in silicon-based circuits cannot be directly used to drive GaN HEMT devices. It is usually necessary to add control functions such as negative voltage shutdown and various gate voltage clamping circuits (such as Miller clamping circuits) to complete the driving of GaN HEMT devices and protect the gate of GaN HEMT devices from damage. Negative voltage shutdown not only increases the design complexity of the drive circuit, but also brings about the problem of excessive negative voltage causing damage to HEMT devices.

[0003] One of the advantages of GaN HEMT devices is that its conductive channel is a two-dimensional electron gas, so it has a very high carrier density and mobility. Correspondingly, high dv / dt and di / dt will be generated during the switching process of the device on and off. On the one hand, this special performance reduces the switching loss of the device and improves the energy utilization efficiency, but on the other hand, due to the effects of parasitic inductance and parasitic capacitance, the device's false start-up will cause damage to the circuit operation. The field of RF applications is the application scenario with high switching frequency requirements, and the application scenario with low switching frequency but large output current and operating voltage. In particular, when GaN HEMT devices are used to form a half-bridge or full-bridge circuit, when the lower half bridge is off and the upper half bridge changes from off to on, the upper half bridge loads a high voltage to the drain of the lower half bridge transistor, and discharges through the parasitic capacitance between the gate and the drain, which may cause the Vgs of the lower half bridge transistor to be forward biased and greater than the threshold voltage, resulting in a mis-turn-on problem. Another application scenario is that in the process of switching the switch states of the upper and lower half-bridge switches, it is easy for the negative voltage of the gate to be too large when the switch is turned off, which will cause the lower half-bridge switch to be mis-turned on when the inductive load is continuing current.

[0004] Since the driving signal from the driving circuit has various electromagnetic interferences or parasitic effects in the overall circuit loop during the alternating high and low level changes of the signal, it is often accompanied by voltage overcharge, that is, in the process of the voltage changing from low to high and reaching a high potential stability, there will be a short-term overcharge voltage higher than the stable high potential. For conventional silicon-based power devices, since their gate capacitance is generally large and the gate withstands strong voltage, they have a strong ability to resist such transient overcharge voltage and are not prone to gate failure caused by voltage overshoot. For GaN HEMT devices, due to the particularity of the gate structure, their ability to withstand transient surge voltage is weak, which often causes damage to the gate of the device.

[0005] Moreover, when the HEMT device is turned off, a large dv / dt and di / dt will be generated. The gate-source capacitance will be charged and discharged through the equivalent inductive inductance coupled in the gate-source loop, which is reflected in the voltage change between the gate and the source. After reaching a low potential, there will be a short potential rebound. Since the gate threshold voltage of the HEMT device is generally low, it is easy to cause the device to be turned on by mistake.

[0006] That is to say, the protection circuit in the related art cannot solve the problem of mis-conduction of GaN HEMT devices, nor can it effectively help the gate of GaN HEMT devices avoid damage from circuit parasitic effects, and it cannot achieve the regulation of the driving voltage of GaN HEMT devices. Summary of the invention

[0007] In order to solve the above problems existing in the related art, the present invention provides a method, a protection circuit and a control circuit for protecting a transistor. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0008] The present invention provides a method for protecting a transistor, which is applied to a transistor control signal input terminal protection circuit, wherein the transistor control signal input terminal protection circuit is connected between a driving circuit and a transistor to be driven, and comprises:

[0009] When the driving voltage provided by the driving circuit makes the first voltage of the transistor control signal input terminal protection circuit not reach the first working voltage, sharing the charging voltage of the driving end capacitor of the transistor to be driven;

[0010] When the driving voltage provided by the driving circuit makes the first voltage reach the first operating voltage, the first conducting state is entered, and the resistance is reduced after entering the first conducting state, and a driving current is provided to the transistor to be driven according to the driving voltage provided by the driving circuit and the reduced resistance, so as to control the conduction or shut-down of the transistor to be driven;

[0011] In the case where the transistor to be driven is turned on, when the driving voltage provided by the driving circuit makes the second voltage of the transistor control signal input terminal protection circuit reach the second working voltage, the first off state is entered, and after entering the first off state, the transistor to be driven is controlled to be turned off or turned on;

[0012] Among them, among the first working voltage and the second working voltage, one working voltage is a forward voltage, and the other working voltage is a reverse voltage.

[0013] The present invention also provides a transistor control signal input terminal protection circuit, comprising: a first protection circuit; one end of the first protection circuit is connected to the drive signal output end of the drive circuit, and the other end of the first protection circuit is connected to the drive end of the transistor to be driven;

[0014] The first protection circuit is used to share the charging voltage of the driving end capacitor of the transistor to be driven when the driving voltage provided by the driving circuit makes the first voltage of the first protection circuit not reach the first working voltage; enter a first on-state when the driving voltage provided by the driving circuit makes the first voltage reach the first working voltage, and control the on or off of the transistor to be driven according to the driving voltage in the first on-state; when the transistor to be driven is turned on, when the driving voltage provided by the driving circuit makes the second voltage of the first protection circuit reach the second working voltage, enter a first off-state, and control the transistor to be driven to be turned off or on after entering the first off-state;

[0015] Among them, the first operating voltage is greater than the threshold voltage of the transistor to be driven; among the first operating voltage and the second operating voltage, one operating voltage is a forward voltage, and the other operating voltage is a reverse voltage.

[0016] The present invention also provides a transistor control signal input electrode protection circuit, which is connected to an enhanced GaN HEMT device, a driving circuit and a switch device respectively; the switch device is a normally-on JFET tube or a depletion MOS tube; the transistor control signal input electrode protection circuit comprises: a first enhanced MOS tube, a second enhanced MOS tube and a diode;

[0017] When the first enhancement-mode MOS transistor is an NMOS transistor, the driving end and the drain of the first enhancement-mode MOS transistor are connected to each other and then connected to the driving signal output end of the driving circuit, the source of the first enhancement-mode MOS transistor is connected to the driving end of the enhancement-mode GaN HEMT device, and the source of the first enhancement-mode MOS transistor is connected to the substrate of the channel region and are connected at the same potential; when the first enhancement-mode MOS transistor is a PMOS transistor, the drain of the first enhancement-mode MOS transistor is connected to the driving signal output end, the source of the first enhancement-mode MOS transistor and the driving end are connected to each other and then connected to the driving end of the enhancement-mode GaN HEMT device, and the drain of the first enhancement-mode MOS transistor is connected to the substrate of the channel region and are connected at the same potential;

[0018] The first enhancement mode MOS transistor is used to share the charging voltage of the driving end capacitor of the enhancement mode GaN HEMT device when the driving voltage provided by the driving circuit makes the voltage of the driving end of the first enhancement mode MOS transistor fail to reach the turn-on voltage of the driving end of the first enhancement mode MOS transistor; when the driving voltage provided by the driving circuit makes the voltage of the driving end of the first enhancement mode MOS transistor reach the turn-on voltage, the first enhancement mode MOS transistor enters the on state, and controls the conduction of the enhancement mode GaN HEMT device according to the driving voltage in the on state; when the enhancement mode GaN HEMT device is turned on, when the driving voltage provided by the driving circuit makes the voltage of the driving end of the first enhancement mode MOS transistor less than the turn-on voltage, the first enhancement mode MOS transistor enters the off state, and controls the enhancement mode GaN HEMT device to be turned off after entering the off state;

[0019] Wherein, the turn-on voltage of the driving end of the first enhancement mode MOS tube is greater than the threshold voltage of the enhancement mode GaN HEMT device;

[0020] The driving electrode of the normally-on JFET tube or the depletion-mode MOS tube is connected to the driving signal output terminal of the driving circuit, the drain of the normally-on JFET tube or the depletion-mode MOS tube is connected to the driving end of the enhancement-mode GaN HEMT device, and the source of the normally-on JFET tube or the depletion-mode MOS tube is connected to the source of the enhancement-mode GaN HEMT device;

[0021] The normally-on JFET tube or the depletion-mode MOS tube is used to provide a one-way free path for charges between the driving end of the enhancement-mode GaN HEMT device and the source of the enhancement-mode GaN HEMT device when the driving voltage provided by the driving circuit makes the driving end voltage of the normally-on JFET tube or the depletion-mode MOS tube not reach the turn-off voltage of the driving end of the normally-on JFET tube or the depletion-mode MOS tube; when the driving voltage provided by the driving circuit reaches the turn-off voltage of the driving end of the normally-on JFET tube or the depletion-mode MOS tube, the normally-on JFET tube or the depletion-mode MOS tube enters the turn-off state;

[0022] Wherein, the turn-off voltage of the driving end of the normally-on JFET tube or the depletion-mode MOS tube is less than the turn-on voltage of the driving end of the first enhancement-mode MOS tube;

[0023] When the second enhancement mode MOS transistor is an NMOS transistor, the driving end and the drain of the second enhancement mode MOS transistor are connected to each other and then connected to the driving end of the enhancement mode GaN HEMT device, the source of the second enhancement mode MOS transistor is connected to one end of the driving circuit and the source of the enhancement mode GaN HEMT device respectively, and the source of the second enhancement mode MOS transistor is connected to the substrate of the channel region and is connected at the same potential; when the second enhancement mode MOS transistor is a PMOS transistor, the drain of the second enhancement mode MOS transistor is connected to the driving end of the enhancement mode GaN HEMT device, the source of the second enhancement mode MOS transistor is connected to the driving end and then connected to one end of the driving circuit, and the drain of the second enhancement mode MOS transistor is connected to the substrate of the channel region and is connected at the same potential; the voltage of the driving end of the first enhancement mode MOS transistor or the second enhancement mode MOS transistor is the voltage difference between the driving electrode and the source of the first enhancement mode MOS transistor or the second enhancement mode MOS transistor; the anode of the diode is connected to one end of the second enhancement mode MOS transistor, and the cathode of the diode is connected to one end of the driving circuit.

[0024] The present invention also provides a control circuit, comprising: a driving circuit, a plurality of the above-mentioned transistor control signal input electrode protection circuits, and a plurality of transistors to be driven corresponding to the plurality of the above-mentioned transistor control signal input electrode protection circuits one by one;

[0025] A plurality of transistors to be driven are connected in parallel, and a driving end of each transistor to be driven is connected to a driving signal output end of the driving circuit through a corresponding transistor control signal input terminal protection circuit;

[0026] When the driving signal provided by the driving circuit causes the plurality of transistor control signal input terminal protection circuits to enter, and the first voltage of the first protection circuit reaches the first operating voltage, the plurality of transistor control signal input terminal protection circuits simultaneously enter the first on-state, and after entering the first on-state, each of the first protection circuits adjusts the driving current of the corresponding transistor to be driven according to the driving voltage and the variable resistor provided by the driving circuit, so as to control the synchronous change of the driving terminal voltages of the plurality of transistors to be driven; the synchronous change of the driving terminal voltages of the plurality of transistors to be driven is used to control the simultaneous on or off of the plurality of transistors to be driven;

[0027] In the case that multiple transistors to be driven are turned on, when the driving voltage provided by the driving circuit makes the second voltage of the first protection circuit reach the second operating voltage, multiple transistor control signal input terminal protection circuits simultaneously enter the first off-state, and after entering the first off-state, control the multiple transistors to be driven to maintain synchronous off or on.

[0028] The present invention has the following beneficial technical effects:

[0029] In the present invention, when the first voltage of the transistor control signal input terminal protection circuit does not reach the first working voltage, the charging voltage of the driving end capacitor of the transistor to be driven is shared, thereby realizing the functions of driving buffering and false start-up protection of the transistor to be driven, effectively avoiding false start-up of the transistor to be driven, and avoiding damage to the driving end of the transistor to be driven; and, by adding a transistor control signal input terminal protection circuit between the transistor to be driven and the driving circuit, that is, the signal of the driving circuit is first transmitted to the protection circuit, and then the signal is transmitted to the driving end of the transistor to be driven after the signal meets the conditions for the normal startup of the protection circuit. For the driving circuit, the protection circuit and the transistor to be driven together constitute an equivalent transistor. When the protection circuit is working, it is equivalent to providing an equivalent driving end threshold voltage for the transistor to be driven. By adopting the protection circuit based on the working principle of the present application to protect the transistor to be driven, the adjustment of the equivalent gate threshold voltage of the transistor can be realized.

[0030] The transistor control signal input terminal protection circuit in the present invention can be packaged in a transistor package by forming a chip seal with the transistor to be driven to form an equivalent discrete device of the transistor to be driven, or it can be integrated in the driving circuit as an interface circuit connected to the transistor to be driven, or as a separate circuit chip connecting the driving circuit and the discrete device of the transistor to be driven.

[0031] In the present invention, by connecting a transistor control signal input terminal protection circuit including a first enhancement MOS transistor, a second enhancement MOS transistor and a diode between an enhancement GaN HEMT device and a driving circuit, the equivalent threshold voltage of the enhancement GaN HEMT device can be increased, that is, through the protection circuit, the driving voltage of the driving circuit must reach the threshold voltage of the enhancement GaN HEMT device plus the driving voltage of the first enhancement MOS transistor before the enhancement GaN HEMT device can be turned on, and the driving end of the enhancement GaN HEMT device can be protected from being damaged by an excessively high voltage; by turning on a normally-on JFET transistor or a depletion MOS transistor when the first enhancement MOS transistor is turned off, a one-way charge path between the driving terminal and the source of the enhancement GaN HEMT device can be provided, so that the voltage of the driving terminal of the GaN HEMT device is consistent with the source, and by turning off a normally-on JFET transistor or a depletion MOS transistor when the first enhancement MOS transistor is turned on, it can be ensured that the driving signal of the driving circuit charges the driving end of the GaN HEMT device through the first enhancement MOS transistor and the charge does not directly flow to the source of the GaN HEMT device.

[0032] After the present invention adds a protection circuit in front of the driving electrodes (driving ends) of multiple transistors to be driven, since the conductive path resistance of the protection circuit is regulated by the first working voltage, when the driving electrode voltage of a certain transistor to be driven among the multiple transistors to be driven rises faster than that of other transistors, the protection circuit connected to the transistor to be driven will increase the path resistance due to the effect of the first working voltage, thereby reducing the current of the driving electrode of the transistor to be driven, slowing down the rising speed of the driving electrode voltage of the transistor to be driven, and finally realizing the synchronous rising of the driving electrode voltages of the multiple transistors to be driven, so as to achieve the synchronous turning on of the multiple transistors to be driven. Similarly, the principle of synchronously turning off the multiple transistors to be driven is similar to this principle.

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the connection relationship between the transistor control signal input terminal protection circuit, the driving circuit and the transistor to be driven provided by an embodiment of the present invention;

[0035] Figure 2 An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 1 ;

[0036] Figure 3 An example of a change in the working state of a device in a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 1 ;

[0037] Figure 4 An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 2 ;;

[0038] Figure 5 An example of a change in the working state of a device in a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 2 ;

[0039] Figure 6 An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 3 ;

[0040] Figure 7 An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 4 ;

[0041] Figure 8 An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 5 ;

[0042] Fig. 9 An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 6 ;

[0043] Fig.10 An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 7 ;

[0044] Fig.11 An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 8 ;

[0045] Fig.12 An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 9 ;

[0046] Fig.13 An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 10 ;

[0047] Fig.14An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 10 one;

[0048] Fig.15 An example of a transistor control signal input terminal protection circuit provided by an embodiment of the present invention Figure 10 two;

[0049] Fig.16 An exemplary diagram of a control circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0051] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0052] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0053] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0054] The present invention provides a method for protecting a transistor, which is applied to a transistor control signal input pole protection circuit. The transistor control signal input pole protection circuit is connected between a driving circuit and a transistor to be driven, and comprises: when a driving voltage provided by a driving circuit makes a first voltage of the transistor control signal input pole protection circuit fail to reach a first working voltage, sharing the charging voltage of a driving end capacitor of the transistor to be driven; when a driving voltage provided by a driving circuit makes the first voltage reach a first working voltage, entering a first on-state, and reducing resistance after entering the first on-state, providing a driving current for the transistor to be driven according to the driving voltage provided by the driving circuit and the reduced resistance, so as to control the on or off of the transistor to be driven; when the transistor to be driven is turned on, when a driving voltage provided by the driving circuit makes a second voltage of the transistor control signal input pole protection circuit reach a second working voltage, entering a first off-state, and controlling the transistor to be driven to be turned off or on after entering the first off-state; wherein, of the first working voltage and the second working voltage, one working voltage is a forward voltage, and the other working voltage is a reverse voltage.

[0055] For example, when the first operating voltage is +5V, the second operating voltage is -5V; when the first operating voltage is -5V, the second operating voltage is +5V.

[0056] In some embodiments, after entering the first off state, the second on state is entered, and the transistor to be driven is controlled to be off or on in the second on state.

[0057] In some embodiments, after the transistor to be driven is turned on, when the driving voltage provided by the driving circuit makes the third voltage of the transistor control signal input terminal protection circuit reach the third operating voltage, it enters the third conduction state, and reduces the resistance in the third conduction state, and controls the driving end of the transistor to be driven to stop charge accumulation or release part of the accumulated charge according to the reduced resistance, so as to control the absolute value of the voltage at the driving end of the transistor to be driven to be less than the absolute value of the maximum withstand voltage of the driving end of the transistor to be driven.

[0058] In some embodiments, when the driving voltage provided by the driven circuit reaches a fourth operating voltage, the second off state is entered to cut off the free charge path between the driving end of the driven transistor and the source of the driven transistor; the absolute value of the fourth operating voltage is less than the absolute value of the first operating voltage.

[0059] In some embodiments, after entering the first off state, the second on state is entered, and the transistor to be driven is controlled to be off in the second on state.

[0060] In some embodiments, the resistance is reduced after entering the first conduction state, and a driving current is provided to the transistor to be driven according to the driving voltage provided by the driving chip and the reduced resistance, so as to control the conduction of the transistor to be driven.

[0061] In some embodiments, when the transistor to be driven is a positive voltage conduction device, after the transistor to be driven is controlled to be turned off, when the driving chip outputs a negative voltage signal, the residual positive charge at the driving end of the transistor to be driven is extracted according to the negative voltage signal; when the transistor to be driven is a negative voltage conduction device, after the transistor to be driven is controlled to be turned off, when the driving chip outputs a positive voltage signal, positive charge is injected into the driving end of the transistor to be driven according to the positive voltage signal.

[0062] In some embodiments, after entering the third conduction state, current is prevented from entering the driving end of the transistor to be driven via a channel that releases the charge at the driving end of the transistor to be driven.

[0063] In some embodiments, after the transistor to be driven is turned on, when the transistor control signal input terminal protection circuit does not enter the third conduction state, the charge reaching the driving end of the transistor to be driven is shared.

[0064] In some embodiments, the resistance is reduced after entering the third conduction state, and a discharge current is provided for the transistor to be driven according to the reduced resistance.

[0065] The invention also provides a transistor control signal input terminal protection circuit. Figure 1 Schematic diagram of the connection relationship between the transistor control signal input terminal protection circuit, the driving circuit and the transistor to be driven provided by the embodiment of the present invention. Figure 1 As shown, the transistor control signal input electrode protection circuit includes a first protection circuit 1, one end of the first protection circuit 1 is connected to the drive signal output end of the drive circuit 2, and the other end of the first protection circuit 1 is connected to the drive end of the transistor 3 to be driven. The first protection circuit 1 is used to share the charging voltage of the drive end capacitor of the transistor 3 to be driven when the drive voltage provided by the drive circuit 2 makes the first voltage of the first protection circuit 1 not reach the first working voltage; when the drive voltage provided by the drive circuit 2 makes the first voltage reach the first working voltage, the first protection circuit 1 enters the first conduction state, and controls the conduction or disconnection of the transistor 3 to be driven according to the drive voltage in the first conduction state. When the transistor 3 to be driven is turned on, when the drive voltage provided by the drive circuit 2 makes the second voltage of the first protection circuit 1 reach the second working voltage, the first protection circuit 1 enters the first off state, and controls the transistor 3 to be driven to be turned off or on after entering the first off state; wherein, the first working voltage of the first protection circuit 1 is greater than the threshold voltage of the transistor 3 to be driven; of the first working voltage and the second working voltage, one working voltage is a forward voltage, and the other working voltage is a reverse voltage.

[0066] Here, the driving circuit may be a driving chip. The transistor to be driven may be an enhancement-mode transistor turned on by a positive voltage, for example, an enhancement-mode GaN HEMT device, or an enhancement-mode transistor turned on by a negative voltage.

[0067] In some embodiments, the first protection circuit 1 includes: a first capacitor C1, a first circuit module and a first unidirectional conductive device D1. Specifically, the first circuit module includes a variable resistor R1 and a switch K1, wherein R1 and K1 can be referred to as path 1, and D1 is referred to as path 2. The above-mentioned first voltage is the forward voltage across C1, and the corresponding above-mentioned first working voltage is a set threshold value (hereinafter referred to as threshold 1); the above-mentioned second voltage is the reverse voltage across C1, and the corresponding above-mentioned second working voltage is another set threshold value (hereinafter referred to as threshold 2). The absolute value of threshold 1 is greater than the absolute value of the threshold voltage of the transistor 3 to be driven; the absolute value of threshold 2 is less than the absolute value of threshold 1. Path 1, path 2 and C1 are all connected in parallel, and the working current directions of path 1 and path 2 are opposite. One end of path 1, path 2 and C1 is connected to the drive signal output end of the drive circuit 2, and the other end of path 1, path 2 and C1 is connected to the drive end of the transistor 3 to be driven. When the voltage of C1 does not reach the first working voltage, C1 is used to share the charging voltage of the driving end capacitor of the transistor 3 to be driven; when the voltage of C1 reaches the first working voltage, the path 1 is turned on, and after the path 1 is turned on, the conduction of the transistor 3 to be driven is controlled according to the driving voltage provided by the driving circuit 2. When the voltage of C1 is less than the first working voltage, the path 1 is turned off, and after the path 1 is turned off and the reverse voltage of C1 reaches the second working voltage, the path 2 is turned on, and after the path 2 is turned on, the transistor 3 to be driven is controlled to be turned off. The path 2 provides an electrical connection channel between the driving circuit 2 and the driving end of the transistor 3 to be driven, and the unidirectional conduction of the current is realized through the channel.

[0068] In the above-mentioned path 2, when K1 is turned on, the resistance of R1 decreases rapidly, thereby obtaining a larger driving current to drive the transistor to be driven 3 to turn on, thereby reducing the time used to drive the transistor to be driven 3 to turn on.

[0069] In some embodiments, D1 can be at least one diode or at least one transistor. For example, D1 can be an IGBT, an enhancement or depletion Si MOSFET / SiC MOSFET or other MOSFET, or various types of JFET, BJT, etc. The specific connection methods may vary, but the functions achieved are all to achieve the above-mentioned unidirectional conduction function. For example, Figure 2 As shown, D1 can be a diode. Figure 2 and Figure 3 , and with Figure 2Taking the transistor 3 to be driven as a GaN HEMT device and the driving circuit 2 as a driving chip as an example, the working principle of the first protection circuit is explained.

[0070] like Figure 2 As shown, when the voltage of C1 reaches the above threshold 1, K1 will be turned on, and the electrical connection between the driver chip and the gate of the GaN HEMT device formed by the path 1 is switched to the on state, and C1 and the equivalent gate-source capacitance of the GaN HEMT device and the driving signal end of the driver chip are in series mode, that is, the voltage difference between the driver chip and the gate of the GaN HEMT device will be shared by the above C1 and the gate-source capacitance of the GaN HEMT device, and the voltage borne by each is related to the ratio of the capacitance of the two. When the reverse voltage of C1 reaches the above threshold 2, the path 2 starts to conduct.

[0071] Take the periodic signal as an example, where the voltage at the signal input terminal gradually increases from the initial value to a set value, maintains the set value for a period of time, and then decreases to the initial value. Figure 3As shown, as the voltage at the signal input terminal gradually increases from the initial value, from 0 to t1, C1 and the gate-source capacitance of the GaN HEMT device are in series mode and the driving signal of the driver chip has no other current path to charge the gate-source capacitance of the GaN HEMT device. When C1 continues to charge and the voltage rises, and K1 is in the off state, the resistance of R1 is close to the maximum value, and the voltage at the signal output terminal also rises synchronously. The rise amplitude is determined by the ratio of C1 to the gate-source capacitance. At t1, the voltage across C1 reaches the threshold 1. At this time, K1 is turned on. From t1 to t2, the voltage at the signal input terminal continues to rise. At the same time, the driving signal directly charges the gate-source capacitance through path 1. The resistance of R1 drops rapidly to a value close to the minimum value. The voltage at the signal output terminal rises synchronously and always remains lower than the voltage at the signal input terminal. From t2 to t3, the voltage at the signal input terminal remains constant, the voltage value on C1 remains constant, K1 remains turned on, the resistance of R1 remains close to the minimum value, and the voltage at the signal output terminal remains constant. Normally, between t1 and t2, the gate-source-drain capacitance is charged to a voltage exceeding the threshold voltage of the GaN HEMT device (hereinafter referred to as threshold T), and the GaN HEMT device is turned on. From t2 to t3, the GaN HEMT device remains in the on state. From t3 to t4, the voltage at the signal input terminal begins to decrease, the voltage on C1 drops rapidly and eventually becomes a reverse voltage drop, and at t4, the voltage at the signal output terminal is higher than the voltage at the signal input terminal, that is, the voltage on C1 is a negative voltage. When the voltage on K1 is lower than the turn-on voltage of K1, K1 begins to turn off rapidly, and at t4, K1 is in the off state. The resistance of R1 begins to gradually increase at t3, and the resistance at t4 is close to the maximum value, because the direction of current flow allowed by path 2 is opposite to that of path 1, so no current passes through path 2 from 0 to t4, that is, the voltage at the signal output terminal has no charge release channel, so it will maintain the voltage value at t3. At t4, the voltage at the signal input terminal is lower than the voltage at the signal output terminal, and has reached the threshold 2 of path 2 conduction, and path 2 begins to conduct. From t4 to t5, the voltage at the signal input terminal further decreases, the voltage across C1 remains in a negative voltage state, K1 remains in an off state, R1 remains close to the maximum value, and the voltage at the signal output terminal releases the charge through path 2, and the voltage gradually decreases and always remains a fixed value higher than the voltage at the signal input terminal. After t5 until the next signal input terminal voltage rise cycle, the signal input terminal voltage remains at a low potential, the voltage across C1 remains at a negative voltage or zero voltage, K1 remains in an off state, R1 remains close to the maximum value, and the signal output terminal voltage remains at a low voltage state. Figure 3 In the example, time points t1 and t2 can coincide, that is, the voltage at the signal input terminal only reaches threshold 1 at most, and threshold 1 is greater than threshold T.

[0072] In some embodiments, the driving circuit 2 includes a negative voltage port, and the negative voltage port is connected to one end of the above-mentioned passage 2. During the period when the driving signal output end of the driving circuit 2 sends a driving signal pulse, the negative voltage port of the driving voltage does not work, and when the driving signal output end of the driving circuit 2 is not working, a negative electrical signal is output for a period of time through the negative voltage port, thereby discharging the residual charge of the driving end of the transistor 3 to be driven, ensuring that the transistor to be driven is turned off. Specifically, when the transistor 3 to be driven is a positive voltage driving device, and after the transistor 3 to be driven is controlled to be turned off, when the negative voltage port of the driving circuit outputs a negative voltage signal, the residual positive charge of the driving end (for example, the gate) of the transistor 3 to be driven is extracted through the passage 2. When the transistor 3 to be driven is a negative voltage driving device, and after the transistor 3 to be driven is controlled to be turned off, when the negative voltage port of the driving circuit outputs a negative voltage signal, a positive charge is injected into the driving end of the transistor 3 to be driven through the passage 2. In this way, the duration of the negative voltage signal can be set to reduce the damage and failure of the transistor caused by the negative bias voltage exceeding the driving end of the transistor to be driven due to long-term negative voltage shutdown, that is, the residual charge of the driving end of the transistor to be driven is discharged through a short negative voltage signal to ensure that the transistor is turned off, but there is no need to maintain the negative voltage continuously to ensure that the transistor is not turned on by mistake, thereby reducing the electric field stress damage caused by the negative voltage at the driving end and the high positive voltage at the drain, and protecting the driving end of the transistor. Compared with the existing design of negative voltage shutdown in the prior art, which usually needs to maintain the negative voltage continuously at other times when the driver chip sends the driving signal pulse to turn on the transistor to ensure that the transistor is not turned on by mistake, it has a good technical effect.

[0073] In some embodiments, the first protection circuit 1 is a first MOS tube M1; one end of the first MOS tube M1 is connected to the driving signal output end of the driving circuit 2, and the other end of the first MOS tube M1 is connected to the driving end of the transistor to be driven 3, and the driving end start-up voltage of the first MOS tube M1 is the above-mentioned first working voltage.

[0074] Specifically, when the transistor 3 to be driven is a positive voltage driving device, and M1 is an NMOS tube, the driving end and the drain of M1 are connected to each other and then connected to the driving signal output end of the driving circuit 2, the source of M1 is connected to the driving end of the transistor 3 to be driven, and the source of M1 is connected to the substrate of the channel region and is connected at the same potential. Specifically, when the transistor 3 to be driven is a positive voltage driving device, and M1 is a PMOS tube, the drain of M1 is connected to the driving signal output end of the driving circuit 2, the source of M1 is connected to the driving end of the transistor 3 to be driven and then connected to the driving end, and the drain of M1 is connected to the substrate of the channel region and is connected at the same potential. Specifically, when the transistor 3 to be driven is a negative voltage driving device, and M1 is an NMOS tube, the source of M1 is connected to the driving signal output end, the drain of M1 is connected to the driving end of the transistor 3 to be driven and then connected to the driving end, and the source of M1 is connected to the substrate of the channel region and is connected at the same potential. Specifically, when the transistor 3 to be driven is a negative voltage driving device and M1 is a PMOS tube, the source and the driving end of M1 are connected to each other and then connected to the driving signal output end of the driving circuit 2, the drain of M1 is connected to the driving end of the transistor 3 to be driven, and the drain of M1 is connected to the channel region substrate and is connected at the same potential.

[0075] The first protection circuit proposed by the present invention connects a Si MOS tube M1 in series between the gate drive signal (i.e., the drive signal output terminal) of the driver chip and the gate of the GaN HEMT device. The drive signal output by the driver chip is used as the gate start signal of M1 and also as the drain input voltage of M1. When the output voltage of the drive signal is higher than the gate start voltage of M1, M1 is fully turned on. The output voltage of the drive signal can be smoothly transmitted to the source of M1, and then transmitted to the gate of the GaN HEMT device. When the output voltage of the drive signal is higher than the threshold voltage of the gate of the GaN HEMT device, the GaN HEMT device is turned on. Furthermore, by setting the gate start voltage of M1 to be greater than the threshold voltage of the gate of the GaN HEMT device, it is equivalent to increasing the threshold voltage of the gate of the GaN HEMT device, so that the problem that the gate threshold voltage of the GaN HEMT device is low and cannot be compatible with most mature Si MOSFET drivers can be overcome, and the gate start speed of the GaN HEMT device can be adjusted. Therefore, in a module circuit in which multiple GaN HEMT devices are connected in parallel, synchronous gate start protection can be provided for each GaN HEMT device. When the output voltage of the driving signal switches to the off voltage, when the voltage transmitted to the gate of M1 (the voltage transmitted to the gate of M1 is the output voltage of the driving signal minus the voltage on the gate of the GaN HEMT device at this time) is lower than the gate turn-on voltage of M1, M1 is in the off state. When the output voltage of the driving signal is lower than the voltage on the gate of the GaN HEMT device, the positive charge on the gate of the GaN HEMT device can be discharged from the channel substrate to the drain through the body diode of M1 until the GaN HEMT device is turned off. Furthermore, when the GaN HEMT device generates a large induced voltage in the circuit loop due to the dv / dt or di / dt effect or other crosstalk, the gate of M1 connected in series to the gate of the GaN HEMT device can provide a capacitive isolation for the gate of the GaN HEMT device to avoid the GaN HEMT device from being turned on by mistake or damaging the gate.

[0076] In some embodiments, the transistor control signal input electrode protection circuit (hereinafter may also be referred to as the transistor signal input electrode protection circuit or the transistor input electrode protection circuit) further includes: a second protection circuit 4; one end of the second protection circuit 4 is connected to the driving end of the transistor 3 to be driven, and the other end of the second protection circuit 4 is respectively connected to one end of the driving circuit 2 and the other end of the transistor 3 to be driven. The second protection circuit 4 is used for, after the transistor 3 to be driven is turned on, when the driving voltage provided by the driving circuit 2 makes the third voltage of the second protection circuit 4 reach the third working voltage, the second protection circuit 4 enters the third on-state, and in the third on-state, controls the driving end of the transistor 3 to be driven to stop accumulating charges or release part of the accumulated charges, so as to control the absolute value of the voltage at the driving end of the transistor 3 to be driven to be less than the absolute value of the ultimate withstand voltage of the driving end of the transistor 3 to be driven.

[0077] In some embodiments, the second protection circuit 4 includes: a second capacitor C2, a second circuit module and a second unidirectional conductive device D2. Specifically, the second circuit module includes: a second variable resistor R2 and a second conduction control switch K2 connected in series, and the electrical path formed by R2 and K2 is called a discharge channel. C2 is connected in parallel with the discharge channel, and the discharge channel is connected in series with D2. The above-mentioned third voltage is the voltage across C2, and the corresponding third operating voltage is a preset threshold value (hereinafter referred to as threshold 3). When the voltage across C2 reaches threshold 3, K2 and D2 are turned on. After K2 is turned on, R2 reduces its own resistance, thereby obtaining a larger discharge current. The charge at the driving end of the transistor 3 to be driven can be quickly released through the discharge channel and D2 to control the voltage at the driving end of the transistor 3 to be driven to be less than the limit voltage of the driving end of the transistor to be driven. At the same time, D2 prevents the charge released from the driving end of the transistor 3 to be driven from entering the driving end of the transistor 3 to be driven again. When the discharge channel is not turned on, C2 shares the charge reaching the driving end of the transistor to be driven 3 , further protecting the driving end of the transistor to be driven 3 from being turned on by mistake.

[0078] In some embodiments, the second unidirectional conductive device D2 may be at least one diode or at least one transistor. For example, the second unidirectional conductive device D2 may be an IGBT, an enhancement or depletion type Si MOSFET / SiC MOSFET or other MOSFET, or various types of JFETs, BJTs, etc. The specific connection methods may vary, but the functions achieved are all to achieve the above-mentioned unidirectional conductive function. For example, Figure 4 As shown, the second unidirectional conductive device D2 can be a diode. Figure 4 and Figure 5 , and with Figure 4 Taking the transistor 3 to be driven as a GaN HEMT device and the driving circuit 2 as a driving chip as an example, the working principle of the second protection circuit is explained.

[0079] like Figure 4 As shown, a discharge channel composed of R2 and K2 is connected in series between the signal output end and the drive circuit end directly connected to the source of the GaN HEMT device. When K2 is in the off state, the default state of the electrical connection between the signal output end and the drive circuit end formed by the discharge channel is the off state. C2 is also connected in parallel at both ends of the discharge channel. When the voltage across C2 reaches the threshold 3, K2 will be turned on. At this time, the electrical connection between the signal output end and the drive circuit end formed by the discharge channel is switched to the on state, and the gate charge will be discharged through the discharge channel. By setting the threshold 3, it can be ensured that the gate voltage of the GaN HEMT device will not exceed the upper voltage limit that the gate can withstand. D2 is also connected in series between the discharge channel and the drive circuit end to ensure that the current from the signal output end to the drive circuit end flows unidirectionally. When the induced potential generated by the dv / dt and di / dt effects charges the gate-source capacitance, the discharge channel prevents the charging current from directly flowing into the gate. The gate-source voltage drop generated by the induced potential is mainly borne by C2 and the gate-source capacitance. By controlling the capacitance ratio of C2 and the gate-source capacitance, most of the voltage drop can be borne by C2, so that the voltage drop on the gate-source capacitance is less than the turn-on threshold voltage of the GaN HEMT device, thereby avoiding the transistor from being turned on inadvertently.

[0080] like Figure 5 As shown, still taking the periodic signal in which the voltage at the signal input terminal gradually increases from the initial value to a certain set value and maintains the set value for a period of time and then decreases to the initial value as an example, when only the second protection circuit 4 works and the first protection circuit 1 is equivalent to an input resistor, as Figure 5As shown, as the voltage at the signal input end gradually increases from the initial value, from 0 to t1, C2 and the gate-source-drain capacitance of the GaN HEMT device are in parallel mode, the driving signal charges the gate-source-drain capacitance of C2 and the GaN HEMT device at the same time, and the driving current has no other current path for charge discharge. C2 continues to charge and the voltage rises, K2 is in the off state, the resistance of R2 is close to the maximum value, and the voltage at the signal output end also rises synchronously. When t1, the voltage across C2 reaches the threshold 3, and K2 is turned on. From t1 to t2, the resistance of R2 drops rapidly to a value close to the minimum value. At this time, the signal input end forms a current path through the discharge channel and the drive loop end. The voltage at the signal output end is determined by the resistance voltage divider between these two ports and the signal output end. The current provided by the signal input end flows to the drive loop end and charges the gate-source-drain capacitance of the GaN HEMT device at the same time, and the voltage at the signal output end always maintains a fixed value. From t2 to t3, the voltage at the signal input terminal remains constant, the voltage value across C2 remains constant, K2 remains turned on, the resistance value of R2 remains close to the minimum value, and the voltage at the signal output terminal remains constant. By setting the threshold 3, for example, dynamically setting the threshold 3 to change between high and low voltages, the high voltage is higher than the gate conduction threshold voltage of the GaN HEMT device, and the low voltage is lower than the gate conduction threshold voltage of the GaN HEMT device, it is possible to control the on / off of the GaN HEMT device when the drive signal of the drive circuit 2 is in the on cycle interval. At t3, the voltage at the signal input terminal begins to decrease, and the voltage across C2 begins to decrease synchronously with the gate voltage of the GaN HEMT device. From t3 to t4, the output terminal voltage continues to decrease, causing the voltage across C2 to be less than the threshold 3, K2 begins to turn off rapidly, and R2 rises rapidly to a value close to the maximum value. At t4, K2 is in the off state, the resistance value of R2 is close to the maximum value, and the voltage drop on C2 is synchronized with the voltage drop at the signal output terminal. From t4 to t5, K2 remains in the off state, R2 remains close to the maximum value, and the voltage on C2 gradually decreases and always remains synchronized with the voltage at the signal output terminal. After t5 until the next signal input voltage rising cycle, the signal input terminal voltage remains at a low potential, the voltage on C2 remains consistent with the signal output terminal voltage, K2 remains in the off state, R2 remains close to the maximum value state, and the signal output terminal voltage remains in a low voltage state. Normally, between t1 and t2, when the gate-source gate-drain capacitance is charged to exceed the threshold voltage of the GaN HEMT device (hereinafter referred to as threshold T), the GaN HEMT device is turned on, and from t2 to t3, the GaN HEMT device remains in the on state or the size of the dynamically set threshold 3 determines whether the GaN HEMT device is turned on or off.

[0081] like Figure 6As shown, taking the periodic signal in which the voltage at the signal input terminal gradually increases from the initial value to a certain set value and maintains the set value for a period of time and then decreases to the initial value as an example, when the first protection circuit 1 and the second protection circuit 4 work simultaneously, as the voltage at the signal input terminal gradually increases from the initial value, from 0 to t1, C1 and the gate-source-gate-drain capacitor of the GaN HEMT device are in a series mode, and C2 and the gate-source-gate-drain capacitor of the GaN HEMT device are in a parallel mode (hereinafter referred to as a parallel group), the driving signal charges C1, C2 and the gate-source-gate-drain capacitor of the GaN HEMT device at the same time, the driving signal has no other current path for charging the gate-source-gate-drain capacitor of the GaN HEMT device, and the gate-source-gate-drain capacitor of the GaN HEMT device has no other current path for charge discharge except path 2, C1 continues to charge and the voltage rises, K1 is in the off state, the resistance of R1 is close to the maximum value, and the voltage at the signal output terminal also rises synchronously, and the rise amplitude is determined by the ratio of C1 to the equivalent capacitance of the parallel group, C2 continues to charge and the voltage rises, K2 is in the off state, and the resistance of R2 is close to the maximum value. At t1, the voltage of C1 reaches threshold 1, and K1 turns on. At t2, the voltage of C2 reaches threshold 3, and K2 turns on. From t1 to t2, the voltage at the signal input continues to rise, and the driving signal directly charges the parallel group capacitor through path 1. The resistance of R1 drops rapidly to a value close to the minimum value, and the voltage at the signal output rises synchronously, and always remains lower than the voltage at the signal input. The charging voltage of C2 continues to rise, K2 remains off, and the resistance of R2 remains close to the maximum value. From t2 to t3, the voltage at the signal input continues to rise, K1 will remain on, and the resistance of R1 will enter a dynamic adjustment state to maintain the voltage ( Figure 6 K2 remains on, and the resistance of R2 will enter a dynamic adjustment state to maintain the voltage ( Figure 6 (both are illustrated by low resistance graphs in the figure). At this time, the signal input terminal forms a current path with the drive circuit terminal through path 1 and the discharge channel. The voltage of the signal output terminal is determined by the resistor voltage divider on path 1 and the discharge channel. The current provided by the signal input terminal flows to the drive circuit terminal and the parallel group capacitor at the same time. The voltage of the signal output terminal begins to maintain a stable value, that is, it does not follow the further increase of the signal input terminal voltage. The voltage value on C2 also maintains a stable value. It should be noted that threshold 3 is lower than the gate withstand voltage limit of the GaN HEMT device and higher than threshold 1. In this way, the gate of the GaN HEMT device can be protected from being damaged by excessive voltage. On this basis, threshold 1 is higher than the gate turn-on threshold voltage of the GaNHEMT device, that is, when t1, the gate of the GaN HEMT device is turned on, and the GaN HEMT device enters the on state. It should also be noted that the voltage of the signal input terminal from t2 to t3 can be directly entering a stable state (such as Figure 6or it continues to rise to a certain value and then enters a stable state (as shown by the solid line in Figure 6 ), or it may rise to a certain value and then fall back to another value and then stabilize (as shown by the dotted line 2 in Figure 6), but all values ​​are not lower than the signal input terminal voltage at t2 (as mentioned above, when t2, the signal input terminal voltage reaches the threshold 3. If the signal input terminal voltage does not reach the threshold 3 during the entire cycle, then it is similar to the principle when only the first protection circuit 1 works. Therefore, the relevant state is as mentioned above. Figure 3 As shown). At t3, the voltage at the signal input terminal begins to decrease. From t3 to t4, the voltage at the signal input terminal continues to decrease. The voltage on C1 drops rapidly and eventually becomes a reverse voltage drop. K1 begins to turn off rapidly when the voltage on C1 is lower than the turn-on voltage of K1. R1 increases rapidly to near the maximum value. The capacitors of the parallel group release the charge through the discharge channel until the voltage on C2 is lower than the threshold 3, causing K2 to switch from on to off, and R2 to rise to near the maximum value, at which time the discharge channel is turned off. During the period from t3 to when both K1 and K2 are turned off, the voltage at the signal output terminal may stabilize at a certain value, depending on the voltage drop rate at the signal input terminal and the dynamic adjustment capabilities of R1 and R2. Figure 6 This is not described in more detail in the text. At t4, the voltage at the signal output end is higher than the voltage at the signal input end and meets the opening condition of path 2, that is, the voltage on C1 is a negative voltage, and path 2 begins to conduct, K1 and K2 remain in the off state, and R1 and R2 remain close to the maximum value. From t4 to t5, the voltage at the signal input end further decreases, K1 and K2 remain in the off state, R1 and R2 remain close to the maximum value, the parallel group continues to release charge through path 2, and the voltage at the signal output end gradually decreases with the voltage at the signal input end. The voltage on C2 is consistent with the voltage drop at the signal output end. After t5 until the next signal input end voltage rise cycle, the voltage at the signal input end remains at a low potential, K1 and K2 remain in the off state, R1 and R2 remain close to the maximum value, and the voltage at the signal output end remains at a low voltage state.

[0082] Above Figure 3 and Figure 6 In the figure, the voltage of C1 is negative at t4. It should be noted that this state is not applicable to the case where the signal input terminal is connected to the negative voltage output port on the driver chip. If the driver chip provides a negative voltage output port to pull the voltage of the signal input terminal to a negative value, that is, the capacitor charge of the parallel group can be completely released, then the voltage of C1 at t4 can be 0. Figure 3 and Figure 6 This will not be described in more detail.

[0083] The transistor control signal input terminal protection circuit proposed in the present application sets a normally closed switch K1 between the signal input terminal and the signal output terminal, and sets the trigger condition for K1 to turn on to the voltage at the signal input terminal rising to a value higher than the turn-on threshold voltage value of the driving terminal of the transistor 3 to be driven, so as to achieve the purpose of equivalently increasing the gate turn-on threshold voltage of the driving terminal of the transistor 3 to be driven, and also provide a more synchronous turn-on capability for multiple parallel transistors 3 to be driven. Furthermore, a capacitor C1 is set, which can share the voltage of the signal input terminal with the gate-source-gate-drain capacitance of the transistor 3 to be driven when K1 is turned off, effectively suppressing the transient induced voltage generated by dv / dt and di / dt in the driving circuit during the turn-on / off process of the transistor 3 to be driven. The function of charging the gate-source capacitance and gate-drain capacitance of the transistor 3 to be driven is effectively avoided, and the transistor 3 to be driven is turned on by mistake. Furthermore, by setting a normally closed switch K2 from the signal output end to the drive circuit end, and setting the trigger condition for turning on K2 to the voltage at the signal output end rising to a voltage close to the withstand voltage limit of the drive end of the transistor to be driven 3, the voltage at the signal output end can be always controlled within a safe range lower than the withstand voltage limit of the drive end of the transistor to be driven, thereby achieving the purpose of protecting the drive end of the transistor to be driven 3 from being damaged; at the same time, because the capacitor C2 is set, it can share the induced voltage at the drive circuit end with the gate-source-gate-drain capacitance of the transistor to be driven 3 when K2 is turned off, effectively suppressing the function of charging the gate-source capacitance and gate-drain capacitance of the transistor to be driven 3 by the transient induced voltage generated by dv / dt and di / dt in the drive circuit during the turn-on / off process of the transistor to be driven 3, solving the problem of the induced voltage charging the gate-source capacitance and gate-drain capacitance of the transistor to be driven 3 through the clamping Schottky diode or other circuit combination in other existing solutions, and the problem that the clamping voltage cannot be flexibly adjusted, effectively avoiding the erroneous turn-on of the transistor to be driven 3 and improving the driving ability of the transistor to be driven 3 in actual use.

[0084] In some embodiments, the second protection circuit includes: a second MOS tube M2. Specifically, when the transistor 3 to be driven is a positive voltage driving device, and M2 is an NMOS tube, the driving end and the drain of M2 are connected to each other and then connected to the driving end of the transistor 3 to be driven, and the source of M2 is respectively connected to one end of the driving circuit and the source of the transistor 3 to be driven, and the source of M2 is connected to the substrate of the channel region and is connected to the same potential. Specifically, when the transistor 3 to be driven is a positive voltage driving device, and M2 is a PMOS tube, the drain of M2 is connected to the driving end of the transistor 3 to be driven, and the source of M2 is connected to the driving end of the transistor 3 to be driven and then connected to one end of the driving circuit, and the drain of M2 is connected to the substrate of the channel region and is connected to the same potential. Specifically, when the transistor 3 to be driven is a negative voltage driving device, and M2 is an NMOS tube, the source of M2 is connected to the driving end of the transistor 3 to be driven, and the drain of M2 is connected to the driving end and then connected to one end of the driving circuit and the source of the transistor 3 to be driven, and the source of M2 is connected to the substrate of the channel region and is connected to the same potential. Specifically, when the transistor 3 to be driven is a negative voltage driving device, and M2 is a PMOS tube, the source of M2 is connected to the driving end and then connected to the driving end of the transistor 3 to be driven, and the drain of M2 is connected to one end of the driving circuit, and the drain of M2 is connected to the substrate of the channel region and is connected to the same potential.

[0085] In some embodiments, the second protection circuit further includes: a third unidirectional conductive device D3, which is used to prevent the current from charging the driving end capacitor of the transistor 3 to be driven via M2 when M2 is turned on.

[0086] For example, Figure 7 It is a schematic diagram of the connection relationship between M1, M2, D3, the driving chip and the enhanced HEMT device when the transistor 3 to be driven is an enhanced HEMT device (i.e., a positive voltage driving device), the driving circuit is a driving chip, and M1 and M2 are NMOS tubes. Figure 8 It is a schematic diagram of the connection relationship between M1, M2, D3, the driving chip and the enhanced HEMT device when the transistor 3 to be driven is an enhanced HEMT device (i.e., a positive voltage driving device), the driving circuit is a driving chip, and M1 and M2 are PMOS tubes. Fig. 9 It is a schematic diagram of the connection relationship between M1, M2, D3, the driving chip and the depletion-type HEMT device when the transistor 3 to be driven is a depletion-type HEMT device (ie, a negative voltage driving device), the driving circuit is a driving chip, and M1 and M2 are NMOS tubes.

[0087] Fig.10The figure is a schematic diagram of the connection relationship between M1, M2, D3, the driver chip and the depletion-type HEMT device when the transistor 3 to be driven is a depletion-type HEMT device (i.e., a negative voltage driver device), the driving circuit is a driver chip, and M1 and M2 are PMOS tubes. D represents the drain, S represents the source, and G represents the gate.

[0088] The second protection circuit proposed by the present invention connects a Si MOS tube M2 in series between the gate and source of the GaN HEMT device, the gate and drain of M2 are both connected to the gate of the GaN HEMT device, the source of M2 is connected to the source of the GaN HEMT device, and the source of M2 is connected to the substrate of the channel region and is connected at the same potential, so that the gate voltage of the GaN HEMT device is used as the gate start signal of M2 and also as the drain input voltage of M2. When the gate voltage of the GaN HEMT device is higher than the gate start voltage of M2, M2 is fully turned on, and the gate of the GaN HEMT device can release charges through the path established with the source. By setting the gate start voltage of M2 to be greater than the withstand voltage limit that the gate of the GaN HEMT device can withstand, it is equivalent to adding a clamping circuit to the gate of the GaN HEMT device, thereby overcoming the problem that it is difficult to flexibly design the clamping voltage in the existing solution, and at the same time, the resistance of the discharge path can be dynamically adjusted, and the performance will not deteriorate after repeated use, thereby increasing the stability and reliability of the clamping circuit. When the gate voltage of the GaN HEMT device drops below the gate turn-on voltage of M2, M2 is in the off state, and the charge on the gate of the GaN HEMT device stops discharging, which ensures that the gate voltage of the GaN HEMT device can be maintained at a suitable operating voltage. Furthermore, D3 is connected in series to the path in which M2 is connected in series with the gate and source of the GaN HEMT device, which ensures that when the GaN HEMT device generates a large induced voltage in the circuit loop due to dv / dt or di / dt effects or other crosstalk, the gate of the GaN HEMT device will not be charged through the above channel, causing the device to be turned on by mistake or damaging the gate.

[0089] In some embodiments, Fig.11 As shown, the second protection circuit further includes: a fourth unidirectional conducting device D4; the conducting directions of D4 and D3 are opposite, and D4 is connected in parallel with M2, and one end of D4 is connected to the clamping voltage output port of the driving chip.

[0090] In some embodiments, the first protection circuit further includes: a first resistor R11 and a second resistor R22; R11 is connected in series between the driving circuit 2 and M1; R22 is connected in series between M1 and the transistor 3 to be driven; R11 and R22 are used to adjust the charging speed and charging voltage of the driving end of the transistor 3 to be driven. In some embodiments, the second protection circuit further includes: a third resistor R33; R33 is connected in series between M2 and the transistor 3 to be driven; R33 is used to adjust the clamping protection voltage of the transistor 3 to be driven. Exemplarily, when the driving circuit is a driving chip, the transistor to be driven is an enhanced HEMT device, and M1 and M2 are both NMOS tubes, the connection relationship between R11, R22, R33 and the driving chip, M1, M2 and the enhanced HEMT device is as follows: Fig.12 shown.

[0091] In some embodiments, a fourth resistor R44 is connected in series between M1 and the transistor 3 to be driven, and between M2 and the transistor 3 to be driven. R44 is used to further adjust the charging speed and charging voltage of the driving end of the transistor 3 to be driven. In some embodiments, a fifth resistor R55 is connected in series between D3 and the driving circuit. R55 is used to adjust the discharge speed of the discharge channel. Exemplarily, when the driving circuit is a driving chip, the transistor to be driven is an enhanced HEMT device, and M1 and M2 are both NMOS tubes, the connection relationship between R11, R22, R33, R44, R55 and the driving chip, M1, M2 and the enhanced HEMT device is as follows: Fig.13 shown.

[0092] In some embodiments, the transistor control signal input electrode protection circuit provided by the present invention further includes: a third protection circuit 5; one end of the third protection circuit 5 is connected to the driving end of the transistor 3 to be driven, and the other end of the third protection circuit 5 is respectively connected to one end of the driving circuit 2 and the other end of the transistor 3 to be driven. The third protection circuit 5 provides a charge free path between the driving end and the source of the transistor 3 to be driven. The third protection circuit 5 is used to enter a second off state to cut off the charge free path between the driving end of the transistor 3 to be driven and the source of the transistor 3 to be driven when the driving voltage provided by the driving circuit 2 makes the fourth voltage of the third protection circuit 5 reach the fourth working voltage; the absolute value of the fourth working voltage is less than the absolute value of the first working voltage.

[0093] In the present invention, the second protection circuit can protect the driving electrode of the transistor to be driven from being damaged by excessive voltage. The third protection circuit provides a charge discharge channel for the driving end of the transistor to be driven when the first protection circuit is turned off, so that the voltage of the driving end is consistent with the source, but when the first protection circuit is turned on, the third protection circuit is in a closed state (because the turn-off voltage of the third protection circuit is less than the above-mentioned first turn-on voltage, so as long as the output voltage of the driving signal is higher than the turn-on voltage of the first protection circuit, the third protection circuit will definitely be turned off), ensuring that the driving signal can charge the driving end of the transistor to be driven through the first protection circuit and the charge will not flow directly to the source of the transistor to be driven, and the conduction of the second protection circuit will be triggered only when the driving signal voltage is too high, and the third protection circuit is still closed at this time.

[0094] In some embodiments, the third protection circuit 5 includes: a third capacitor C3, a third circuit module and a fifth unidirectional conductive device D5; the third capacitor C3 is connected in parallel with the third circuit module, and the third circuit module is connected in series with the fifth unidirectional conductive device. Specifically, the third circuit module includes: a third variable resistor R3 and a third conduction control switch K3 connected in series, and the electrical path formed by R3 and K3 is called path 3. C3 is connected in parallel with path 3, and path 3 is connected in series with D5. The above-mentioned fourth voltage is the voltage across C3, and the corresponding fourth operating voltage is a preset threshold value (hereinafter referred to as threshold value 4), and the absolute value of threshold value 4 is less than the absolute value of the above-mentioned threshold value 1. When the voltage across C3 does not reach the threshold value 4, D5 is turned on, and K3 is turned on, the resistance of R3 decreases rapidly, so that the path 3 is also turned on, and the charge at the driving end of the transistor 3 to be driven flows freely in one direction between the driving end of the transistor 3 to be driven and the source of the transistor 3 to be driven through the path 3 and D5. When the voltage across C3 reaches and / or exceeds the threshold value 4, K3 is turned off to cut off the free charge path between the driving end of the transistor 3 to be driven and the source of the transistor 3 to be driven, so that the charge at the driving end of the transistor 3 to be driven cannot be released through the path 3 and D5. Exemplarily, in the case where the driving circuit is a driving chip and the transistor to be driven is an enhanced HEMT device, the connection relationship between the third protection circuit 5 and the driving chip, the transistor to be driven, the first protection circuit 1 and the second protection circuit 4 is as follows: Fig.14 shown.

[0095] In some embodiments, the third protection circuit 5 can be a normally-on JFET tube or a depletion-mode MOS tube, and the drain of the normally-on JFET tube or the depletion-mode MOS tube is connected to the driving end of the transistor 3 to be driven, and the source of the normally-on JFET tube or the depletion-mode MOS tube is connected to the source of the transistor 3 to be driven.

[0096] The present invention also provides a transistor control signal input electrode protection circuit, which is respectively connected to an enhanced GaN HEMT device, a driving circuit and a switch device; the switch device is a normally open JFET tube or a depletion MOS tube. The transistor control signal input electrode protection circuit includes: a first enhanced MOS tube, a second enhanced MOS tube and a diode. When the first enhanced MOS tube is an NMOS tube, the driving end and the drain of the first enhanced MOS tube are connected to the driving signal output end of the driving circuit after being connected to each other, the source of the first enhanced MOS tube is connected to the driving end of the enhanced GaN HEMT device, and the source of the first enhanced MOS tube is connected to the substrate of the channel region and is connected to the same potential; when the first enhanced MOS tube is a PMOS tube, the drain of the first enhanced MOS tube is connected to the driving signal output end, the source of the first enhanced MOS tube is connected to the driving end of the enhanced GaN HEMT device after being connected to each other, and the drain of the first enhanced MOS tube is connected to the substrate of the channel region and is connected to the same potential. The first enhancement MOS tube is used to share the charging voltage of the driving end capacitor of the enhancement GaN HEMT device when the driving voltage provided by the driving circuit makes the voltage of the driving end of the first enhancement MOS tube not reach the turn-on voltage of the driving end of the first enhancement MOS tube; when the driving voltage provided by the driving circuit makes the voltage of the driving end of the first enhancement MOS tube reach the turn-on voltage, the first enhancement MOS tube enters the on state, and controls the conduction of the enhancement GaN HEMT device according to the driving voltage in the on state; when the enhancement GaN HEMT device is turned on, when the driving voltage provided by the driving circuit makes the voltage of the driving end of the first enhancement MOS tube less than the turn-on voltage, the first enhancement MOS tube enters the off state, and controls the turn-off of the enhancement GaN HEMT device after entering the off state. The turn-on voltage of the driving end of the first enhancement MOS tube is greater than the threshold voltage of the enhancement GaN HEMT device. The driving electrode of the normally-on JFET tube or the depletion-type MOS tube is connected to the driving signal output terminal of the driving circuit, the drain of the normally-on JFET tube or the depletion-type MOS tube is connected to the driving terminal of the enhancement-type GaN HEMT device, and the source of the normally-on JFET tube or the depletion-type MOS tube is connected to the source of the enhancement-type GaN HEMT device. The normally-on JFET tube or the depletion-type MOS tube is used to provide a one-way free charge path between the driving electrode of the enhancement-type GaN HEMT device and the source of the enhancement-type GaN HEMT device when the driving voltage provided by the driving circuit makes the driving terminal voltage of the normally-on JFET tube or the depletion-type MOS tube not reach the turn-off voltage of the driving terminal of the normally-on JFET tube or the depletion-type MOS tube; when the driving voltage provided by the driving circuit reaches the turn-off voltage of the driving terminal of the normally-on JFET tube or the depletion-type MOS tube, the normally-on JFET tube or the depletion-type MOS tube enters the turn-off state.The turn-off voltage of the driving end of the normally-on JFET tube or the depletion-mode MOS tube is less than the turn-on voltage of the driving end of the first enhancement-mode MOS tube. When the second enhancement-mode MOS tube is an NMOS tube, the driving end and the drain of the second enhancement-mode MOS tube are connected to the driving end of the enhancement-mode GaN HEMT device after being connected to each other, and the source of the second enhancement-mode MOS tube is connected to one end of the driving circuit and the source of the enhancement-mode GaN HEMT device respectively, and the source of the second enhancement-mode MOS tube is connected to the substrate of the channel region and is connected to the same potential; when the second enhancement-mode MOS tube is a PMOS tube, the drain of the second enhancement-mode MOS tube is connected to the driving end of the enhancement-mode GaN HEMT device, and the source of the second enhancement-mode MOS tube is connected to the driving end of the second enhancement-mode MOS tube after being connected to one end of the driving circuit, and the drain of the second enhancement-mode MOS tube is connected to the substrate of the channel region and is connected to the same potential. The anode of the diode is connected to one end of the second enhancement-mode MOS tube, and the cathode of the diode is connected to one end of the driving circuit. Exemplarily, when the first enhancement-mode MOS transistor and the second enhancement-mode MOS transistor are both NMOS transistors and the driving circuit is a driving chip, the connection relationship between the first enhancement-mode MOS transistor, the second enhancement-mode MOS transistor, and the normally-on JFET transistor or the depletion-mode MOS transistor and the driving circuit and the enhancement-mode GaN HEMT device is as follows. Fig.15 shown.

[0097] The present invention also provides a control circuit including: a driving circuit, a plurality of transistor control signal input pole protection circuits, and a plurality of transistors to be driven corresponding to the plurality of transistor control signal input pole protection circuits. The plurality of transistors to be driven are connected in parallel, and the driving end of each transistor to be driven is connected to the driving signal output end of the driving circuit through the corresponding transistor control signal input pole protection circuit. When the driving signal provided by the driving circuit causes the first voltage of the first protection circuit in the plurality of transistor control signal input pole protection circuits to reach the first working voltage, the plurality of transistor control signal input pole protection circuits simultaneously enter the first conduction state, and after entering the first conduction state, each first protection circuit adjusts the driving current of the corresponding transistor to be driven according to the driving voltage and variable resistor provided by the driving circuit, so as to control the synchronous change of the driving end voltage of the plurality of transistors to be driven; the synchronous change of the driving end voltage of the plurality of transistors to be driven is used to control the simultaneous conduction or shut-down of the plurality of transistors to be driven. In the case where multiple transistors to be driven are turned on, when the driving voltage provided by the driving circuit makes the second voltage of the first protection circuit reach the second working voltage, multiple transistor control signal input terminal protection circuits simultaneously enter the first off state, and after entering the first off state, control multiple transistors to be driven to keep being turned off or turned on synchronously. For example, Fig.16As shown, the control circuit includes a driving circuit (ie, a driving chip), four transistor control signal input terminal protection circuits, and four transistors to be driven corresponding to the four transistor control signal input terminal protection circuits.

[0098] The transistor signal input pole protection circuit proposed in the present application establishes an adjustable isolation channel between the driving signal sent by the driving circuit and the driving end of the transistor to be driven. The channel allows the driving signal to reach the driving end of the transistor to be driven through the protection circuit only when certain conditions are met, which is equivalent to increasing the turn-on threshold voltage of the transistor to be driven, and can adapt to more driving chips; while the existing schemes currently require a dedicated driving chip to be designed separately for the HEMT transistor. The isolation channel provided by the protection circuit proposed in the present application also includes a capacitor or an equivalent capacitor connected in series with the driving end of the transistor to be driven. When the above isolation channel is not turned on, the series path between the above capacitor and the driving end of the transistor to be driven is the only path for charging the driving end capacitor of the transistor to be driven through the driving circuit, and the other paths are all discharge paths. If interference of the induction signal occurs, the above capacitor can share most of the interference voltage of the charging induction signal for the driving end capacitor of the transistor to be driven, thereby preventing the transistor to be driven from being turned on by mistake; while the existing schemes do not provide an isolation channel with circuit-breaking electrical isolation. The isolation channel provided by the transistor signal input pole protection circuit proposed in the present application also has the characteristic of adjustable resistance or equivalent resistance, that is, after the isolation channel is turned on, the resistance can be quickly reduced, so as to obtain a larger driving current and reduce the start-up time of the driving end of the transistor to be driven; further, the synchronous start-up capability can be improved when multiple transistors to be driven are connected in parallel; while the resistors or equivalent resistors connected in series before the driving end of the transistor to be driven in the existing scheme are all fixed resistance resistors. The isolation channel provided by the transistor signal input pole protection circuit proposed in the present application also includes a discharge path, which can provide a charge release channel for the driving end of the transistor to be driven. If the driving circuit has a negative voltage port, the residual charge of the driving end of the transistor to be driven can be fully released through the connection between the negative voltage port and the discharge path. At the same time, a short pulse negative voltage signal can be used to complete the extraction of the residual charge of the driving end of the transistor to be driven, and there is no need to provide negative voltage in all non-start signal cycles; while the existing scheme usually adopts the method of providing negative voltage in all non-start signal cycles to ensure that the transistor is in the off state. The transistor signal input electrode protection circuit proposed in the present application establishes an adjustable discharge channel between the driving end of the transistor to be driven and the source of the transistor to be driven. When certain conditions are met, the channel will be turned on to discharge the voltage of the driving end of the transistor to be driven, and the conduction condition can be flexibly designed to ensure that the driving end voltage of the transistor to be driven will not exceed the upper limit of the driving end voltage resistance; however, the existing scheme has limitations on the design of the clamping voltage. On the one hand, it cannot be flexibly adjusted, and on the other hand, the designable voltage values ​​are generally integer multiples of a certain base voltage value, so there is a lack of design flexibility.The discharge channel provided by the transistor signal input pole protection circuit proposed in the present application also includes a capacitor or equivalent capacitor connected in parallel with the capacitor (for example, gate-source capacitor) formed by the driving end and source of the transistor to be driven. When the above discharge channel is not turned on, the above capacitor can share the charge reaching the driving end of the transistor to be driven, and further protect the driving end of the transistor to be driven from being turned on by mistake; and the existing scheme does not provide parallel capacitor protection for the capacitor formed by the driving end and source of the transistor to be driven in the clamping circuit. The discharge channel provided by the transistor signal input pole protection circuit proposed in the present application also has the characteristics of adjustable resistance or equivalent resistance, that is, the resistance can be quickly reduced after the discharge channel is turned on, so as to obtain a larger discharge current, improve the response speed of the protection of the driving end of the transistor to be driven, and enhance the protection capability; and the resistance or equivalent resistance of the discharge path is fixed after the clamping voltage of the clamping circuit of the existing scheme is fixed, and usually the higher the clamping voltage design, the greater the resistance, that is, the worse the current discharge capability, which affects the response speed of the protection of the driving end of the transistor to be driven, and also weakens the protection capability. The conduction mechanism of the discharge channel provided by the transistor signal input electrode protection circuit proposed in the present application is the normal working conduction of the components, and the stability and reliability of repeated conduction are good; while in the existing schemes, the discharge channels provided by the clamping circuit or other circuit combinations will involve the reverse breakdown conduction of the diode, so the stability and reliability of repeated conduction will be limited.

[0099] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for protecting a transistor, characterized in that: Applicable to a transistor control signal input terminal protection circuit, the transistor control signal input terminal protection circuit is connected between a driving circuit and a transistor to be driven, and includes: When the driving voltage provided by the driving circuit makes the first voltage of the transistor control signal input terminal protection circuit not reach the first working voltage, sharing the charging voltage of the driving end capacitor of the transistor to be driven; When the driving voltage provided by the driving circuit makes the first voltage reach the first operating voltage, the first conducting state is entered, and the resistance is reduced after entering the first conducting state, and a driving current is provided to the transistor to be driven according to the driving voltage provided by the driving circuit and the reduced resistance, so as to control the conduction or shut-down of the transistor to be driven; In the case where the transistor to be driven is turned on, when the driving voltage provided by the driving circuit makes the second voltage of the transistor control signal input terminal protection circuit reach the second working voltage, the first off state is entered, and after entering the first off state, the transistor to be driven is controlled to be turned off or turned on; Among them, among the first working voltage and the second working voltage, one working voltage is a forward voltage, and the other working voltage is a reverse voltage.

2. The method for protecting a transistor according to claim 1, characterized in that: The step of controlling the transistor to be driven to be turned off or on after entering the first off state comprises: After entering the first off state, the second on state is entered, and the transistor to be driven is controlled to be off or on in the second on state.

3. The method for protecting a transistor according to claim 1, characterized in that: The method further comprises: After the transistor to be driven is turned on, when the driving voltage provided by the driving circuit makes the third voltage of the transistor control signal input terminal protection circuit reach the third operating voltage, it enters the third conduction state, and reduces the resistance in the third conduction state, and controls the driving end of the transistor to be driven to stop accumulating charges or release part of the accumulated charges according to the reduced resistance, so as to control the absolute value of the voltage at the driving end of the transistor to be driven to be smaller than the absolute value of the ultimate withstand voltage of the driving end of the transistor to be driven.

4. The method for protecting a transistor according to claim 1, characterized in that: The method further comprises: When the driving voltage provided by the driven circuit reaches a fourth operating voltage, the second off state is entered to cut off the free charge path between the driving end of the transistor to be driven and the source of the transistor to be driven; the absolute value of the fourth operating voltage is less than the absolute value of the first operating voltage.

5. A transistor control signal input terminal protection circuit, characterized in that: include: a first protection circuit; One end of the first protection circuit is connected to the driving signal output end of the driving circuit, and the other end of the first protection circuit is connected to the driving end of the transistor to be driven; The first protection circuit is used for sharing the charging voltage of the driving end capacitor of the transistor to be driven when the driving voltage provided by the driving circuit causes the first voltage of the first protection circuit to fail to reach the first working voltage; When the driving voltage provided by the driving circuit makes the first voltage reach the first working voltage, the first conducting state is entered, and in the first conducting state, the transistor to be driven is controlled to be turned on or off according to the driving voltage; In the case where the transistor to be driven is turned on, when the driving voltage provided by the driving circuit makes the second voltage of the first protection circuit reach the second working voltage, the first off state is entered, and after entering the first off state, the transistor to be driven is controlled to be turned off or turned on; Among them, the first operating voltage is greater than the threshold voltage of the transistor to be driven; among the first operating voltage and the second operating voltage, one operating voltage is a forward voltage, and the other operating voltage is a reverse voltage.

6. The transistor control signal input terminal protection circuit according to claim 5, characterized in that: The first protection circuit comprises: a first capacitor, a first circuit module and a first unidirectional conductive device; The first circuit module, the first unidirectional conductive device and the first capacitor are all connected in parallel, and the working current directions of the first circuit module and the first unidirectional conductive device are opposite; one end of the first circuit module, the first unidirectional conductive device and the first capacitor are all connected to the driving signal output end, and the other ends of the first circuit module, the first unidirectional conductive device and the first capacitor are all connected to the driving end of the transistor to be driven; When the voltage of the first capacitor does not reach the first working voltage, the first capacitor is used to share the charging voltage of the driving end capacitor of the transistor to be driven; When the voltage of the first capacitor reaches the first operating voltage, the first circuit module is turned on, and the first protection circuit enters a first on state; When the voltage of the first capacitor is less than the first operating voltage, the first circuit module is turned off, and the first protection circuit enters a first off state; When the reverse voltage of the first capacitor reaches the second operating voltage, the first unidirectional conductive device is turned on, and the first protection circuit enters a second conductive state.

7. The transistor control signal input terminal protection circuit according to claim 6, characterized in that: The first circuit module includes: a first variable resistor and a first conduction control switch connected in series; the first unidirectional conducting device includes: at least one diode or at least one transistor.

8. The transistor control signal input terminal protection circuit according to claim 5, characterized in that: The first protection circuit includes: a first MOS tube; one end of the first MOS tube is connected to the drive signal output end, and the other end of the first MOS tube is connected to the drive end of the transistor to be driven; the drive end start-up voltage of the first MOS tube is the first working voltage.

9. The transistor control signal input terminal protection circuit according to claim 8, characterized in that: When the transistor to be driven is a positive voltage driving device, and the first MOS transistor is an NMOS transistor, the driving end and the drain of the first MOS transistor are connected to each other and then connected to the driving signal output end, the source of the first MOS transistor is connected to the driving end of the transistor to be driven, and the source of the first MOS transistor is connected to the substrate of the channel region and is connected at the same potential; When the transistor to be driven is a positive voltage driving device and the first MOS transistor is a PMOS transistor, the drain of the first MOS transistor is connected to the driving signal output terminal, the source of the first MOS transistor is connected to the driving terminal and then connected to the driving terminal of the transistor to be driven, and the drain of the first MOS transistor is connected to the channel region substrate and is connected at the same potential; When the transistor to be driven is a negative voltage driving device and the first MOS transistor is an NMOS transistor, the source of the first MOS transistor is connected to the driving signal output terminal, the drain of the first MOS transistor is connected to the driving terminal and then connected to the driving terminal of the transistor to be driven, and the source of the first MOS transistor is connected to the channel region substrate and is connected at the same potential; When the transistor to be driven is a negative voltage driving device and the first MOS tube is a PMOS tube, the source and the driving end of the first MOS tube are connected to each other and then connected to the driving signal output end, the drain of the first MOS tube is connected to the driving end of the transistor to be driven, and the drain of the first MOS tube is connected to the channel region substrate and is connected at the same potential.

10. The transistor control signal input terminal protection circuit according to claim 5, characterized in that: The transistor control signal input terminal protection circuit also includes: A second protection circuit; one end of the second protection circuit is connected to the driving end of the transistor to be driven, and the other end of the second protection circuit is respectively connected to one end of the driving circuit and the other end of the transistor to be driven; The second protection circuit is used to enter a third conduction state after the transistor to be driven is turned on, when the driving voltage provided by the driving circuit makes the third voltage of the second protection circuit reach the third operating voltage, and in the third conduction state, control the driving end of the transistor to be driven to stop accumulating charges or release part of the accumulated charges, so as to control the absolute value of the voltage at the driving end of the transistor to be driven to be smaller than the absolute value of the maximum withstand voltage of the driving end of the transistor to be driven.

11. The transistor control signal input terminal protection circuit according to claim 10, characterized in that: The second protection circuit comprises: a second capacitor, a second circuit module and a second unidirectional conductive device; the second capacitor is connected in parallel with the second circuit module, and the second circuit module is connected in series with the second unidirectional conductive device; When the voltage across the second capacitor reaches the third operating voltage, the second circuit module and the second unidirectional conductive device are turned on, the second protection circuit enters a third conductive state, and the charge at the driving end of the transistor to be driven is released through the second circuit module and the second unidirectional conductive device.

12. The transistor control signal input terminal protection circuit according to claim 11, characterized in that: The second circuit module includes: a second variable resistor and a second conduction control switch connected in series; the second unidirectional conducting device includes: at least one diode or at least one transistor.

13. The transistor control signal input terminal protection circuit according to claim 10, characterized in that: The second protection circuit includes: a second MOS tube; When the transistor to be driven is a positive voltage driving device, and the second MOS transistor is an NMOS transistor, the driving end and the drain of the second MOS transistor are connected to each other and then connected to the driving end of the transistor to be driven, the source of the second MOS transistor is respectively connected to one end of the driving circuit and the source of the transistor to be driven, and the source of the second MOS transistor is connected to the substrate of the channel region and is connected at the same potential; When the transistor to be driven is a positive voltage driving device and the second MOS tube is a PMOS tube, the drain of the second MOS tube is connected to the driving end of the transistor to be driven, the source of the second MOS tube is connected to the driving end and then connected to one end of the driving circuit, and the drain of the second MOS tube is connected to the channel region substrate and is connected at the same potential; When the transistor to be driven is a negative voltage driving device, and the second MOS transistor is an NMOS transistor, the source of the second MOS transistor is connected to the driving end of the transistor to be driven, the drain of the second MOS transistor is connected to the driving end and then connected to one end of the driving circuit and the source of the transistor to be driven, respectively, and the source of the second MOS transistor is connected to the substrate of the channel region and is connected at the same potential; When the transistor to be driven is a negative voltage driving device and the second MOS tube is a PMOS tube, the source and the driving end of the second MOS tube are connected to each other and then connected to the driving end of the transistor to be driven, the drain of the second MOS tube is connected to one end of the driving circuit, and the drain of the second MOS tube is connected to the channel region substrate and is connected at the same potential.

14. The transistor control signal input terminal protection circuit according to claim 13, characterized in that: The second protection circuit further includes: a third unidirectional conductive device and a fourth unidirectional conductive device; the fourth unidirectional conductive device has a conduction direction opposite to that of the third unidirectional conductive device; The third unidirectional conducting device is used to prevent the current from charging the driving end capacitor of the transistor to be driven via the second MOS transistor when the second MOS transistor is turned on; The fourth unidirectional conducting device is connected in parallel with the second MOS tube.

15. The transistor control signal input terminal protection circuit according to claim 5, characterized in that: The transistor control signal input terminal protection circuit also includes: a third protection circuit; one end of the third protection circuit is connected to the driving end of the transistor to be driven, and the other end of the third protection circuit is respectively connected to one end of the driving circuit and the other end of the transistor to be driven; the third protection circuit provides a charge free path between the driving end and the source of the transistor to be driven; The third protection circuit is used to enter a second shutdown state to cut off the free path of charge between the driving end of the transistor to be driven and the source of the transistor to be driven when the driving voltage provided by the driving circuit makes the fourth voltage of the third protection circuit reach a fourth operating voltage; the absolute value of the fourth operating voltage is less than the absolute value of the first operating voltage.

16. The transistor control signal input terminal protection circuit according to claim 15, characterized in that: The third protection circuit comprises: a third capacitor, a third circuit module and a fifth unidirectional conductive device; the third capacitor is connected in parallel with the third circuit module, and the third circuit module is connected in series with the fifth unidirectional conductive device; When the voltage across the third capacitor does not reach the fourth operating voltage, the third circuit module and the fifth unidirectional conductive device are turned on, and the charge at the driving end of the transistor to be driven flows freely in one direction between the driving end of the transistor to be driven and the source of the transistor to be driven through the third circuit module and the fifth unidirectional conductive device. When the voltage across the third capacitor reaches and or exceeds the fourth operating voltage, the third protection circuit enters a second off state, and the charge at the driving end of the transistor to be driven cannot be released through the third circuit module and the third unidirectional conductive device.

17. A transistor control signal input terminal protection circuit, characterized in that: The device is connected to an enhanced GaN HEMT device, a driving circuit and a switch device respectively; the switch device is a normally-on JFET tube or a depletion-type MOS tube; the transistor control signal input electrode protection circuit includes: a first enhanced MOS tube, a second enhanced MOS tube and a diode; When the first enhancement-mode MOS transistor is an NMOS transistor, the driving end and the drain of the first enhancement-mode MOS transistor are connected to each other and then connected to the driving signal output end of the driving circuit, the source of the first enhancement-mode MOS transistor is connected to the driving end of the enhancement-mode GaN HEMT device, and the source of the first enhancement-mode MOS transistor is connected to the substrate of the channel region and is connected at the same potential; when the first enhancement-mode MOS transistor is a PMOS transistor, the drain of the first enhancement-mode MOS transistor is connected to the driving signal output end, the source of the first enhancement-mode MOS transistor and the driving end are connected to each other and then connected to the driving end of the enhancement-mode GaN HEMT device, and the drain of the first enhancement-mode MOS transistor is connected to the substrate of the channel region and is connected at the same potential; The first enhancement mode MOS transistor is used to share the charging voltage of the driving end capacitor of the enhancement mode GaN HEMT device when the driving voltage provided by the driving circuit makes the voltage of the driving end of the first enhancement mode MOS transistor fail to reach the turn-on voltage of the driving end of the first enhancement mode MOS transistor; when the driving voltage provided by the driving circuit makes the voltage of the driving end of the first enhancement mode MOS transistor reach the turn-on voltage, the first enhancement mode MOS transistor enters the on state, and controls the conduction of the enhancement mode GaN HEMT device according to the driving voltage in the on state; when the enhancement mode GaN HEMT device is turned on, when the driving voltage provided by the driving circuit makes the voltage of the driving end of the first enhancement mode MOS transistor less than the turn-on voltage, the first enhancement mode MOS transistor enters the off state, and controls the turn-off of the enhancement mode GaN HEMT device after entering the off state; Wherein, the turn-on voltage of the driving end of the first enhancement mode MOS tube is greater than the threshold voltage of the enhancement mode GaN HEMT device; The driving electrode of the normally-on JFET tube or the depletion-mode MOS tube is connected to the driving signal output terminal of the driving circuit, the drain of the normally-on JFET tube or the depletion-mode MOS tube is connected to the driving end of the enhancement-mode GaN HEMT device, and the source of the normally-on JFET tube or the depletion-mode MOS tube is connected to the source of the enhancement-mode GaN HEMT device; The normally-on JFET tube or the depletion-mode MOS tube is used to provide a one-way free charge path between the driving end of the enhancement-mode GaN HEMT device and the source of the enhancement-mode GaN HEMT device when the driving voltage provided by the driving circuit makes the driving end voltage of the normally-on JFET tube or the depletion-mode MOS tube not reach the turn-off voltage of the driving end of the normally-on JFET tube or the depletion-mode MOS tube; when the driving voltage provided by the driving circuit reaches the turn-off voltage of the driving end of the normally-on JFET tube or the depletion-mode MOS tube, the normally-on JFET tube or the depletion-mode MOS tube enters the turn-off state; Wherein, the turn-off voltage of the driving end of the normally-on JFET tube or the depletion-mode MOS tube is less than the turn-on voltage of the driving end of the first enhancement-mode MOS tube; When the second enhancement-mode MOS transistor is an NMOS transistor, the driving end and the drain of the second enhancement-mode MOS transistor are connected to each other and then connected to the driving end of the enhancement-mode GaN HEMT device, the source of the second enhancement-mode MOS transistor is connected to one end of the driving circuit and the source of the enhancement-mode GaN HEMT device respectively, and the source of the second enhancement-mode MOS transistor is connected to the substrate of the channel region and is connected at the same potential; when the second enhancement-mode MOS transistor is a PMOS transistor, the drain of the second enhancement-mode MOS transistor is connected to the driving end of the enhancement-mode GaN HEMT device, the source of the second enhancement-mode MOS transistor is connected to the driving end and then connected to one end of the driving circuit, and the drain of the second enhancement-mode MOS transistor is connected to the substrate of the channel region and is connected at the same potential; The anode of the diode is connected to one end of the second enhancement mode MOS transistor, and the cathode of the diode is connected to one end of the driving circuit.

18. A control circuit, characterized in that: include: A driving circuit, a plurality of transistor control signal input terminal protection circuits as described in any one of claims 5 to 17, and a plurality of transistors to be driven corresponding to the plurality of transistor control signal input terminal protection circuits one by one; A plurality of transistors to be driven are connected in parallel, and a driving end of each transistor to be driven is connected to a driving signal output end of the driving circuit through a corresponding transistor control signal input terminal protection circuit; When the driving signal provided by the driving circuit causes the plurality of transistor control signal input terminal protection circuits to enter, and the first voltage of the first protection circuit reaches the first working voltage, the plurality of transistor control signal input terminal protection circuits simultaneously enter the first conduction state, and after entering the first conduction state, each of the first protection circuits adjusts the driving current of the corresponding transistor to be driven according to the driving voltage and the variable resistor provided by the driving circuit, so as to control the synchronous change of the driving terminal voltages of the plurality of transistors to be driven; The synchronous change of the driving terminal voltages of the plurality of transistors to be driven is used to control the simultaneous turning on or off of the plurality of transistors to be driven; In the case that multiple transistors to be driven are turned on, when the driving voltage provided by the driving circuit makes the second voltage of the first protection circuit reach the second operating voltage, multiple transistor control signal input terminal protection circuits simultaneously enter the first off-state, and after entering the first off-state, control the multiple transistors to be driven to maintain synchronous off or on.

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