High-precision time synchronization system and method based on processor, and electronic equipment

Abstract

A high-precision time synchronization system and method based on a processor, and an electronic device, the synchronization system comprises an active antenna access module, a dual-mode positioning module and a processor, the active antenna access module is used for receiving satellite signals and taking the received satellite signals as system input, and the dual-mode positioning module is used for receiving the satellite signals and taking the received satellite signals as system input. The dual-mode positioning module is connected to the active antenna access module and the processor so as to receive the synchronization time sent by the active antenna access module, receive a signal sent by the processor and send the signal to the processor, and the processor is connected to the dual-mode positioning module and internally comprises a clock synchronization processing module; the system is used for realizing time synchronization, processing pulse per second signals and analyzing information sent by the dual-mode positioning module. According to the invention, the high-resolution HRTIM timer is combined with the pulse signal generated by the PPS, so that the time alignment process is optimized, and nanosecond-level time synchronization is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of time synchronization, and in particular to a processor-based high-precision time synchronization system and method, and electronic equipment. Background Art

[0002] The necessity of high-precision time synchronization in the fields of synchronous acquisition, reconnaissance and positioning, and vehicle-mounted communications is becoming increasingly prominent. With the popularization of various intelligent systems and automation technologies, accurate time synchronization has become a key factor in ensuring system reliability, efficiency, and data consistency.

[0003] In some areas where time accuracy is high, such as the widespread distribution of power grid equipment, monitoring data often comes from different locations. High-precision time synchronization can ensure that the data from each monitoring point is consistent in time sequence, and the fault source can be quickly and accurately located. This is particularly important for improving the response speed of power system faults and optimizing power grid restoration strategies. Reconnaissance and positioning systems, especially in public safety and geographic information system (GIS) applications, rely on the collaborative work of multiple sensors and monitoring devices. Time synchronization can ensure that data between different devices are accurately aligned in time, thereby improving positioning accuracy, the effectiveness of data fusion, and providing accurate time series data for subsequent investigations of events. In the field of vehicle-to-everything (V2X), autonomous driving and intelligent transportation systems rely on real-time data exchange and precise positioning. The collaborative work of vehicles, roadside facilities and cloud platforms requires that the sensor data of all parties be highly synchronized to avoid traffic accidents or reduced efficiency caused by delays. High-precision time synchronization ensures the accuracy and safety of these systems in high-frequency real-time decision-making.

[0004] High-precision, low-latency time synchronization technology has become one of the key requirements in the above fields. Although the existing PPS (pulse per second signal) and TOD (time and date information)-based time synchronization technology has been widely used in power, positioning, communication and other fields, it still faces technical challenges in actual scenarios with high precision requirements.

[0005] At present, high-precision time synchronization solutions mainly rely on satellite signal sources such as external GPS modules to achieve time synchronization between nodes by receiving PPS and TOD signals. The following are several common existing technical solutions: First, a solution based on FPGA to receive PPS pulses and maintain time synchronization: FPGA is used to receive PPS second pulse signals, and the internal high-precision timer is reset when each PPS pulse arrives to generate a synchronization timestamp to achieve high-precision time synchronization. Due to the high power consumption characteristics of FPGA, the battery output is required to have a higher power, which limits its use in application scenarios with strict requirements on power consumption, such as portable or remote devices. In addition, high power consumption will also cause the device to overheat, requiring additional heat dissipation measures, which not only increases the cost, but also increases the complexity of the system.

[0006] Second, the time synchronization solution based on PPS and TOD: The traditional distributed fault detection system receives satellite signals through an external GPS module, uses the PPS signal as the second-level time reference, and obtains specific timestamp data through the TOD information transmitted through the serial port. This solution uses the PPS pulse to synchronize the timer inside the processor to maintain the consistency of the second-level time. However, this method does not perform alignment processing at the microsecond or even nanosecond level of accuracy, and it is difficult to meet the needs of high-precision power fault detection. Summary of the invention

[0007] The present invention provides a processor-based high-precision time synchronization system and method, and electronic equipment to address the deficiencies of the above-mentioned prior art. By accessing an external GPS signal source and combining a high-resolution timer (HRTIM) inside the processor, high-precision alignment of PPS signal capture and second-level time reference is achieved. The system updates the second-level time in real time in the interrupt response, and uses counting accuracy to achieve nanosecond-level synchronization requirements, providing a stable, low-latency time reference for the application system.

[0008] In order to achieve the purpose of the present invention, the following technologies are proposed: First, a processor-based high-precision time synchronization system is provided, including an active antenna access module, a dual-mode positioning module and a processor; An active antenna access module is used to receive satellite signals and use the received satellite signals as system input; The dual-mode positioning module is connected to the active antenna access module and the processor to receive the synchronization time signal sent by the active antenna access module, receive the signal sent by the processor and send a signal to the processor; The processor is connected to the dual-mode positioning module, which contains a clock synchronization processing module for realizing time synchronization, processing second pulse signals and analyzing the information sent by the dual-mode positioning module.

[0009] Furthermore, the dual-mode positioning module has RF_IN, 1PPS, RXD, TXD, ANT_PWR, and VCC_RF pins; The RF_IN pin is connected to the signal output terminal of the active antenna access module to receive the synchronization time signal; 1PPS pin is connected to the clock synchronization processing module of the processor and is used to receive the PPS pulse signal once per second; The RXD and TXD pins are connected to the processor's transmit and receive serial ports respectively; VCC_RF is connected to the ANT_PWR pin to provide antenna power.

[0010] Furthermore, the clock synchronization processing module has an HRTIM timer, an NVIC interrupt controller, a pulse interrupt processing unit, a TOD analysis module, a cross-second maintenance unit and an external timing acquisition interface; The HRTIM timer is connected to the 1PPS pin of the dual-mode positioning module and is used to achieve time synchronization through the NVIC interrupt controller; The pulse interrupt processing unit is connected to the 1PPS pin of the dual-mode positioning module and is used to process the pulse signal of PPS once per second; The TOD analysis module is connected to the RXD and TXD pins of the dual-mode positioning module to analyze the second-level time sent by the dual-mode positioning module; A cross-second maintenance unit to align time; The external timing acquisition interface is connected to the RXD and TXD pins of the dual-mode positioning module and is used to provide external devices with access time information.

[0011] Second, a processor-based high-precision time synchronization method is provided, using a processor-based high-precision time synchronization system, including the steps of: Step 1, initialize the HRTIM timer in the clock synchronization processing module to extract the nanosecond part of the time, And set the NVIC interrupt controller to use the HRTIM timer as the interrupt source, set the interrupt priority, and enable the interrupt; Step 2: The dual-mode positioning module generates a pulse-per-second signal output through the 1PPS pin every 1 second. The rising edge of the pulse-per-second signal triggers the NVIC interrupt controller and generates an external interrupt. At this time, the 1PPS pin in the dual-mode positioning module is characterized by a high level. Step 3: Determine whether to reset the counter based on the 1PPS pin level status in the dual-mode positioning module: If the 1PPS pin level is at a low level, proceed to step 2 to wait for the pulse per second signal generated by the 1PPS pin to be at a rising edge to trigger the NVIC interrupt controller; If the 1PPS pin level state is high, proceed to step 4; Step 4, resetting the HRTIM timer in the clock synchronization processing module so that the HRTIM timer is aligned with the pulse per second signal generated every 1 second by the 1PPS pin in step 2; Set the value of the count buffer CNT in the HRTIM timer to 0; Step 5: After the HRTIM timer is reset, wait for the TXD pin to trigger the NVIC interrupt controller. The TOD parsing module extracts the second-level time of the message sent by the TXD pin on the dual-mode positioning module, and caches the extracted second-level time in the processor, and records the second-level time cached in the processing as the second-level time of the previous cycle. The clock synchronization processing module obtains the second-level time of the previous cycle, and sets the second-level time of the previous cycle as the second-level partial time; Step 6, after setting the second-level time of the upper cycle to the second-level part time, the dual-mode positioning module sends NMEA format data containing time to the processor through the TXD pin on it, and provides the UTC second-level time to the clock synchronization processing module in a TOD format message; Step 7, the TOD parsing module in the clock synchronization processing module parses the TOD format message provided in step 6 and extracts the UTC time; Step 8: Determine whether the UTC time extracted in step 7 is the first time for time synchronization: If the UTC time extracted in step 7 is the first time for time synchronization, the extracted UTC time is set to a fractional time in seconds, the processor caches the extracted UTC time, and the extracted UTC time cached in the processor is recorded as the current cycle time, and the current cycle time is set to a fractional time in seconds; If the currently extracted UTC time is not the first time for time synchronization, the extracted UTC time is cached in the processor as the second-level time of the previous cycle in step 5, and the second-level time of the previous cycle is set as the second-level partial time; Step 9, when the value of the count buffer CNT in the HRTIM timer is set to 0, the count buffer CNT in the HRTM timer performs an accumulation operation, extracts the nanosecond part of time within the counting cycle, and updates the nanosecond part of time according to the counting cycle; Step 10, when the external device needs a timing operation, the second-level partial time obtained in step 8 and the nanosecond-level partial time obtained in step 9 are aligned with the second-level partial time corresponding to the period in which the nanosecond-level partial time is located; Step 11, when the external device performs timing operation, the second-level partial time obtained in step 8 and the nanosecond-level partial time in step 9 are combined, and the combined time information is returned to the external device.

[0012] Furthermore, the setting parameters of the HRTIM timer in the clock synchronization processing module are: Continuous working mode; The frequency division is set to 1; The interrupt frequency is configured to 6.1kHz; Set the period of the HRTIM timer to 2.5 nanoseconds; Set 3+1 cycles to trigger the scheduled task every 10 nanoseconds.

[0013] Further, in step 10, the method of adding 1 second is adopted to align the nanosecond partial time with the second-level partial time corresponding to the cycle in which it is located. The cross-second maintenance unit introduces a cache mechanism to cache the second-level time delay to the next cycle, that is, each time the second-level partial time and the nanosecond-level partial time correspond, the cached second-level partial time of the last 1 second is always extracted. And when the external device is operating at the time service, the entire system is in a stable state, that is, the 1PPS pin in the model positioning module generates multiple rounds of second pulse signal output at this time. Therefore, when the external device is operating at the time service, it is always in the method of adding 1 second to align the nanosecond partial time with the second-level partial time corresponding to the cycle in which it is located. In this way, the continuity of time information in the cross-second scenario and the seamless connection of the alignment operation can be ensured. When performing synchronization, the difference between the cache of the second-level time and the real-time time is calculated, and the time information alignment is completed by adding seconds.

[0014] Furthermore, in step 9, the count buffer CNT in the HRTIM timer takes 10 nanoseconds as a count cycle.

[0015] Furthermore, the time information returned to the external device in step 11 is in nanosecond level.

[0016] First, an electronic device is provided, comprising at least a processor and a memory; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory, so that the processor executes a processor-based high-precision time synchronization method.

[0017] The advantages of the above technical solution are: The present invention adopts a high-resolution HRTIM timer in combination with a pulse signal generated by a PPS, optimizes the time alignment process, and realizes nanosecond-level time synchronization.

[0018] The present invention adopts the high-resolution HRTIM timer built in the processor without the need for additional high-cost hardware support, thereby significantly reducing the cost and power consumption of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings.

[0020] Figure 1 A framework diagram of a processor-based high-precision time synchronization system is shown.

[0021] Figure 2A flowchart of a processor-based high-precision time synchronization method is shown. DETAILED DESCRIPTION

[0022] Example 1 like Figure 1 As shown, a processor-based high-precision time synchronization system includes an active antenna access module, a dual-mode positioning module and a processor. The active antenna access module is used to receive satellite signals and use the received satellite signals as system input. The dual-mode positioning module is connected to the active antenna access module and the processor to receive the synchronization time signal sent by the active antenna access module, receive the signal sent by the processor and send a signal to the processor. The processor is connected to the dual-mode positioning module, which contains a clock synchronization processing module for realizing time synchronization, processing second pulse signals and parsing the information sent by the dual-mode positioning module.

[0023] The dual-mode positioning module has RF_IN, 1PPS, RXD, TXD, ANT_PWR, and VCC_RF pins.

[0024] The RF_IN pin is connected to the signal output terminal of the active antenna access module to receive the synchronization time signal. The 1PPS pin is connected to the clock synchronization processing module of the processor to receive the PPS pulse signal once per second. The RXD and TXD pins are connected to the processor's transmit and receive serial ports respectively. VCC_RF is connected to the ANT_PWR pin to provide antenna power.

[0025] The clock synchronization processing module has an HRTIM timer, an NVIC interrupt controller, a pulse interrupt processing unit, a TOD parsing module, a cross-second maintenance unit and an external timing acquisition interface. The HRTIM timer is connected to the 1PPS pin of the dual-mode positioning module and is used to achieve time synchronization through the NVIC interrupt controller. The pulse interrupt processing unit is connected to the 1PPS pin of the dual-mode positioning module and is used to process the pulse signal of PPS once per second. The TOD parsing module is connected to the RXD and TXD pins of the dual-mode positioning module to parse the second-level time sent by the dual-mode positioning module. The cross-second maintenance unit is used to align the time. The external timing acquisition interface is connected to the RXD and TXD pins of the dual-mode positioning module and is used to provide external devices with access time information.

[0026] Example 2 A processor-based high-precision time synchronization method, using a processor-based high-precision time synchronization system, includes the following steps: Step 1: Initialize the HRTIM timer in the clock synchronization processing module to extract the nanosecond part of time, and set the NVIC interrupt controller to use the HRTIM timer as the interrupt source, set the interrupt priority, and enable the interrupt.

[0027] Among them, the setting parameters of the HRTIM timer in the clock synchronization processing module are: continuous working mode, frequency division set to 1, interrupt frequency configured to 6.1kHz, the period of the HRTIM timer is 2.5 nanoseconds, and 3+1 periods are set to trigger a timing task every 10 nanoseconds.

[0028] Step 2: The dual-mode positioning module generates a pulse-per-second signal output through the 1PPS pin every second. The rising edge of the pulse-per-second signal triggers the NVIC interrupt controller and generates an external interrupt. At this time, the 1PPS pin in the dual-mode positioning module is characterized by a high level.

[0029] Step 3: Determine whether to reset the counter based on the 1PPS pin level status in the dual-mode positioning module: If the 1PPS pin level is low, proceed to step 2 to wait for the pulse per second signal generated by the 1PPS pin to be at a rising edge to trigger the NVIC interrupt controller. If the 1PPS pin level is high, proceed to step 4.

[0030] Step 4: reset the HRTIM timer in the clock synchronization processing module to align the HRTIM timer with the second pulse signal generated every 1 second by the 1PPS pin in step 2. Set the value of the count buffer CNT in the HRTIM timer to 0.

[0031] Step 5. After the HRTIM timer is reset, wait for the TXD pin to trigger the NVIC interrupt controller. The TOD parsing module extracts the second-level time from the message sent by the TXD pin on the dual-mode positioning module, and caches the extracted second-level time in the processor. The second-level time cached in the processing is recorded as the second-level time of the previous cycle. The clock synchronization processing module obtains the second-level time of the previous cycle and sets the second-level time of the previous cycle to the second-level part time.

[0032] Step 6, after setting the second-level time of the upper cycle to the second-level part time, the dual-mode positioning module sends NMEA format data containing time to the processor through its TXD pin, and provides UTC second-level time to the clock synchronization processing module in a TOD format message.

[0033] Step 7: The TOD parsing module in the clock synchronization processing module parses the TOD format message provided in step 6 and extracts the UTC time.

[0034] Step 8: Determine whether the UTC time extracted in step 7 is the first time for time synchronization: If the UTC time extracted in step 7 is the first time for time synchronization, the extracted UTC time is set to the partial time in seconds, the processor caches the extracted UTC time, and records the extracted UTC time cached in the processor as the current cycle time, and sets the current cycle time to the partial time in seconds.

[0035] If the currently extracted UTC time is not the first time for time synchronization, the extracted UTC time is cached in the processor as the previous cycle second time in step 5, and the previous cycle second time is set as the second partial time.

[0036] Step 9: When the value of the count buffer CNT in the HRTIM timer is set to 0, the count buffer CNT in the HRTM timer performs an accumulation operation, extracts the nanosecond part of time within the counting cycle, and updates the nanosecond part of time according to the counting cycle. The count buffer CNT in the HRTIM timer takes 10 nanoseconds as a counting cycle.

[0037] Step 10, when the external device needs to operate the timing service, the second-level partial time obtained in step 8 and the nanosecond-level partial time obtained in step 9 are aligned with the second-level partial time corresponding to the cycle in which the nanosecond-level partial time is located. In step 10, the method of adding 1 second is adopted to align the nanosecond-level partial time with the second-level partial time corresponding to the cycle in which it is located. The cross-second maintenance unit introduces a cache mechanism to cache the second-level time delay to the next cycle, that is, each time the second-level partial time and the nanosecond-level partial time correspond, the cached second-level partial time of the last 1 second is always extracted. And when the external device operates the timing service, the entire system is in a stable state, that is, at this time, the 1PPS pin in the model positioning module generates multiple rounds of second pulse signal output. Therefore, when the external device operates the timing service, it is always in the method of adding 1 second to align the nanosecond-level partial time with the second-level partial time corresponding to the cycle in which it is located. In this way, the continuity of time information in the cross-second scenario and the seamless connection of the alignment operation can be ensured. When performing synchronization, the difference between the cache of the second-level time and the real-time time is calculated, and the time information alignment is completed by adding seconds.

[0038] Step 11, when the external device performs timing operation, the second-level partial time obtained in step 8 and the nanosecond-level partial time in step 9 are combined, and the combined nanosecond-level time information is returned to the external device.

[0039] Example 3 An electronic device comprises at least a processor and a memory; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory, so that the processor executes a high-precision time synchronization method based on the processor.

[0040] The processor-based high-precision time synchronization system mentioned in Embodiment 1 is described below by taking a specific application example.

[0041] In the power system, it is necessary to monitor the occurrence of transmission line faults, and the equipment is required to provide nanosecond-level timestamps to support real-time data transmission. The processor-based high-precision time synchronization system and method proposed above, with the help of the clock synchronization processing module in the processor, the second pulse generated by the 1PPS pin in the dual-mode positioning module, TOD timestamp information, and high-resolution HRTIM timer, ensures high-precision time synchronization, as follows: (1) System assembly and antenna access Before the device is connected to the network, install the active antenna and place it in a location with good signal reception. The active antenna needs to be connected to the RF_IN pin of the dual-mode positioning module to ensure that satellite signals can be continuously received to provide a basis for time synchronization.

[0042] (2) Connection and initialization of each module of the device In this application example, the 1PPS pin of the dual-mode positioning module is connected to the HRTIM timer input of the processor, and the RXD and TXD pins are connected to the transmit and receive serial ports of the processor respectively, which are used to transmit time information in NMEA format. The VCC_RF pin is connected to the ANT_PWR port to power the antenna module.

[0043] The processor initializes the HRTIM timer, sets it to continuous working mode, divides it by 1, configures the interrupt frequency to 6.1kHz, and configures the period to 2.5 nanoseconds to achieve 10 nanosecond high-resolution timing, sets the NVIC interrupt priority, and ensures that when the 1PPS pin triggers an external interrupt, it can be processed in time.

[0044] (3) Data communication and 1PPS pulse information triggering The RXD and TXD pins in the dual-mode positioning module begin to send NMEA format data to the processor through the serial port interface of the processor at a cycle of one second, and the data contains TOD information accurate to the second.

[0045] The 1PPS pin in the dual-mode positioning module generates a pulse signal every second, triggering the interrupt handler in the processor. The processor uses this interrupt to capture the rising edge of the pulse signal every second to align the internal high-resolution HRTIM timer.

[0046] (4) Second-level time alignment and caching When the 1PPS signal in the dual-mode positioning module triggers the NVIC interrupt controller, the processor's HRTIM timer is reset and starts counting from zero to ensure that the pulse signal generated by 1PPS is strictly synchronized with the count buffer of the HRTIM timer.

[0047] After the pulse signal generated by PPS is triggered: If there is a second-level TOD second-level format message in the cache, the system will temporarily store the TOD format message and record it as the trigger time of the current 1PPS pulse signal, and the trigger time will be used for the next trigger cycle.

[0048] If the cache is empty, the system stores the TOD second-level format message received this time into the cache to ensure time alignment after the span seconds.

[0049] The cache and cross-second maintenance unit (which is used to align time, that is, align the nanosecond part of time with the second part of time corresponding to its cycle) effectively reduce the instantaneous error in data transmission and avoid time misalignment.

[0050] (5) High-precision nanosecond time generation During the operation of the equipment, nanosecond time recording is achieved by reading the count value of the HRTIM timer and combining it with the second-level TOD format message. This process is very important for the precise synchronization of the fault waveform. Through the 2.5 nanosecond cycle and 100 nanosecond trigger accuracy of the HRTIM timer, the system can achieve precise calibration of the fault occurrence time, which helps to quickly determine the fault type and location.

[0051] (6) Time-aligned output When a power grid fault occurs and triggers the monitoring device, the system will first call the second-level TOD format message and the count value of the high-resolution HRTIM timer in the cache to generate a complete ns-level timestamp. The monitoring device uses this high-precision timestamp to record the occurrence time of the fault event as the starting time of this traveling wave fault data, which is used for subsequent modules to locate the fault and perform synchronous analysis.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A processor-based high-precision time synchronization system, characterized in that: Including active antenna access module, dual-mode positioning module and processor; An active antenna access module is used to receive satellite signals and use the received satellite signals as system input; The dual-mode positioning module is connected to the active antenna access module and the processor to receive the synchronization time signal sent by the active antenna access module, receive the signal sent by the processor and send a signal to the processor; The processor is connected to the dual-mode positioning module, which contains a clock synchronization processing module for realizing time synchronization, processing second pulse signals and analyzing the information sent by the dual-mode positioning module.

2. The processor-based high-precision time synchronization system according to claim 1, characterized in that: The dual-mode positioning module has RF_IN, 1PPS, RXD, TXD, ANT_PWR, and VCC_RF pins; The RF_IN pin is connected to the signal output terminal of the active antenna access module to receive the synchronization time signal; 1PPS pin is connected to the clock synchronization processing module of the processor and is used to receive the PPS pulse signal once per second; The RXD and TXD pins are connected to the processor's transmit and receive serial ports respectively; VCC_RF is connected to the ANT_PWR pin to provide antenna power.

3. The processor-based high-precision time synchronization system according to claim 1, characterized in that: The clock synchronization processing module has an HRTIM timer, an NVIC interrupt controller, a pulse interrupt processing unit, a TOD analysis module, a cross-second maintenance unit, and an external timing acquisition interface; The HRTIM timer is connected to the 1PPS pin of the dual-mode positioning module and is used to achieve time synchronization through the NVIC interrupt controller; The pulse interrupt processing unit is connected to the 1PPS pin of the dual-mode positioning module and is used to process the pulse signal of PPS once per second; The TOD analysis module is connected to the RXD and TXD pins of the dual-mode positioning module to analyze the second-level time sent by the dual-mode positioning module; A cross-second maintenance unit to align time; The external timing acquisition interface is connected to the RXD and TXD pins of the dual-mode positioning module and is used to provide external devices with access time information.

4. A high-precision time synchronization method based on a processor, characterized in that: A processor-based high-precision time synchronization system as claimed in any one of claims 1 to 3, comprising the steps of: Step 1, initialize the HRTIM timer in the clock synchronization processing module to extract the nanosecond part of the time, And set the NVIC interrupt controller to use the HRTIM timer as the interrupt source, set the interrupt priority, and enable the interrupt; Step 2: The dual-mode positioning module generates a pulse-per-second signal output through the 1PPS pin every 1 second. The rising edge of the pulse-per-second signal triggers the NVIC interrupt controller and generates an external interrupt. At this time, the 1PPS pin in the dual-mode positioning module is characterized by a high level. Step 3: Determine whether to reset the counter based on the 1PPS pin level status in the dual-mode positioning module: If the 1PPS pin level is at a low level, proceed to step 2 to wait for the pulse per second signal generated by the 1PPS pin to be at a rising edge to trigger the NVIC interrupt controller; If the 1PPS pin level state is high, proceed to step 4; Step 4, resetting the HRTIM timer in the clock synchronization processing module so that the HRTIM timer is aligned with the pulse per second signal generated every 1 second by the 1PPS pin in step 2; Set the value of the count buffer CNT in the HRTIM timer to 0; Step 5: After the HRTIM timer is reset, wait for the TXD pin to trigger the NVIC interrupt controller, and the TOD parsing module extracts the second-level time of the message sent by the TXD pin on the dual-mode positioning module, and caches the extracted second-level time in the processor, and records the second-level time cached in the processing as the second-level time of the previous cycle; The clock synchronization processing module obtains the second-level time of the previous cycle, and sets the second-level time of the previous cycle as the second-level partial time; Step 6, after setting the second-level time of the upper cycle to the second-level part time, the dual-mode positioning module sends NMEA format data containing time to the processor through the TXD pin on it, and provides the UTC second-level time to the clock synchronization processing module in a TOD format message; Step 7, the TOD parsing module in the clock synchronization processing module parses the TOD format message provided in step 6 and extracts the UTC time; Step 8: Determine whether the UTC time extracted in step 7 is the first time for time synchronization: If the UTC time extracted in step 7 is the first time for time synchronization, the extracted UTC time is set to a fractional time in seconds, the processor caches the extracted UTC time, and the extracted UTC time cached in the processor is recorded as the current cycle time, and the current cycle time is set to a fractional time in seconds; If the currently extracted UTC time is not the first time for time synchronization, the extracted UTC time is cached in the processor as the second-level time of the previous cycle in step 5, and the second-level time of the previous cycle is set as the second-level partial time; Step 9, when the value of the count buffer CNT in the HRTIM timer is set to 0, the count buffer CNT in the HRTM timer performs an accumulation operation, extracts the nanosecond part of time within the counting cycle, and updates the nanosecond part of time according to the counting cycle; Step 10, when the external device needs a timing operation, the second-level partial time obtained in step 8 and the nanosecond-level partial time obtained in step 9 are aligned with the second-level partial time corresponding to the period in which the nanosecond-level partial time is located; Step 11, when the external device performs timing operation, the second-level partial time obtained in step 8 and the nanosecond-level partial time in step 9 are combined, and the combined time information is returned to the external device.

5. The processor-based high-precision time synchronization method according to claim 4, characterized in that: The setting parameters of the HRTIM timer in the clock synchronization processing module are: Continuous working mode; The frequency division is set to 1; The interrupt frequency is configured to 6.1kHz; Set the period of the HRTIM timer to 2.5 nanoseconds; Set 3+1 cycles to trigger the scheduled task every 10 nanoseconds.

6. The processor-based high-precision time synchronization method according to claim 4, characterized in that: In step 10, the method of adding 1 second is adopted to align the nanosecond part of time with the second part of time corresponding to its cycle.

7. The processor-based high-precision time synchronization method according to claim 4, characterized in that: In step 9, the count buffer CNT in the HRTIM timer takes 10 nanoseconds as a count cycle.

8. The processor-based high-precision time synchronization method according to claim 4, characterized in that: The time information returned to the external device in step 11 is in nanosecond level.

9. An electronic device comprising at least one processor and a memory; the memory is used to store a computer program; characterized in that: The processor is used to execute the computer program stored in the memory, so that the processor executes the processor-based high-precision time synchronization method as described in any one of claims 4 to 8.

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