FPGA-based data plane state programmable system and switch

Abstract

The invention provides an FPGA (Field Programmable Gate Array)-based data plane state programmable system and a switch. The FPGA-based data plane state programmable system comprises a multi-stage matching action table assembly line, the assembly line comprises a plurality of ordered matching action table modules which are used for realizing different data plane processing and forwarding algorithms according to read configuration instructions in combination with a flow state matching table and a condition branch matching table; the matching action table module comprises a key value extraction module used for forming a to-be-matched key value; the stream state query module is used for obtaining stream address information through matching of the key value to be matched and reading corresponding stream state information; the packet header vector transmitting queue is used for dynamically scheduling packet header vector out-of-order transmission according to a flow state address and a dependency relationship by taking the flow state address in the flow state information as an identifier; the action module is used for determining a data plane processing and forwarding algorithm for processing according to the configuration instruction and updating flow state information and table state information; and the packet header vector reordering cache module is used for storing the packet header vectors which are executed completely and submitting the out-of-order packet header vectors in sequence.

Description

Technical Field

[0001] The present invention is applied to the field of FPGA and network data packet processing, and in particular to an FPGA-based data plane state programmable system and switch. The data plane state is programmable based on FPGA hardware, supporting the deployment of user-defined packet processing algorithms on the data plane, and the state query time is constant. Background Art

[0002] With the rapid development of the Internet, the traffic volume in the network is growing exponentially, which poses a great challenge to the performance of switching equipment. The current switching equipment architecture is mainly divided into three categories: architecture based on dedicated network card chips, general-purpose processors, and FPGA-based architectures. In recent years, with the continuous expansion of network scale, general-purpose processors are difficult to support the line-speed forwarding requirements of data packets in high-speed networks. As a compromise between general-purpose processors and dedicated chips, FPGAs are widely used in high-speed networks due to their programmable and high-performance characteristics.

[0003] In traditional network devices, network devices such as routers and switches use data plane and control plane algorithms to process data packets. Users can configure control plane functions and protocols, but the underlying algorithms are only changed by operators. In software-defined networks (SDN), users can deploy their own custom algorithms in network devices. Forwarding devices with programmable data planes provide the implementation of user-programmable functions. They use the "match-action" paradigm, and users can define protocol field processing methods and forwarding behaviors through programmable data planes.

[0004] The data plane in traditional SDN is a stateless data plane, whose network status information is completely managed by the controller, and the data plane is only responsible for forwarding functions.

[0005] The related patent application "Packet Programmable State Set (Publication No.: CN111771358A)" proposes a network device including a state set memory, whose state set retains the flow state information of the data packets passing through the network device, and the network device interacts with the state set to control the processing performed on the flow of the above data packets. The patented method implements the data packet processing and state set management functions based on the general-purpose processor of the computer, and the packet processing delay is relatively large. The related published paper "Open Packet Processor" proposes a hardware-implementable extended state machine model to deploy the state data plane on the hardware. The problem with the above method is that the consistency of the flow state information is not considered. Summary of the invention

[0006] The purpose of the present invention is to overcome the defects of the prior art and propose a data plane state programmable system and a switch based on FPGA.

[0007] A data plane state programmable system based on FPGA, the system comprising a matching action table pipeline with multiple stages;

[0008] The multi-level matching action table pipeline includes a plurality of ordered matching action table modules, each matching action table module is used to implement different data plane processing forwarding algorithms according to the read configuration instructions, combined with the flow state matching table and the conditional branch matching table; wherein the matching action table module includes:

[0009] A key value extraction module is used to extract fields from the packet header vector, the global state and / or the table state information according to the issued instructions to form a key value to be matched;

[0010] The flow state query module is used to match the flow address information of the packet from the flow state matching table according to the key value to be matched, and read the corresponding flow state information based on this address;

[0011] The packet header vector transmission queue is used to dynamically schedule the packet header vector for out-of-order transmission based on the flow state address and dependency relationship in the flow state information, using the flow state address in the flow state information as an identifier;

[0012] An action module, configured to determine a custom data plane processing forwarding algorithm through a conditional branch matching table according to the read configuration instruction, process the flow state information corresponding to the packet header vector transmitted out of order, and update the flow state information and table state information; and

[0013] The packet header vector reordering cache module is used to store the executed packet header vectors and submit the disordered packet header vectors in order.

[0014] Preferably, the output of each matching action table module can be used as the input of a subsequent matching action table module.

[0015] Preferably, the flow state matching table is a ternary content addressable memory matching table, a hash matching table or a longest prefix matching table.

[0016] Preferably, the packet header vector transmission queue includes:

[0017] The scoreboard is used to record the read and write operations of the flow state, and to determine whether the flow state of the packet header vector entering the packet header vector transmission queue depends on the write-back results of other packet header vectors to be executed;

[0018] The packet header vector transmission queue is used to cache the input packet header vector into the free table entry;

[0019] The selection logic is used to select a packet header vector with the longest time for which flow state information is ready from the packet header vector transmission queue in each clock cycle and transmit it to the action module, while the packet header vector for which flow state information is not ready continues to wait.

[0020] Preferably, the configuration instruction adopts a very long instruction word structure, and encapsulates multiple instructions with no data dependency into one very long instruction word.

[0021] Preferably, the action module includes a conditional branch judgment submodule, a state update submodule and a packet header vector action submodule, wherein:

[0022] The conditional branch judgment submodule is used to select fields from the packet header vector and the status information according to the configuration instruction, input them into several arithmetic logic units for calculating the comparison results that are executed in parallel and support very long instruction words, and determine the corresponding specific data plane processing forwarding algorithm in the conditional branch matching table according to the comparison result;

[0023] The status update submodule is used to update the status information according to the configuration instructions;

[0024] The packet header vector action submodule is used to modify the packet header vector.

[0025] On the other hand, the present invention provides a switch, comprising the above-mentioned FPGA-based data plane state programmable system.

[0026] Compared with the prior art, the advantages of the present invention are:

[0027] 1. The state data plane in this application allows network applications to store some network state information in the data plane. The state data plane adopts the "match-state-action" paradigm. The overall design of the module highlights programmability. It can implement user-defined algorithms by issuing configuration instructions. At the same time, it supports the deployment of some dynamic network applications and can select appropriate data packet forwarding strategies in real time according to the state information in the data plane;

[0028] 2. Compared with the stateless data plane of traditional SDN, the stateful data plane allows network applications to store some network status information on the data plane, reducing the interaction between the data plane and the control plane, and realizing more dynamic network functions;

[0029] 3. Flexibility: Ability to quickly change data plane functions and enable rapid deployment of new protocols;

[0030] 4. High performance: allows parallel processing of packet header vectors at the flow level, enabling line-speed processing and flow state consistency assurance;

[0031] 5. Dynamically schedule packet header vectors based on flow state addresses and dependencies, significantly improving packet processing speed while ensuring state consistency;

[0032] 6. Based on FPGA deployment, it has the advantages of low latency and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is the overall framework diagram of the data plane state programmable system based on FPGA of the present invention;

[0034] Figure 2 yes Figure 1 A matching action module architecture diagram in ;

[0035] Figure 3 yes Figure 2 The packet header vector transmit queue architecture diagram in ;

[0036] Figure 4 This is the conditional branch judgment submodule architecture diagram;

[0037] Figure 5 It is a state programmable data plane flow chart;

[0038] Figure 6 This is the architecture diagram of the arithmetic logic unit. DETAILED DESCRIPTION

[0039] The present invention aims at the demand for supporting packet processing based on state information and the demand for programmable flexibility in FPGA programmable switching chips, and proposes a programmable system based on FPGA supporting data plane state. Figure 1 The system includes a multi-stage matching action table pipeline; the multi-stage matching action table pipeline includes a plurality of ordered matching action table modules, each matching action table module is used to implement different data plane processing forwarding algorithms according to the read configuration instructions, combined with the flow state matching table and the conditional branch matching table. Figure 2 As shown, including:

[0040] A key value extraction module is used to extract fields from the packet header vector, the global state and / or the table state information according to the issued instructions to form a key value to be matched;

[0041] The flow state query module is used to match the flow address information of the packet from the flow state matching table according to the key value to be matched, and read the corresponding flow state information based on this address;

[0042] The packet header vector transmission queue is used to dynamically schedule the packet header vector for out-of-order transmission based on the flow state address and dependency relationship in the flow state information, using the flow state address in the flow state information as an identifier;

[0043] An action module, configured to determine a custom data plane processing forwarding algorithm through a conditional branch matching table according to the read configuration instruction, process the flow state information corresponding to the packet header vector transmitted out of order, and update the flow state information and table state information; and

[0044] The packet header vector reordering cache module is used to store the executed packet header vectors and submit the disordered packet header vectors in order.

[0045] The implementation steps of the programmable key value extraction module are: according to the issued instructions, extract fields from the packet header vector, global state, and table state to form the key value to be matched. This module supports key value extraction of up to 256 bits.

[0046] The implementation steps of the matching table are as follows: the matching table can be configured as a ternary content addressable memory (TCAM) matching table, a hash matching table or a longest prefix matching table, and can match the address information of the flow to which the packet belongs according to the input key value, and read the corresponding flow status information at this address.

[0047] The implementation steps of the flow state storage are: reading the flow state information in the storage module according to the input address information.

[0048] The implementation steps of the packet header vector transmission queue are as follows: using the flow state address as an identifier, according to the dependency of the flow state to which the packet header vector belongs, adjacent packet header vectors belonging to the same flow ID are scheduled in the transmission queue, and packet header vectors with flow state dependencies are blocked. The transmission queue caches the input packet header vectors into the idle table entries of the queue. Each clock cycle selects a packet header vector with the longest data readiness time to be transmitted to the pipeline, while the packet header vectors whose flow state information is not ready continue to wait in the transmission queue. After the flow state is updated, it will be broadcast to all entries in the transmission queue. The entries in the transmission queue determine whether the waiting flow state is ready based on the broadcasted flow state. The packet header vectors of the same flow are transmitted in order according to the updated flow state information, and different flows are transmitted out of order. Figure 3 shown.

[0049] The action module consists of a conditional branch judgment submodule, a state update submodule and a packet header vector action submodule.

[0050] The implementation steps of the conditional branch judgment submodule are as follows: according to the issued instructions, select fields from the packet header vector and the status information, and input them into several parallel executions, and support the arithmetic logic units for calculating the comparison results of the very long instruction words. The comparator can execute R-type and I-type instructions, and output the comparison judgment result as the basis for conditional branch judgment. The result can be spliced ​​with the flow state value as a three-state content addressable memory (TCAM) table query key value. Input it into the three-state content addressable memory (TCAM) conditional branch matching table to query the corresponding conditional branch instruction block address and determine the specific processing method of the packet with the current state value. Figure 4 It is the structural framework diagram of the conditional branch judgment submodule.

[0051] The implementation steps of the state update submodule and the packet header vector action submodule are as follows: according to the super long instruction word read from the instruction storage module, the current packet header vector and the modification and update instruction of the state information are determined. The arithmetic logic unit modifies the packet header vector and updates the state value according to the instruction.

[0052] The VLIW mentioned above is a computer instruction set architecture with highly parallel instructions. Multiple unrelated instructions are packaged into a VLIW. A processor that supports VLIW consists of multiple independent functional components. This structure simplifies hardware design and has strong data processing capabilities.

[0053] The implementation steps of the reorder buffer are as follows: the reorder buffer stores the packet header vectors executed by the pipeline, writes them to the corresponding addresses of the queue according to the ROB ID, and submits the out-of-order packet header vectors in order.

[0054] Figure 5 It is a state programmable data plane flow chart.

[0055] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0056] Example 1

[0057] Embodiment 1 of the present invention proposes a data plane status programmable system based on FPGA, and takes the implementation of counting the number of TCP retransmission data packets and the weighted round robin algorithm as an example for specific description. If other custom algorithms need to be implemented, they can be designed according to this principle.

[0058] Calculate the number of TCP retransmission packets. The implementation principle of the algorithm is as follows: for multiple packets that arrive in sequence belonging to the same flow, determine whether this packet is a retransmission packet by the seq sequence number in the TCP packet and the latest valid seq sequence number of the flow to which it belongs. If the seq sequence number of the current received packet is the same as or less than the seq number of the latest packet of the flow recorded by the module, the received packet is determined to be a retransmission packet. And use the flow state variable Num to record the number of retransmission packets of a flow.

[0059] The implementation method of the algorithm in the present application is to sequentially configure the corresponding instructions and table items of the data plane state programmable module components: programmable key value extraction module, matching table, state storage module, programmable condition judgment module, and state update module. First, the programmable key value extraction module will issue an instruction to extract a five-tuple (source IP address, destination IP address, source port number, destination port number, protocol number) from the packet header vector to form the Key to be matched. The flow matching table and the flow state storage module together constitute the flow state matching table shown below. The flow matching table matches the key value to obtain the flow state address, which is used to read the flow state information (R0, R1) from the storage module, which are respectively: the cumulative number of retransmitted packets of the flow to which the data packet belongs, flow i .Num; sequence number flow i .Seq, as shown in Table 1 below.

[0060] Table 1 Calculation of TCP retransmission packet quantity-flow state matching table

[0061]

[0062] In the conditional judgment module, the state information and the comparison judgment result can be used as the matching domain input. In this application, according to the instructions issued by the module, the size relationship between the seq sequence number of the current TCP packet and the maximum seq sequence number of the flow to which it belongs is judged, and the judgment result is output: C i (Indicates the size relationship between the packet seq number and the stream seq number). Enter the TCAM matching table shown in Table 2 below, match the corresponding conditional branch, obtain the instruction block address of the corresponding conditional branch, and read the super long instruction word from the instruction storage module according to the address. In Table 2, Key corresponds to the conditional branch to be matched, and Value corresponds to the matched instruction block.

[0063] Table 2 Calculation of TCP retransmission packet quantity - conditional branch matching table

[0064]

[0065] The state update and action arithmetic logic unit executes the corresponding instructions for updating the state information and modifying the packet header vector according to the very long instruction word read from the instruction storage module. In the current application of calculating the number of TCP retransmitted packets, the seq sequence number of the flow to which it belongs is updated according to the result of the conditional branch judgment. i .Seq) or the number of retransmitted packets (flow i .Num) increases by 1.

[0066] Example 2

[0067] Embodiment 2 of the present invention proposes a data plane state programmable system based on FPGA to implement a weighted polling scheduling algorithm.

[0068] Weighted round-robin scheduling is a load balancing algorithm. The implementation principle of this algorithm is: poll the optional path weight set of the current node. The arriving data packet will select the path corresponding to the current weight. After selecting the path, the current weight will be reduced by 1. Until the current weight value is reduced to 0, it will be restored to the initial weight value, and then jump to the next optional path. The above process is performed again until the weight value of the currently selected path is reduced to 0, and then restored to the initial weight value, and jump to the next optional path.

[0069] The following will take the application of 8 optional path weights as an example to illustrate the application of the data plane state programmable module, and explain the corresponding instruction configuration of each data plane state programmable module and the table entries under the matching action table. The information sent by the data plane table state storage module is the current node optional path set: {path[0], path[1], ..., path[7]}, the initial weight value of each path of the current node: {init[0], init[1], ..., init[7]}, and each packet header vector entering the matching action table can obtain the above table state information.

[0070] The programmable key value extraction module extracts the optional path set of the table state information and the corresponding field of the packet header vector according to the issued instructions, and generates the optional path subset mask of the data packet at the current node as the input query key value of the flow state matching table.

[0071] In the flow state matching table shown in Table 3 below, the variables {w0, w1, ..., w7} represent the current weight values ​​of the 8 optional paths of the flow, and the variables {nxt_w0, nxt_w1, ..., nxt_w7} represent the next hop optional path number of the current path. The index value range is 0 to 7, representing the current optional path number of the flow. The matching table can indicate the flow state information such as the path number and the path weight value of the current flow.

[0072] Table 3 Weighted round-robin scheduling-flow state matching table

[0073]

[0074]

[0075] In the conditional branch judgment module, the state can be used as a matching domain or as an arithmetic logic unit input. The module determines whether the current weight value has enough surplus according to the issued instructions. If the current weight value is greater than 1, continue to select the current path, otherwise jump to the next optional path: (the corresponding state update operation index = nxt_w index). The key value generated by the module enters the TCAM conditional branch matching table shown in Table 4 below, matches the corresponding conditional branch, obtains the instruction block address of the corresponding conditional branch, and reads the super long instruction word from the instruction storage module according to the address.

[0076] Table 4 Weighted round-robin scheduling-conditional branch matching table

[0077]

[0078]

[0079] The status update and action module performs the corresponding update status information and modification packet header vector operations according to the super long instruction word read out by the bear instruction storage module. In the current weighted polling scheduling application, the module will update the weight value (W i ) and index, and modify the corresponding indication path field in the packet header vector.

[0080] The conditional branch judgment module, state update and action module are composed of several parallel basic arithmetic logic units. The overall architecture of the arithmetic logic unit is as follows: Figure 6 As shown, its input is: two 32-bit operands oprand0 and oprand1, and a 32-bit instruction, and its output is a 32-bit result. The ALU supports 32-bit, 16-bit, and 8-bit operations and comparisons. Figure 6 The variable suffixes in: B3, B2, B1, B0, H1, H0, W represent 8-bit, 16-bit, 32-bit input, and the relative position in the 32-bit input width. The arithmetic logic unit supports the selection of input and output data relative addresses (such as result.B3 = oprand0.B0 + oprand1.B2, and the input data address can be selected and the output data address can be specified through instructions), with good programmability and flexibility.

[0081] It should be noted that the above two embodiments are only for illustrating how to implement the system in combination with a specific data forwarding algorithm, and are not limited to the above algorithms.

[0082] Example 3

[0083] An embodiment of the present invention provides a switch having the system of embodiment 1 or embodiment 2.

[0084] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A data plane state programmable system based on FPGA, characterized in that: The system includes a matching action table pipeline having multiple stages; The multi-level matching action table pipeline includes a plurality of ordered matching action table modules, each matching action table module is used to implement different data plane processing forwarding algorithms according to the read configuration instructions, combined with the flow state matching table and the conditional branch matching table; wherein the matching action table module includes: A key value extraction module is used to extract fields from the packet header vector, the global state and / or the table state information according to the issued instructions to form a key value to be matched; The flow state query module is used to match the flow address information of the packet from the flow state matching table according to the key value to be matched, and read the corresponding flow state information based on this address; The packet header vector transmission queue is used to dynamically schedule the packet header vector for out-of-order transmission based on the flow state address and dependency relationship in the flow state information, using the flow state address in the flow state information as an identifier; An action module, configured to determine a custom data plane processing forwarding algorithm through a conditional branch matching table according to the read configuration instruction, process the flow state information corresponding to the packet header vector transmitted out of order, and update the flow state information and table state information; and The packet header vector reordering cache module is used to store the executed packet header vectors and submit the disordered packet header vectors in order.

2. The FPGA-based data plane state programmable system according to claim 1, characterized in that: The output of each matching action table module can be used as the input of the subsequent matching action table module.

3. The FPGA-based data plane state programmable system according to claim 1, characterized in that: The flow state matching table is a ternary content addressable memory matching table, a hash matching table or a longest prefix matching table.

4. The FPGA-based data plane state programmable system according to claim 1, characterized in that: The packet header vector transmission queue includes: The scoreboard is used to record the read and write operations of the flow state, and to determine whether the flow state of the packet header vector entering the packet header vector transmission queue depends on the write-back results of other packet header vectors to be executed; The packet header vector transmission queue is used to cache the input packet header vector into the free table entry; The selection logic is used to select a packet header vector with the longest time for which flow state information is ready from the packet header vector transmission queue in each clock cycle and transmit it to the action module, while the packet header vector for which flow state information is not ready continues to wait.

5. The FPGA-based data plane state programmable system according to claim 1, characterized in that: The configuration instruction adopts a very long instruction word structure to encapsulate multiple instructions with no data dependency into one very long instruction word.

6. The FPGA-based data plane state programmable system according to claim 5, characterized in that: The action module includes a conditional branch judgment submodule, a state update submodule and a packet header vector action submodule, wherein: The conditional branch judgment submodule is used to select fields from the packet header vector and the status information according to the configuration instruction, input them into several arithmetic logic units for calculating the comparison results that are executed in parallel and support very long instruction words, and determine the corresponding specific data plane processing forwarding algorithm in the conditional branch matching table according to the comparison result; The status update submodule is used to update the status information according to the configuration instructions; The packet header vector action submodule is used to modify the packet header vector.

7. A switch, characterized in that: A data plane state programmable system based on FPGA comprising any one of claims 1-6.

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