BMS common DCDC power supply wake-up holding circuit

Abstract

The utility model relates to the technical field of power supply wake-up circuit design, in particular to a BMS (battery management system) common DCDC power supply wake-up holding circuit, which comprises a DCDC power supply chip U1, an eighth pin IN end of the DCDC power supply chip U1 is connected with a low-voltage 12V power supply LV-12V, a fifth pin EN end of the DCDC power supply chip U1 is connected with an enable control circuit, and the enable control circuit is topologically connected with a load switch circuit. According to the BMS common DCDC power supply wake-up holding circuit, a topological structure of an enabling control circuit, a load switch circuit and a power supply holding control circuit is arranged on a DCDC power supply chip U1, so that the working state of a common DCDC power supply is not influenced by an external wake-up source, and the DCDC power supply can be powered off to control the start and stop of the DCDC power supply by controlling I / O through an MCU; reliability and stability of output of the DCDC power supply are improved, abnormal power-off is avoided, and normal operation and data integrity of the system can be guaranteed.

Description

Technical Field

[0001] The utility model relates to the technical field of power supply wake-up circuit design, and in particular to a BMS common DCDC power supply wake-up holding circuit. Background Art

[0002] BMS is a battery management system. The wake-up and hold circuit of a common DCDC power supply can avoid abnormal power-off or abnormal data storage caused by the wake-up source being disconnected. At present, the working state of a common DCDC power supply is easily affected by the wake-up source. When the wake-up source is disconnected, the common DCDC power supply will directly enter the sleep state, or most common DCDC power supplies do not have a wake-up and hold function. Therefore, the circuit system power-off is not controlled by the MCU, which will cause abnormal power-off or abnormal data storage.

[0003] For example, application number CN202221123961.8 discloses a pulsed BMS wake-up circuit with power retention. By inputting a high-level signal at the positive and negative ends of the wake-up input, the capacitor C1 is charged after the voltage is divided by resistors R1 and R2. The BMS power-off is controlled by the MCU autonomously. When the MCU needs to power off, it can control PWR DN to enable NMOS Q2 and NMOS Q3 quickly resets capacitor C1 to prepare for the next power-on, so that the BMS is awakened after the wake-up source level is higher than a specific value for a certain period of time. At this time, the internal MCU enables the power retention signal, and the power-off of the BMS is controlled by the MCU. However, any failure in the power retention circuit may cause abnormal BMS function and affect the overall power management defects; Application No. CN201620529980.9 discloses a main power wake-up circuit, which shortens the wake-up time by setting an AC circuit that generates AC current, a DC-DC circuit that converts a higher DC voltage into a lower DC voltage, and a charging capacitor that receives a higher DC current at one end and wakes up the main current at the other end. However, for an ordinary DCDC power supply, the addition of an AC circuit and a DC-DC conversion circuit will increase the complexity of the circuit design, resulting in higher manufacturing costs and maintenance difficulties, as well as insufficient capacitor charging or circuit failures. The main power supply may not be woken up as expected, which will affect the response time and reliability of the system.

[0004] Therefore, the wake-up circuits in the two utility information patents disclosed above have the problem that, for the DCDC power supply, they rely on the stability of the external wake-up source. The lack of the wake-up retention function may cause data loss, file damage or system status errors, and the uncontrolled power-off of the system may affect the battery charging status and health information data storage, and other safety hazards. Utility Model Content

[0005] The purpose of the utility model is to provide a BMS common DCDC power supply wake-up and holding circuit to solve the technical problems mentioned in the above background technology.

[0006] In order to achieve the above-mentioned purpose, the utility model discloses a BMS common DCDC power supply wake-up and hold circuit, including a DCDC power supply chip U1, wherein the 8th pin IN end of the DCDC power supply chip U1 is connected to a low voltage 12V power supply LV-12V, the 5th pin EN end of the DCDC power supply chip U1 is connected to an enable control circuit, the enable control circuit is topologically connected to a load switch circuit, the load switch circuit is topologically connected to a power supply hold control circuit, and the DCDC power supply chip U1 is provided with a feedback circuit for output voltage regulation;

[0007] The power retention control circuit includes an N-type metal oxide semiconductor field effect transistor NMOS-M2, wherein pin 1 of the N-type metal oxide semiconductor field effect transistor NMOS-M2 is connected in series with an MCU output IO port current limiting resistor R7 and an MCU input / output port MCO-I / O, and pin 1 of the N-type metal oxide semiconductor field effect transistor NMOS-M2 is connected to a ground line GND, wherein the MCU input / output port MCO-I / O provides a control power retention signal to a gate of the N-type metal oxide semiconductor field effect transistor NMOS-M2 through the MCU output IO port current limiting resistor R7, and when the MCU input / output port MCO-I / O outputs a high level signal, the N-type metal oxide semiconductor field effect transistor NMOS-M2 is turned on and connected to the ground line GND, thereby realizing a circuit control link.

[0008] Optionally, the load switch circuit includes a P-type metal oxide semiconductor field effect transistor PMOS-M1, pin 2 of the P-type metal oxide semiconductor field effect transistor PMOS-M1 is connected to the DCDC power supply output voltage VDDA, and the circuit topology between pin 2 of the P-type metal oxide semiconductor field effect transistor PMOS-M1 and the DCDC power supply output voltage VDDA is connected in series with a wake-up holding voltage divider resistor R5 and a wake-up holding voltage divider resistor R6, pin 1 of the P-type metal oxide semiconductor field effect transistor PMOS-M1 is connected between the wake-up holding voltage divider resistor R5 and the wake-up holding voltage divider resistor R6, and the other end of the wake-up holding voltage divider resistor R6 is connected to pin 3 of the N-type metal oxide semiconductor field effect transistor NMOS-M2, wherein the P-type metal oxide semiconductor field effect transistor PMOS-M1 controls the connection and disconnection of the DCDC power supply output voltage VDDA, and is used to provide the DCDC power supply output voltage VDDA to the subsequent circuit as needed, and the control signal of the load switch circuit is provided by the power supply holding control circuit.

[0009] Optionally, the enable control circuit includes an external wake-up source EXT-KL15, the external wake-up source EXT-KL15 is connected in series with a wake-up source current limiting resistor R4, and the other end of the wake-up source current limiting resistor R4 is connected to the No. 5 pin EN end of the DCDC power chip U1, and the wake-up source current limiting resistor R4 and the No. 5 pin EN end of the DCDC power chip U1 are topologically connected to the No. 3 pin of the P-type metal oxide semiconductor field effect transistor PMOS-M1, wherein the signal sent by the external wake-up source EXT-KL15 is used to control the startup and shutdown of the DCDC power chip U1, and by adjusting the wake-up source current limiting resistor R4, the No. 5 pin EN end of the DCDC power chip U1 is protected from high current damage.

[0010] Optionally, the output voltage regulation feedback circuit is formed by topologically connecting a VDDA output regulation feedback resistor R1, a VDDA output regulation feedback resistor R2, a VDDA output regulation feedback resistor R3, a ground line GND and a DCDC power supply output voltage VDDA on a DCDC power supply chip U1, wherein a No. 3 pin PG end of the DCDC power supply chip U1 is connected in series with the VDDA output regulation feedback resistor R1, and the other end of the VDDA output regulation feedback resistor R1 is connected in series with the VDDA output regulation feedback resistor R2, the VDDA output regulation feedback resistor R3 and the ground line GND in sequence, a No. 1 pin OUT end of the DCDC power supply chip U1 is connected to the DCDC power supply output voltage VDDA, and is topologically connected between the VDDA output regulation feedback resistor R1 and the VDDA output regulation feedback resistor R2, and the VDDA output regulation feedback resistor R2 and the VDDA output regulation feedback resistor R3 are connected in series with the VDDA output regulation feedback resistor R2. The resistor R3 is topologically connected to the FB / DNC end of pin 2 of the DCDC power chip U1, and the VDDA output adjustment feedback resistor R3 and the ground wire GND are topologically connected to the GND end of pin 4 of the DCDC power chip U1 and the EP end of pin 9 of the DCDC power chip U1, respectively. Among them, for the 9 pins on the DCDC power chip U1, the OUT end of pin 1 is the output end, which is used to provide a stable DC output, the FB / DNC end of pin 2 is the feedback end / unconnected end, which is used for voltage feedback regulation and maintaining output stability, the PG end of pin 3 is the power good indication end, which is used to display the power status, the GND end of pin 4 is the ground end, the EN end of pin 5 is the enable end, which is used to control the on and off of the power supply, the NC end of pin 6 is the unconnected end, the DELAY end of pin 7 is the delay end, which is used to set the startup delay, the IN end of pin 8 is the input end, which is used to receive the input 12V voltage, and the EP end of pin 9 is an exposed pad.

[0011] Optionally, the external wake-up source EXT-KL15 is a 12V power input controlled by an ignition switch, KL15 is the key in the car matched to the first gear, used to activate non-engine running electronic devices, the DDA output adjustment resistor feedback resistor R1, the DDA output adjustment resistor feedback resistor R2 and the DDA output adjustment resistor feedback resistor R3 are all adjustable resistors with a resistance range of 10-100KΩ and an accuracy of 1%, which are used to adjust and feedback the power output of the DCDC power chip U1.

[0012] Optionally, the P-type metal oxide semiconductor field effect transistor PMOS-M1 is of model S-LBSS84LT1G, which is used in lower power applications to provide reverse current blocking and high-speed switching, and the N-type metal oxide semiconductor field effect transistor NMOS-M2 is of model 2N7002BK, which is used in high-efficiency switching and amplification applications, and the PMOS-M1 is turned off when controlled by a high-level signal, while the NMOS-M2l is turned on when the level is high.

[0013] Optionally, the wake-up source current limiting resistor R4 and the MCU output IO port current limiting resistor R7 have equal resistance values, both are 10Ω, with an accuracy of 1%, and are used for current limiting protection. The wake-up holding voltage dividing resistor R5 and the wake-up holding voltage dividing resistor R6 have equal resistance values, both are 5Ω, with an accuracy of 1%, and are used for voltage division and control.

[0014] Compared with the prior art, the utility model has the following advantages:

[0015] In the BMS common DCDC power wake-up and hold circuit, by setting the topological structure of the enable control circuit, the load switch circuit and the power hold control circuit on the DCDC power chip U1, the working state of the common DCDC power is not affected by the external wake-up source and the DCDC power can be powered off by the MCU to control the start and stop of the DCDC power. The reliability and stability of the DCDC power output are improved, abnormal power-off is avoided, the normal operation of the system and the data integrity can be guaranteed, the flexibility and programmability of the system are improved, and the design of the BMS common DCDC power wake-up and hold circuit effectively reduces the system failure or safety risk caused by abnormal operation or external interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the structure of the BMS common DCDC power supply wake-up and holding circuit of the utility model.

[0017] The accompanying drawings are marked as follows: 1. enabling control circuit; 2. feedback circuit for output voltage regulation; 3. load switch circuit; 4. power supply holding control circuit. DETAILED DESCRIPTION

[0018] The technical solution of the utility model is described in detail below through specific embodiments.

[0019] Reference Figure 1 As shown, the utility model discloses a BMS common DCDC power supply wake-up and hold circuit structure, including a DCDC power supply chip U1, the 8th pin IN end of the DCDC power supply chip U1 is connected to a low voltage 12V power supply LV-12V, the 5th pin EN end of the DCDC power supply chip U1 is connected to an enable control circuit 1, the enable control circuit 1 is topologically connected to a load switch circuit 3, the load switch circuit 3 is topologically connected to a power hold control circuit 4, and the DCDC power supply chip U1 is provided with a feedback circuit 2 for output voltage regulation;

[0020] The power retention control circuit 4 includes an N-type metal oxide semiconductor field effect transistor NMOS-M2, wherein pin 1 of the N-type metal oxide semiconductor field effect transistor NMOS-M2 is connected in series with the MCU output IO port current limiting resistor R7 and the MCU input / output port MCO-I / O in sequence, and pin 1 of the N-type metal oxide semiconductor field effect transistor NMOS-M2 is connected to the ground line GND, wherein the MCU input / output port MCO-I / O provides a control power retention signal to the gate of the N-type metal oxide semiconductor field effect transistor NMOS-M2 through the MCU output IO port current limiting resistor R7, and when the MCU input / output port MCO-I / O outputs a high-level signal, the N-type metal oxide semiconductor field effect transistor NMOS-M2 is turned on and connected to the ground line GND, thereby realizing a circuit control link to ensure that when the system needs to remain in a working state, even if the signal of the external wake-up source EXT-KL15 disappears, the power will not be immediately cut off.

[0021] Preferably, the load switch circuit 3 includes a P-type metal oxide semiconductor field effect transistor PMOS-M1, pin 2 of the P-type metal oxide semiconductor field effect transistor PMOS-M1 is connected to the DCDC power supply output voltage VDDA, and the circuit topology between pin 2 of the P-type metal oxide semiconductor field effect transistor PMOS-M1 and the DCDC power supply output voltage VDDA is connected in series with a wake-up holding voltage divider resistor R5 and a wake-up holding voltage divider resistor R6, pin 1 of the P-type metal oxide semiconductor field effect transistor PMOS-M1 is connected between the wake-up holding voltage divider resistor R5 and the wake-up holding voltage divider resistor R6, and the other end of the wake-up holding voltage divider resistor R6 is connected to pin 3 of the N-type metal oxide semiconductor field effect transistor NMOS-M2, wherein the P-type metal oxide semiconductor field effect transistor PMOS-M1 controls the connection and disconnection of the DCDC power supply output voltage VDDA, and is used to provide the DCDC power supply output voltage VDDA to the subsequent circuit as needed, and the control signal of the load switch circuit 3 is provided by the power supply holding control circuit 4.

[0022] Preferably, the enable control circuit 1 includes an external wake-up source EXT-KL15, the external wake-up source EXT-KL15 is connected in series with a wake-up source current limiting resistor R4, and the other end of the wake-up source current limiting resistor R4 is connected to the No. 5 pin EN end of the DCDC power chip U1, and the wake-up source current limiting resistor R4 and the No. 5 pin EN end of the DCDC power chip U1 are topologically connected to the No. 3 pin of the P-type metal oxide semiconductor field effect transistor PMOS-M1, wherein the signal sent by the external wake-up source EXT-KL15 is used to control the start and shutdown of the DCDC power chip U1, and by adjusting the wake-up source current limiting resistor R4, the No. 5 pin EN end of the DCDC power chip U1 is protected from damage by high current, and the pull-up or pull-down resistance of the No. 5 pin EN end of the DCDC power chip U1 can be adjusted so that it can respond correctly when the wake-up signal is received.

[0023] Preferably, the output voltage regulation feedback circuit 2 is formed by topologically connecting the VDDA output regulation feedback resistor R1, the VDDA output regulation feedback resistor R2, the VDDA output regulation feedback resistor R3, the ground line GND and the DCDC power supply output voltage VDDA on the DCDC power supply chip U1, wherein the No. 3 pin PG end of the DCDC power supply chip U1 is connected in series with the VDDA output regulation feedback resistor R1, and the other end of the VDDA output regulation feedback resistor R1 is connected in series with the VDDA output regulation feedback resistor R2, the VDDA output regulation feedback resistor R3 and the ground line GND in sequence, the No. 1 pin OUT end of the DCDC power supply chip U1 is connected to the DCDC power supply output voltage VDDA, and is topologically connected between the VDDA output regulation feedback resistor R1 and the VDDA output regulation feedback resistor R2, and the VDDA output regulation feedback resistor R2 and the VDDA output regulation feedback resistor R3 are topologically connected. At the FB / DNC end of pin 2 of the DCDC power chip U1, the VDDA output regulation feedback resistor R3 and the ground wire GND are topologically connected to the GND end of pin 4 of the DCDC power chip U1 and the EP end of pin 9 of the DCDC power chip U1, respectively. Among them, for the 9 pins on the DCDC power chip U1, the OUT end of pin 1 is the output end, which is used to provide a stable DC output, the FB / DNC end of pin 2 is the feedback end / unconnected end, which is used for voltage feedback regulation and maintaining output stability, the PG end of pin 3 is the power good indicator end, which is used to display the power status, the GND end of pin 4 is the ground end, the EN end of pin 5 is the enable end, which is used to control the on and off of the power supply, the NC end of pin 6 is the unconnected end, the DELAY end of pin 7 is the delay end, which is used to set the startup delay, the IN end of pin 8 is the input end, which is used to receive the input 12V voltage, and the EP end of pin 9 is an exposed pad for thermal management.

[0024] Preferably, the external wake-up source EXT-KL15 is a 12V power input controlled by the ignition switch, KL15 is the key in the car matched to the first gear, used to activate non-engine running electronic equipment, and in the BMS, the external wake-up source EXT-KL15 signal is used to trigger the wake-up circuit to ensure that the BMS system is activated when the car starts, the DDA output adjustment resistor feedback resistor R1, the DDA output adjustment resistor feedback resistor R2 and the DDA output adjustment resistor feedback resistor R3 are all adjustable resistors with a resistance range of 10-100KΩ and an accuracy of 1%, which are used to adjust and feedback the power output of the DCDC power chip U1.

[0025] Preferably, the P-type metal oxide semiconductor field effect transistor PMOS-M1 is of model S-LBSS84LT1G, which is used in lower power applications to provide reverse current blocking and high-speed switching, and the N-type metal oxide semiconductor field effect transistor NMOS-M2 is of model 2N7002BK, which is used in high-efficiency switching and amplification applications, and the PMOS-M1 is turned off when controlled by a high-level signal, while the NMOS-M2l is turned on when the level is high.

[0026] Preferably, the wake-up source current limiting resistor R4 and the MCU output IO port current limiting resistor R7 have equal resistance values, both of which are 10Ω, with an accuracy of 1%, and are used for current limiting protection. The wake-up holding voltage dividing resistor R5 and the wake-up holding voltage dividing resistor R6 have equal resistance values, both of which are 5Ω, with an accuracy of 1%, and are used for voltage division and control.

[0027] Working principle: During the DCDC power wake-up and hold process, first connect the low-voltage 12V power supply LV-12 to the regulated power supply 12V. Since the DCDC power chip U1 is not connected to the external wake-up source EXT-KL15 at this time, the DCDC power output voltage VDDA has no output. Then, when the external wake-up source EXT-KL15 is connected to the regulated power supply 12V, the DCDC power output voltage VDDA output is normal. When the DCDC power output voltage VDDA output is normal, the MCU input / output port MCO-I / O output is set to a high level to turn on the N-type metal oxide semiconductor field effect transistor NMOS-M2. When the N-type metal oxide semiconductor field effect transistor NMOS-M2 is turned on, the wake-up holding voltage divider resistor R6 is pulled down to the ground line GND. At this time, the P-type metal oxide semiconductor Pin 1 of the conductor field effect transistor PMOS-M1 is at a low level and can turn on the P-type metal oxide semiconductor field effect transistor PMOS-M1. Secondly, when the P-type metal oxide semiconductor field effect transistor PMOS-M1 is turned on, the voltage of the P-type metal oxide semiconductor field effect transistor PMOS-M1 flows through the P-type metal oxide semiconductor field effect transistor PMOS-M1 to the 5th pin EN of the DCDC power chip U1. At this time, there are two wake-up sources for the DCDC power chip U1, namely the load switch circuit 3 and the enable control circuit 1. Finally, when the external wake-up source EXT-KL15 is disconnected and the potential is 0V, because the load switch circuit 3 supplies power to the wake-up pin of the DCDC power chip U1, the DCDC power chip U1 can work normally, and the wake-up retention is achieved.

[0028] During the DCDC power hibernation process, when the system needs to hibernate, the external wake-up source EXT-KL15 is disconnected first, because the load switch circuit 3 supplies power to the EN end of the No. 5 pin of the DCDC power chip U1, so that the DCDC power chip U1 can work normally. Then, the host computer sends a hibernation instruction to the MCU input / output port MCO-I / O, and sets the I / O end to a low level. When the No. 1 pin of the N-type metal oxide semiconductor field effect transistor NMOS-M2 is at a low level, the N-type metal oxide semiconductor field effect transistor NMOS-M2 is disconnected. Secondly, when the N-type metal oxide semiconductor field effect transistor NMOS-M2 is disconnected, the No. 1 pin level of the P-type metal oxide semiconductor field effect transistor PMOS-M1 is at a high level, and the P-type metal oxide semiconductor field effect transistor PMOS-M1 is disconnected. When the P-type metal oxide semiconductor field effect transistor PMOS-M1 is disconnected, the wake-up pin of the DCDC power chip U1 is at a low level. Finally, when the No. 5 pin EN end of the DCDC power chip U1 is at a low level, the DCDC power chip U1 will enter the hibernation state.

[0029] The above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. Any modifications, equivalent substitutions, improvements, etc. made within the design concept of the utility model should be included in the protection scope of the utility model.

Claims

1. A BMS common DCDC power supply wake-up and hold circuit, characterized in that: The invention comprises a DCDC power chip U1, wherein the 8th pin IN of the DCDC power chip U1 is connected to a low voltage 12V power supply LV-12V, the 5th pin EN of the DCDC power chip U1 is connected to an enable control circuit (1), the enable control circuit (1) is topologically connected to a load switch circuit (3), the load switch circuit (3) is topologically connected to a power supply holding control circuit (4), and the DCDC power chip U1 is provided with an output voltage regulating feedback circuit (2); The power supply holding control circuit (4) comprises an N-type metal oxide semiconductor field effect transistor NMOS-M2, wherein pin 1 of the N-type metal oxide semiconductor field effect transistor NMOS-M2 is connected in series with a current limiting resistor R7 of an MCU output IO port and an MCU input / output port MCO-I / O, and pin 1 of the N-type metal oxide semiconductor field effect transistor NMOS-M2 is connected to a ground line GND.

2. A BMS common DCDC power supply wake-up and hold circuit according to claim 1, characterized in that: The load switch circuit (3) comprises a P-type metal oxide semiconductor field effect transistor PMOS-M1, wherein pin 2 of the P-type metal oxide semiconductor field effect transistor PMOS-M1 is connected to a DCDC power supply output voltage VDDA, and a wake-up holding voltage divider resistor R5 and a wake-up holding voltage divider resistor R6 are connected in series in the circuit topology between pin 2 of the P-type metal oxide semiconductor field effect transistor PMOS-M1 and the DCDC power supply output voltage VDDA, pin 1 of the P-type metal oxide semiconductor field effect transistor PMOS-M1 is connected between the wake-up holding voltage divider resistor R5 and the wake-up holding voltage divider resistor R6, and the other end of the wake-up holding voltage divider resistor R6 is connected to pin 3 of the N-type metal oxide semiconductor field effect transistor NMOS-M2.

3. A BMS common DCDC power supply wake-up and hold circuit according to claim 2, characterized in that: The enable control circuit (1) comprises an external wake-up source EXT-KL15, wherein the external wake-up source EXT-KL15 is connected in series with a wake-up source current limiting resistor R4, and the other end of the wake-up source current limiting resistor R4 is connected to a No. 5 pin EN end of the DCDC power chip U1, and the wake-up source current limiting resistor R4 and the No. 5 pin EN end of the DCDC power chip U1 are topologically connected to a No. 3 pin of the P-type metal oxide semiconductor field effect transistor PMOS-M1.

4. A BMS common DCDC power supply wake-up and holding circuit according to claim 3, characterized in that: The output voltage regulation feedback circuit (2) is formed by topologically connecting a VDDA output regulation feedback resistor R1, a VDDA output regulation feedback resistor R2, a VDDA output regulation feedback resistor R3, a ground line GND and a DCDC power supply output voltage VDDA on a DCDC power supply chip U1, wherein a No. 3 pin PG end of the DCDC power supply chip U1 is connected in series with the VDDA output regulation feedback resistor R1, and the other end of the VDDA output regulation feedback resistor R1 is connected in series with the VDDA output regulation feedback resistor R2, the VDDA output regulation feedback resistor R3 and the ground line GND in sequence, and the D The pin 1 OUT end of the CDC power chip U1 is connected to the DCDC power output voltage VDDA, and is topologically connected between the VDDA output regulation feedback resistor R1 and the VDDA output regulation feedback resistor R2. The VDDA output regulation feedback resistor R2 and the VDDA output regulation feedback resistor R3 are topologically connected to the pin 2 FB / DNC end of the DCDC power chip U1. The VDDA output regulation feedback resistor R3 and the ground wire GND are topologically connected to the pin 4 GND end of the DCDC power chip U1 and the pin 9 EP end of the DCDC power chip U1, respectively.

5. A BMS common DCDC power supply wake-up and hold circuit according to claim 4, characterized in that: The external wake-up source EXT-KL15 is a 12V power input controlled by an ignition switch, and the DDA output adjustment resistor feedback resistor R1, the DDA output adjustment resistor feedback resistor R2 and the DDA output adjustment resistor feedback resistor R3 are all adjustable resistors with a resistance range of 10-100KΩ and an accuracy of 1%.

6. A BMS common DCDC power supply wake-up and hold circuit according to claim 4, characterized in that: The model of the P-type metal oxide semiconductor field effect transistor PMOS-M1 is S-LBSS84LT1G, and the model of the N-type metal oxide semiconductor field effect transistor NMOS-M2 is 2N7002BK.

7. A BMS common DCDC power supply wake-up and hold circuit according to claim 4, characterized in that: The wake-up source current limiting resistor R4 and the MCU output IO port current limiting resistor R7 have the same resistance value, both of which are 10Ω, with an accuracy of 1%. The wake-up holding voltage dividing resistor R5 and the wake-up holding voltage dividing resistor R6 have the same resistance value, both of which are 5Ω, with an accuracy of 1%.

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