Method for preventing hierarchical order disorder of multi-layer PCB (Printed Circuit Board)
By adding digital identification and setting open areas on each layer of the multi-layer PCB, the problem of hierarchical order in the stacking process is solved, and a more efficient production process and lower cost waste is achieved.
Patent Information
- Application Number
- CN202411811161.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2025-03-21
AI Technical Summary
In the multi-layer PCB stacking process, the hierarchical order is prone to be disordered, resulting in the scrapping of the produced PCB and causing cost waste.
Add hierarchical identification at any position on each layer of PCB, design as digital identification, and determine the location of the open area through measurement and calculation, and set the open area to facilitate observation and superimposition of the board.
Through the design of hierarchical markings and open areas, operators can clearly understand the stacking order of the boards, avoid the problem of disordered hierarchical order, improve production efficiency, and reduce cost waste.
Smart Images
Figure CN119676992A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of PCBs, and in particular to a method for preventing a multi-layer PCB from having its layers disordered. Background Art
[0002] Multilayer PCB, or multilayer printed circuit board, refers to a printed circuit board composed of three or more conductive layers, each of which is usually composed of a copper layer, an insulating substrate, and a solder mask layer. Multilayer PCBs can provide higher circuit density, more complex circuit design, and better electrical performance. As the integration of PCBs becomes higher and higher, the distribution of circuits on the board becomes denser and denser. At the same time, in order to make the area of the board smaller and smaller, it can only be achieved by increasing the number of PCB layers, which leads to the current number of PCB layers increasing.
[0003] In the production process of multi-layer PCB, there is a key process step called stacking, which is essential to ensure the quality and performance of multi-layer PCB. The stacking process refers to the process of arranging and combining different material layers according to design requirements. When stacking, a layer of copper foil with a circuit pattern etched on it is usually placed as the bottom layer, and then one or more layers of prepreg are placed on the bottom copper foil, and then a layer of core material is placed on the prepreg, and the prepreg and core material are placed alternately until all layers are placed, and finally a layer of etched copper foil is placed on the top. The prepreg here usually acts as an adhesive in multi-layer PCBs, and the core material usually refers to a board with copper foil attached to both sides.
[0004] In the prior art, in the stacking process for producing multi-layer PCBs, workers generally stack the boards manually. Not only is it easy to make mistakes in the stacking order, but also because copper foil is attached to both sides of the boards, it is easy to make mistakes in the front and back sides of the stacked boards. Therefore, it is necessary to provide certain knowledge training to the employees who stack the boards on the production line to ensure that they can understand the correct stacking order. However, it takes a certain amount of time to provide corresponding training to the employees, and the employees on the production line are more popular. Therefore, training the employees cannot adapt well to the actual production rhythm. Once the boards are stacked incorrectly, the produced PCBs will be directly scrapped, resulting in cost waste. Therefore, it is urgent to design a method to solve the above problems. Summary of the invention
[0005] In view of the problem in the above technology that the produced PCB is scrapped due to the wrong stacking of the plates, resulting in cost waste, the present invention provides a method for preventing the disorder of the layer order of a multi-layer PCB, comprising the following steps: S1: Add a layer mark at any position of each layer of the multi-layer PCB; S2: Design the hierarchical identification as a digital identification, and number the digital identification on the plate according to the hierarchical level. The first level identification number is "1", the second level identification number is "2", the third level identification number is "3", and so on; S3: Arrange the positions of the digital identifications of each layer so that the digital identifications of any two layers will not overlap on the board surface after the boards are stacked; S4: Measure the length and width of the digital logo of each layer, and calculate the area occupied by all the digital logos on the board surface after stacking; S5: According to the calculated area, an open area is set at the corresponding position of each layer, and no other objects are added to the open area; S6: Observe the open areas on each layer and stack the boards according to the digital markings of the open areas.
[0006] As a further improvement of the present invention, before step S1, the number of layers of the multi-layer PCB is confirmed, and a multi-layer PCB with less than four layers is not designed with a layer identification, but is stacked according to other methods.
[0007] As a further improvement of the present invention, in step S2, for the layer designed on the back of the plate, the digital identification of the layer is designed as a mirror image character of the corresponding digital identification.
[0008] As a further improvement of the present invention, in step S3, the digital identification of each layer is designed with a uniform font and uniform size, and its arrangement is optimized so that the digital identifications presented on the board surface after stacking are arranged in order of size.
[0009] As a further improvement of the present invention, in step S4, the area occupied by all digital identifications on the board surface after stacking is determined by measuring the total length occupied from the hierarchical identification "1" to the digital identification of the last layer, and then measuring the width of the hierarchical identification characters.
[0010] As a further improvement of the present invention, in step S6, before stacking the plates, the digital identification of the plates is checked and whether the digital identification of the plates is a mirror image character, and then the plates are stacked according to the actual situation.
[0011] As a further improvement of the present invention, the hierarchical identification is a character formed by designing the film of the plate and then etching it.
[0012] As a further improvement of the present invention, the open area is arranged on the broken edge of the plate and avoids any circuit in the plate.
[0013] The beneficial effect of the present invention is as follows: compared with the prior art, the present invention provides a method for preventing disorder of the layer order of a multi-layer PCB, by providing an open area on the plate, adding layer identification in the open area, and then designing the layer identification as a digital identification, and then by observing the digital identification, the workers operating the stacking of the plates can easily understand the order in which the plates need to be stacked, thereby avoiding the problem of disorder of the layer order when stacking the plates. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 It is a flow chart of the present invention.
[0015] Figure 2 Schematic diagram of an embodiment of the present invention.
[0016] Figure 3 It is a top view of an embodiment of the present invention.
[0017] Figure 4 FIG. 1 is a top view of another embodiment of the present invention.
[0018] The main component symbols are described as follows: 1. First level; 2. Second level; 3. Third level; 4. Fourth level; 5. Fifth level; 6. Surface copper foil; 7. Prepreg; 8. Board; 9. Open area; 10. Digital identification. DETAILED DESCRIPTION
[0019] In order to more clearly illustrate the present invention, the present invention is further described below in conjunction with the accompanying drawings.
[0020] In the following description, general election example details are given to provide a deeper understanding of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all embodiments. It should be understood that the specific embodiments are only used to explain the present invention and are not used to limit the present invention.
[0021] It should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the existence of features, integers, steps, operations, elements or components, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components or combinations thereof.
[0022] See also Figure 1A method for preventing disorder of the layer order of a multi-layer PCB of the present invention comprises the following steps: S1: adding a layer mark at any position of each layer of the multi-layer PCB; S2: designing the layer mark as a digital mark, and numbering the layers by the digital marks on the plates, the first layer mark number is "1", the second layer mark number is "2", the third layer mark number is "3", and so on; S3: arranging the positions of the digital marks of each layer so that the digital marks of any two layers will not overlap on the plate surface after the plates are stacked; S4: measuring the length and width of the digital marks of each layer, and calculating the area occupied by all the digital marks on the plate surface after the plates are stacked; S5: according to the calculated area, setting an open area at the corresponding position of each layer, and no other objects are added to the open area; S6: observing the open area of each layer, and stacking the plates according to the digital marks of the open area. In this method, firstly, according to actual production needs, digital identification representing the level of multi-layer PCB is added on one side or both sides of the plate. The digital identification is arranged in order of level as "1", "2", "3" and so on. When the plates are stacked, all the digital identifications can be seen on the stacked board, that is, the digital identifications do not overlap with each other and are designed at different positions on the board. However, since the material of the plate cannot be completely transparent, and the stacking of the plates often starts from the bottom, the level digital identification of the bottom plate will become more and more blurred during the continuous stacking of the plates. Then the area occupied by the digital identification of each layer is measured. Since the digital identifications do not overlap with each other, the areas of the digital identifications in all levels are added up to get the area occupied by all the digital identifications on the board. This area is designed as an open area. Only digital identifications can be designed in the open area, and no other substances can be added. Setting this open area enables the workers on the production line to clearly observe which level the circuit design of the plate belongs to. At the same time, when the workers stack the plates, they can also check whether the stacked plates are correct according to the digital identification in the open area.
[0023] See also Figure 1 Before step S1, the number of layers of the multi-layer PCB is confirmed. If the number of layers is less than four, no layer identification is designed, and the stacking is performed according to other methods. Because the stacking operation of a multi-layer PCB with fewer layers does not need to be judged by digital identification, on the contrary, digital identification on a multi-layer PCB with fewer layers will cause unnecessary waste.
[0024] See also Figure 1In step S2, for the level designed on the back of the board, the digital identification of the level is designed as a mirror image character of the corresponding digital identification. In the production of multi-layer PCBs, the board located in the middle often has circuits designed on both the front and back sides. Therefore, when stacking boards, if the digital identification on the back of the board is not set to a mirror image, then during the stacking operation, the digital identification on the back of the board is observed through the front of the board as a mirror image, so it will affect the judgment during the stacking operation to a certain extent; however, there are some special cases, specifically, the digital identification on the back of the board is deliberately not set to a mirror image, but is designed according to the original normal form. Under this design, when the board is stacked, the boards are stacked in sequence according to the size of the digital identification. It can be quickly judged whether a certain level is designed on the front or back of the board according to the digital identification in the open area. If the digital identification is in a normal form, it means that the level of the digital identification is designed on the front of the board. If the digital identification is in a mirror image, it means that the level of the digital identification is designed on the back of the board. Therefore, through this design, it can intuitively reflect that the level is located on the front and back of the board, thereby facilitating subsequent inspections.
[0025] See also Figure 1 In step S3, the digital identification of each layer is designed to be of uniform font and uniform size, and its arrangement is optimized so that the digital identifications presented on the board surface after stacking are arranged in order of size; this design makes it convenient to check the stacking status of the previous boards when stacking the boards, and makes the digital identifications relatively concentrated for easy verification, so that the positions of the digital identifications of each level are staggered and arranged in sequence according to the size of the numbers on the board surface, and are arranged in a row on the board surface, that is, all the digital identifications can be observed on the board surfaces at the beginning and end.
[0026] See also Figure 1 In step S4, the area occupied by all digital logos on the board after stacking is determined by measuring the overall length occupied by the digital logo from the level logo "1" to the last layer, and then measuring the width of the level logo characters; after the above design, the measurement of the area occupied by the digital logo is also much more convenient. By measuring the length and width of the area occupied by the digital logos lined up in a row, the empty area can be set according to the length and width, which simplifies the process of calculating and merging the area of each layer of digital logos.
[0027] See also Figure 1In step S6, before stacking the plates, check the digital identification of the plates and check whether the digital identification of the plates is a mirror image character, and then stack the plates according to the actual situation; in the circuit design of the plates, it is first necessary to clarify whether the digital identification on the back of the plates needs to be designed as a mirror image. The numbers on the back of the plates are designed as a mirror image, which can enable workers to quickly determine whether the stacking is correct when stacking the plates. The numbers on the back of the plates are not designed as a mirror image, which can quickly confirm the front and back positions of the plates at the level when analyzing abnormal plates. Therefore, corresponding designs can be made according to different needs. After the design is completed, the workers stack the plates according to the digital identification on the plates, and check whether the previous stacking order is correct when stacking the plates, and then stack the plates based on the original ones. Because when the number of plates to be stacked is large, the digital identification marked on the plates stacked earlier often becomes blurred and difficult to observe, so when stacking the plates, it is necessary to constantly observe the changes in the digital identification to avoid the occurrence of missed plates.
[0028] See also Figure 1 The hierarchical identification is formed by designing the film of the plate and then etching the characters; when designing the circuit of the plate, an empty area is reserved in the plate, and the corresponding digital identification is designed in the empty area. Then, the film is attached to the plate, coated with photoresist, cured, and etched to form the digital identification. In the subsequent process, the solder mask ink sprayed needs to avoid the empty area so that the layer of the plate can be identified from the empty area later.
[0029] See also Figure 1 , the open area is set on the broken edge of the board and avoids any circuits in the board. The broken edge here refers to the weak part designed to separate individual circuit boards from large materials during the production process of PCB. These parts can be easily broken after production is completed to obtain independent PCBs. The broken edge is usually located at the edge of the PCB. At the same time, designing the open area at the edge of the PCB board is more conducive to observation and will not affect the circuit design of the PCB board.
[0030] The advantages of the present invention are: 1. Set up an open area on the plate and add layer identification in the open area to clearly confirm whether the stacking layer is wrong.
[0031] 2. Design normal digital identification or mirror digital identification on the front and back of the plate as required. When an abnormal plate appears, it can be used as a basis for judgment when taking the plate for analysis.
[0032] 3. The open area is designed on the broken edge of the plate to facilitate identification by operators.
[0033] The above disclosures are only several specific embodiments of the present invention, but the present invention is not limited thereto, and any changes that can be conceived by those skilled in the art should fall within the protection scope of the present invention.
Claims
1. A method for preventing the disorder of the layer order of a multi-layer PCB, characterized in that: The following steps are involved: S1: Add layer identification to the board material for making multi-layer PCB, and the layer identification is designed as a digital identification; S2: Number the digital labels on the plate by level, the first level is numbered "1", the second level is numbered "2", the third level is numbered "3", and so on; S3: Arrange the positions of the digital identifications of each layer so that the digital identifications of any two layers do not overlap on the board surface after the boards are stacked; S4: Measure the length and width of the digital logo of each layer, and calculate the total area occupied by all the digital logos on the board surface after stacking; S5: According to the calculated total area, an open area is set at the corresponding position of each layer, and no other objects are added to the open area; S6: Observe the open areas on each layer and stack the boards according to the digital markings of the open areas.
2. The method for preventing the disorder of the layer order of a multi-layer PCB according to claim 1 is characterized in that: Before step S1, the number of layers of the multi-layer PCB is confirmed. A multi-layer PCB with less than four layers is not designed with a layer identification, but is stacked according to other methods.
3. The method for preventing the disorder of the layer order of a multi-layer PCB according to claim 1 is characterized in that: In step S2, for the layer designed on the back side of the plate, the digital identification of the layer is designed as a mirror image character of the corresponding digital identification.
4. The method for preventing the disorder of the layer order of a multi-layer PCB according to claim 1 is characterized in that: In step S3, the digital identification of each layer is designed to be in a uniform font and size, and the arrangement thereof is optimized so that the digital identifications presented on the board surface after stacking are arranged in order of size.
5. The method for preventing the disorder of the layer order of a multi-layer PCB according to claim 4 is characterized in that: In step S4, the area occupied by all digital labels on the board after stacking is determined by measuring the overall length from the level label "1" to the last digital label and then measuring the width of the level label characters.
6. The method for preventing the disorder of the layer order of a multi-layer PCB according to claim 4, characterized in that: In step S6, before stacking the plates, the digital identifications of the plates are checked and whether the digital identifications of the plates are mirror images, and then the plates are stacked according to the actual situation.
7. The method for preventing the disorder of the layer order of a multi-layer PCB according to claim 1, characterized in that: The hierarchical logo is formed by designing the film of the plate and then etching it.
8. The method for preventing the disorder of the layer order of a multi-layer PCB according to claim 1, characterized in that: The open area is arranged on the broken edge of the plate and avoids any circuit in the plate.