Resistive random access memory element and manufacturing method thereof

Abstract

The invention discloses a resistive random access memory element. The resistive random access memory element comprises a substrate; a dielectric layer disposed on the substrate; a conductive via disposed in the dielectric layer; the metal nitride layer is arranged on the conductive through hole, and the metal nitride layer has gradient nitrogen concentration in the thickness direction of the metal nitride layer; the resistance switching layer is arranged on the metal nitride layer; and the metal nitrogen oxide layer is arranged on the resistance switching layer, and the metal nitrogen oxide layer has gradient nitrogen concentration in the thickness direction of the metal nitrogen oxide layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an improved resistance random access memory element and a manufacturing method thereof. Background Art

[0002] Resistive random access memory (RRAM) is a memory structure that includes an array of RRAM cells, each of which uses resistance value rather than charge to store a bit of data. Specifically, each RRAM cell includes a layer of resistance-switching material whose resistance can be adjusted to represent a logical "0" or a logical "1".

[0003] At advanced technology nodes, feature sizes are scaled down, and the size of memory devices is also shrinking accordingly. However, the scaling of RRAM devices is limited due to the "forming" operation. During the "forming" process, high voltage is applied to the RRAM device to generate a conductive path in the resistance switching material layer.

[0004] Existing HfO x The RRAM device faces the problem of insufficient operating window. When the bit line voltage is too high, it is easy to cause oxygen atoms to diffuse outward, and when the source line voltage is too high, too many oxygen atoms will be trapped in the HfO x In the titanium metal layer below the resistive switching layer. Summary of the invention

[0005] The main purpose of the present invention is to provide an improved resistance random access memory element and a manufacturing method thereof to solve the deficiencies or shortcomings of the prior art.

[0006] On one hand, the present invention provides a resistive random access memory element, comprising a substrate; a dielectric layer disposed on the substrate; a conductive via disposed in the dielectric layer; a metal nitride layer disposed on the conductive via, wherein the metal nitride layer has a gradient nitrogen concentration in a thickness direction thereof; a resistance switching layer disposed on the metal nitride layer; and a metal nitride oxide layer disposed on the resistance switching layer, wherein the metal nitride oxide layer has a gradient nitrogen concentration in a thickness direction thereof.

[0007] According to an embodiment of the present invention, the resistance switching layer includes a HfO2 layer.

[0008] According to an embodiment of the present invention, the thickness of the HfO2 layer is 50 angstroms.

[0009] According to an embodiment of the present invention, the metal oxynitride layer includes TiO x N y or TaO x N y , where x is between 0 and 1, and y is between 0 and 1.

[0010] According to an embodiment of the present invention, the metal oxynitride layer includes an oxygen-rich TiO x N y Layers where x is greater than 0.5 and y is less than 0.5.

[0011] According to an embodiment of the present invention, the oxygen-rich TiO x N y The thickness of the layer is 10 to 20 angstroms.

[0012] According to an embodiment of the present invention, the metal oxynitride layer includes nitrogen-rich TiO x N y Layers where x is less than 0.5 and y is greater than 0.5.

[0013] According to an embodiment of the present invention, the nitrogen-rich TiO x N y The thickness of the layer is 200 to 500 angstroms.

[0014] According to an embodiment of the present invention, the conductive via is a tungsten via.

[0015] According to an embodiment of the present invention, the conductive via is in direct contact with the metal nitride layer.

[0016] Another aspect of the present invention provides a method for forming a resistive random access memory element, comprising the following steps: providing a substrate; forming a dielectric layer on the substrate; forming a conductive via in the dielectric layer; forming a metal nitride layer on the conductive via, wherein the metal nitride has a gradient nitrogen concentration in a thickness direction; forming a resistance switching layer on the metal nitride layer; and forming a metal oxynitride layer on the resistance switching layer, wherein the metal oxynitride layer has a gradient nitrogen concentration in a thickness direction.

[0017] According to an embodiment of the present invention, the resistance switching layer includes a HfO2 layer.

[0018] According to an embodiment of the present invention, the thickness of the HfO2 layer is 50 angstroms.

[0019] According to an embodiment of the present invention, the metal oxynitride layer includes TiO x N y or TaO x N y , where x is between 0 and 1, and y is between 0 and 1.

[0020] According to an embodiment of the present invention, the metal oxynitride layer includes an oxygen-rich TiO x N y Layers where x is greater than 0.5 and y is less than 0.5.

[0021] According to an embodiment of the present invention, the oxygen-rich TiO x N y The thickness of the layer is 10 to 20 angstroms.

[0022] According to an embodiment of the present invention, the metal oxynitride layer includes nitrogen-rich TiO x N y Layers where x is less than 0.5 and y is greater than 0.5.

[0023] According to an embodiment of the present invention, the nitrogen-rich TiO x N y The thickness of the layer is 200 to 500 angstroms.

[0024] According to an embodiment of the present invention, the conductive via is a tungsten via.

[0025] According to an embodiment of the present invention, the conductive via is in direct contact with the metal nitride layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 6 It is a schematic diagram of a method for forming a resistance switching element according to an embodiment of the present invention.

[0027] Explanation of symbols

[0028] 1 Resistor switching component

[0029] 100 Base

[0030] 102 Conductive structure

[0031] 110 Dielectric layer

[0032] 111 Through hole

[0033] 112 Metal Layer

[0034] 112a Conductive via

[0035] 120 Metal nitride layer

[0036] 121 bottom layer

[0037] 122 Middle Layer

[0038] 123 Top layer

[0039] 130 resistance switching layer

[0040] 140 Metal Oxynitride Layer

[0041] 140a oxygen-rich TiO x N y layer

[0042] 140b Nitrogen-rich TiO x Ny layer

[0043] 141 bottom layer

[0044] 142 Middle Layer

[0045] 143 Top Layer

[0046] 210 Intermetallic Dielectric Layer

[0047] 220 Conductive contact structure

[0048] NS storage structure

[0049] S1, S2 top surface

[0050] SP spacer DETAILED DESCRIPTION

[0051] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0052] Of course, other embodiments may be implemented, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0053] See also Figures 1 to 6 , which is a schematic diagram of a method for forming a resistance switching element 1 according to an embodiment of the present invention. Figure 1 As shown, first, a substrate 100 is provided, such as a silicon substrate. At least one conductive structure 102 is formed on the substrate 100, such as a metal layer or a metal pad, but is not limited thereto. According to an embodiment of the present invention, for example, the conductive structure 102 can be a damascene copper structure. Those skilled in the art should understand that the substrate 100 can further include circuit components, dielectric layers, and interconnect structures, etc., which are not shown in the figure for simplicity of description.

[0054] Next, a dielectric layer 110 is formed on the substrate 100 to cover the conductive structure 102. According to an embodiment of the present invention, for example, the dielectric layer 110 may include a dielectric material such as silicon oxide. A through hole 111 is formed in the dielectric layer 110 using photolithography and etching processes to expose a portion of the conductive structure 102. Next, a metal layer 112, for example, a tungsten metal layer, is deposited on the substrate 100 to fill the through hole 111.

[0055] like Figure 2As shown, a chemical mechanical polishing (CMP) process is then performed to remove the metal layer 112 outside the through hole 111, leaving only the metal layer 112 inside the through hole 111, thereby forming a conductive through hole 112a. According to an embodiment of the present invention, the conductive through hole 112a is a tungsten through hole. At this time, the top surface S1 of the conductive through hole 112a is coplanar with the top surface S2 of the first dielectric layer 110.

[0056] like Figure 3 As shown, a chemical vapor deposition (CVD) process, such as an atomic layer deposition (ALD) method, is performed to form a metal nitride layer 120 on the conductive via 112a and the dielectric layer 110. According to an embodiment of the present invention, the metal nitride layer 120 has a gradient nitrogen concentration in the thickness direction, and has a higher nitrogen concentration near the conductive via 112a.

[0057] According to an embodiment of the present invention, for example, the metal nitride layer 120 includes a bottom layer 121 directly in contact with the conductive via 112a, an intermediate layer 122 located on the bottom layer 121, and a top layer 123 located on the intermediate layer 122, wherein the nitrogen concentration of the bottom layer 121 is higher than the nitrogen concentration of the intermediate layer 122, and the nitrogen concentration of the intermediate layer 122 is higher than the nitrogen concentration of the top layer 123.

[0058] According to an embodiment of the present invention, for example, the metal nitride layer 120 includes titanium nitride, wherein the bottom layer 121 may be a nitrogen-rich titanium nitride layer (e.g., Ti:N=1:1) deposited by multiple TiN ALD cycles, and its thickness may be, for example, between 100 and 200 angstroms, the middle layer 122 may be a titanium nitride layer (e.g., Ti:N=1:0.5) deposited by multiple TiN ALD cycles and multiple Ti ALD cycles, and the top layer 123 may be a titanium layer (e.g., Ti:N=1:0) deposited by multiple Ti ALD cycles, and its thickness may be, for example, less than 100 angstroms. According to an embodiment of the present invention, the bottom layer 121 of the metal nitride layer 120 is used as a bottom electrode of the resistance switching element 1, and the top layer 123 may be used as an oxygen storage layer of the resistance switching element 1.

[0059] like Figure 4As shown, a chemical vapor deposition process, such as an atomic layer deposition method, can then be continued to form a resistance switching layer 130 on the metal nitride layer 120. According to an embodiment of the present invention, the resistance switching layer 130 may include a HfO2 layer with a thickness of about 50 angstroms. According to other embodiments of the present invention, the resistance switching layer 130 may include a transition metal oxide such as TiO2 or Ta2O5.

[0060] like Figure 5 As shown, a chemical vapor deposition process, such as an atomic layer deposition method, can be continued to form a metal oxynitride layer 140 on the resistance switching layer 130, wherein the metal oxynitride layer 140 has a gradient nitrogen concentration in the thickness direction. According to an embodiment of the present invention, the metal oxynitride layer 140 includes TiO x N y or TaO x N y , where x is between 0 and 1, and y is between 0 and 1.

[0061] According to an embodiment of the present invention, for example, the metal nitride oxide layer 140 includes a bottom layer 141 directly in contact with the resistance switching layer 130, an intermediate layer 142 located on the bottom layer 141, and a top layer 143 located on the intermediate layer 142, wherein the nitrogen concentration of the bottom layer 141 is lower than the nitrogen concentration of the intermediate layer 142, and the nitrogen concentration of the intermediate layer 142 is lower than the nitrogen concentration of the top layer 143.

[0062] According to an embodiment of the present invention, for example, the metal oxynitride layer 140 is TiO x N y , where x is between 0 and 1, and y is between 0 and 1. The bottom layer 141 can be an oxygen-rich titanium nitride layer (e.g., Ti:O:N=1:1:0) deposited by multiple Ti ALD cycles and oxygen treatment steps, and the middle layer 142 can be a TiO deposited by multiple Ti ALD cycles, oxygen treatment steps, and TiN ALD cycles. x N y The top layer 143 may be a titanium nitride layer (e.g., Ti:O:N=1:0.5:0.5) deposited by multiple TiNALD cycles. According to an embodiment of the present invention, the top layer 143 of the metal nitride oxide layer 140 is used as a top electrode of the resistance switching component 1, and the bottom layer 141 may be used as an oxygen barrier layer of the resistance switching component 1.

[0063] According to an embodiment of the present invention, the metal oxynitride layer 140 includes an oxygen-rich TiO x N yLayer 140a, wherein x is greater than 0.5 and y is less than 0.5. According to an embodiment of the present invention, oxygen-rich TiO x N y The layer 140a includes a bottom layer 141 and a portion of an intermediate layer 142, and has a thickness of, for example, 10-20 angstroms. According to an embodiment of the present invention, the metal nitride oxide layer 140 includes nitrogen-rich TiO x N y Layer 140b, wherein x is less than 0.5 and y is greater than 0.5. According to an embodiment of the present invention, nitrogen-rich TiO x N y The thickness of the layer 140 b is, for example, 200 to 500 angstroms.

[0064] like Figure 5 As shown, then, a photolithography process and an etching process are performed to pattern the film stack structure composed of the metal nitride layer 120, the resistance switching layer 130 and the metal oxynitride layer 140, and a storage structure NS is formed on the conductive via 112a. Then, a chemical vapor deposition process and a back etching process can be performed to form a spacer SP on the sidewall of the storage structure NS, for example, a silicon nitride spacer. Then, a chemical vapor deposition process can be performed to deposit a metal interlayer dielectric layer 210, for example, a silicon oxide layer, on the storage structure NS and the spacer SP. Finally, a metallization process is performed to form a conductive contact structure 220, for example, a copper damascene structure, in the metal interlayer dielectric layer 210 directly above the storage structure NS.

[0065] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A resistive random access memory element, comprising: substrate; A dielectric layer is disposed on the substrate; A conductive via is disposed in the dielectric layer; a metal nitride layer disposed on the conductive via, wherein the metal nitride layer has a gradient nitrogen concentration in a thickness direction thereof; A resistance switching layer is disposed on the metal nitride layer; as well as The metal nitride oxide layer is disposed on the resistance switching layer, wherein the metal nitride oxide layer has a gradient nitrogen concentration in a thickness direction thereof.

2. The resistance random access memory element according to claim 1, wherein: The resistance switching layer includes a HfO2 layer.

3. The resistance random access memory element according to claim 2, wherein: The thickness of the HfO2 layer is 50 angstroms.

4. The resistance random access memory element according to claim 1, wherein: The metal oxynitride layer includes TiO x N y or TaO x N y , where x is between 0 and 1, and y is between 0 and 1.

5. The resistance random access memory element according to claim 1, wherein: The metal oxynitride layer includes an oxygen-rich TiO x N y Layers where x is greater than 0.5 and y is less than 0.

5.

6. The resistance random access memory element according to claim 5, wherein: The oxygen-rich TiO x N y The thickness of the layer is 10 to 20 angstroms.

7. The resistance random access memory element according to claim 1, wherein: The metal oxynitride layer includes nitrogen-rich TiO x N y Layers where x is less than 0.5 and y is greater than 0.

5.

8. The resistance random access memory element according to claim 7, wherein: The nitrogen-rich TiO x N y The thickness of the layer is 200 to 500 angstroms.

9. The resistance random access memory element according to claim 1, wherein: The conductive via is a tungsten via.

10. The resistance random access memory element according to claim 1, wherein: The conductive via is in direct contact with the metal nitride layer.

11. A method of forming a resistive random access memory element, comprising: forming a base; forming a dielectric layer on the substrate; forming a conductive via in the dielectric layer; forming a metal nitride layer on the conductive via, wherein the metal nitride layer has a gradient nitrogen concentration in a thickness direction thereof; forming a resistance switching layer on the metal nitride layer; as well as A metal oxynitride layer is formed on the resistance switching layer, wherein the metal oxynitride layer has a gradient nitrogen concentration in a thickness direction thereof.

12. The method of claim 1, wherein: The resistance switching layer includes a HfO2 layer.

13. The method of claim 12, wherein: The thickness of the HfO2 layer is 50 angstroms.

14. The method of claim 11, wherein: The metal oxynitride layer includes TiO x N y or TaO x N y , where x is between 0 and 1, and y is between 0 and 1.

15. The method of claim 11, wherein: The metal oxynitride layer includes an oxygen-rich TiO x N y Layers where x is greater than 0.5 and y is less than 0.

5.

16. The method of claim 15, wherein: The oxygen-rich TiO x N y The thickness of the layer is 10 to 20 angstroms.

17. The method of claim 11, wherein: The metal oxynitride layer includes nitrogen-rich TiO x N y Layers where x is less than 0.5 and y is greater than 0.

5.

18. The method of claim 17, wherein: The nitrogen-rich TiO x N y The thickness of the layer is 200 to 500 angstroms.

19. The method of claim 11, wherein: The conductive via is a tungsten via.

20. The method of claim 11, wherein: The conductive via is in direct contact with the metal nitride layer.

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