Semiconductor structure and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a chip and electronic equipment, and the semiconductor structure comprises a substrate, a device is formed on the substrate, the substrate comprises a target region located below the device, and the target region is different from other regions of the substrate in material crystalline state, so that the target region generates stress, and the stress is reduced. And the generated stress can be transmitted to the channel region of the device and accumulated in the channel region, so that the mobility of carriers in the channel region of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof, a chip and an electronic device. Background Art

[0002] With the development of integrated circuit related manufacturing processes and the trend of chip size reduction, the role of stress engineering in semiconductor processes and device performance is becoming more and more obvious.

[0003] Generally, there are various stresses in the complex manufacturing process of metal oxide semiconductor devices. As the device size gradually decreases, the stress that is finally left in the channel region of the device has a great influence on the stability of the device. Many stresses improve the performance of the device, and different types of stresses have different effects on the mobility of carriers (i.e., electrons and holes) in the device. The influence of the stress layer on the mobility of carriers has been disclosed in the current field of stress of semiconductor devices. For example, if tensile stress is applied in the channel direction of the channel region of an N-type MOS (NMOS) device, the electron mobility in the NMOS device will be greatly improved; while for a P-type MOS (PMOS) device, the stress effect is just the opposite. If compressive stress is applied in the channel direction of a PMOS device, the hole mobility in the PMOS device will be greatly improved.

[0004] As the process nodes are reduced, how to use stress to increase the mobility of carriers in MOS transistors has become an issue that attracts more and more attention. Summary of the invention

[0005] The purpose of this application is to provide a semiconductor structure and a method for preparing the same, a chip and an electronic device.

[0006] In a first aspect, the present application provides a semiconductor structure, including a substrate on which a device is formed; the substrate includes a target region located below the device, and the target region has a material crystalline state different from that of other regions of the substrate.

[0007] In some embodiments of the present application, the device includes an NMOS, the target region includes a first target region located below a channel region of the NMOS, and a material crystalline state of the first target region is different from a material crystalline state of other regions of the substrate.

[0008] In some embodiments of the present application, the target region further includes a second target region located on a side of the first target region away from the device, and a material crystalline state of the second target region is the same as that of the first target region.

[0009] In some embodiments of the present application, the first target area is smaller than or equal to the second target area.

[0010] In some embodiments of the present application, the device includes a PMOS, the target region includes a third target region located below a source and drain region of the PMOS, and a material crystalline state of the third target region is different from a material crystalline state of other regions.

[0011] In some embodiments of the present application, the target region further includes a fourth target region located on a side of the third target region away from the device, and a material crystal state of the fourth target region is the same as that of the third target region.

[0012] In some embodiments of the present application, the third target area is smaller than or equal to the fourth target area.

[0013] In some embodiments of the present application, the material of the target area includes polycrystalline silicon, and the material of other areas of the substrate includes single crystal silicon.

[0014] In a second aspect, the present application also provides a method for preparing a semiconductor structure, comprising providing a substrate, the substrate comprising a device region; performing heat treatment on a target region of the substrate located below the device region to change the crystal state of the substrate material in the target region; and preparing a device in the device region.

[0015] In some embodiments of the present application, the device includes an NMOS, the target region includes a first target region located below a channel region of the NMOS, and the first target region is heat treated to change a crystalline state of a material in the first target region.

[0016] In some embodiments of the present application, the target region further includes a second target region located on a side of the first target region away from the device, and the second target region is heat treated to change the crystal state of the material in the second target region.

[0017] In some embodiments of the present application, the device includes a PMOS, the target region includes a third target region located below a channel region of the PMOS, and the third target region is heat treated to change a crystalline state of a material in the third target region.

[0018] In some embodiments of the present application, the target region further includes a fourth target region located on a side of the third target region away from the device, and the fourth target region is heat treated to change the crystal state of the material in the fourth target region.

[0019] In some embodiments of the present application, the heat treatment of a target area of ​​the substrate located below the device further includes: performing the heat treatment using a high-energy beam.

[0020] In some embodiments of the present application, the target area is heat treated by focusing a laser on the target area, and the temperature of the heat treatment, the area size of the heat treatment and the position of the heat treatment are changed by changing the spot size and position of the focal point of the laser.

[0021] In a third aspect, the present application further provides a chip, which includes the semiconductor structure described in the first aspect.

[0022] In a fourth aspect, the present application further provides an electronic device, wherein the electronic device comprises the chip described in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] It should be understood by those skilled in the art that the drawings are provided for a better understanding of the present application but do not constitute any limitation on the scope of the present application.

[0024] Figure 1 It is a schematic diagram of a semiconductor device structure provided by the related technology of this application;

[0025] Figure 2 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of a semiconductor device structure provided in yet another embodiment of the present application;

[0027] Figure 4 A schematic diagram of a semiconductor device structure provided in yet another embodiment of the present application;

[0028] Figure 5 A schematic diagram of a semiconductor device structure provided in yet another embodiment of the present application;

[0029] Figure 6 A schematic flow chart of a method for preparing a semiconductor device provided in accordance with another embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the purpose, advantages and features of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present application. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0031] As used in this application, the singular forms "one", "an", and "the" include plural objects, the term "or" is generally used to include "and / or", the term "several" is generally used to include "at least one", and the term "at least two" is generally used to include "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0032] refer to Figure 1 , is a cross-sectional structural diagram of a PMOS transistor and a shallow trench isolation structure of the related art, specifically comprising: a semiconductor substrate 10, an active region 11 located in the semiconductor substrate 10; a gate structure 12 located on the surface of the active region 11, a source region 13 and a drain region 14 located on both sides of the gate structure 12, the source region 13 and the drain region 14 are respectively filled with germanium silicon materials, the source region 13, the drain region 14, the gate structure 12 and the channel region 15 located in the active region below the gate structure 12 constitute a MOS transistor, and a shallow trench isolation structure 18 located in the semiconductor substrate 10 and arranged around the MOS transistor, using the compressive stress (compressive stress) generated by the difference in the lattice constant of germanium silicon to improve the mobility of PMOS carriers. In contrast to PMOS, the channel region of NMOS can improve the mobility of carriers after receiving tensile stress, so SIC materials are usually filled in the source and drain regions of NMOS. In addition, a stress film layer can also be covered on the surface of the transistor gate, thereby transferring the stress to the channel region of the device and accumulating it in the channel region to improve the mobility of carriers in the channel region of the device.

[0033] The above-mentioned related technologies for improving carrier mobility are relatively complex and costly, and require photomasks to be set for different types of MOS, making it difficult to complete stress changes for all MOS in one process.

[0034] In order to overcome the above problems, an embodiment of the present application provides a semiconductor structure, including: a substrate, on which a device is formed; the substrate includes a target area located below the device, and the target area has a material crystalline state different from that of other areas of the substrate.

[0035] Figure 2 is a schematic diagram of a semiconductor structure of this embodiment, the semiconductor structure includes:

[0036] A substrate 1 is provided with a device 2 formed thereon. A target region 3 is provided on the substrate 1 below the device 2 . The crystalline state of the material in the target region 3 is different from the crystalline state of the material in other regions of the substrate 1 .

[0037] The change in the crystalline state of the material at the target region 3 can increase or decrease the distance between atoms in the target region 3, thereby increasing or decreasing the volume of the target region 3, and generating compressive stress or tensile stress between the target region 3 and the adjacent substrate 1 region with a different crystalline state, thereby transferring the stress to the device 2 position, generating stress in the same direction as that at the target region 3 at the device 2 position above the target region 3, and accumulating in the channel region of the device 2, thereby improving the mobility of carriers in the channel region of the device 2.

[0038] In some embodiments of the present application, Figure 3 As shown, the device 2 includes an NMOS transistor 21, the NMOS transistor 21 includes a source 211, a drain 212, a channel region 213 and a gate 224 located above the channel region 213, the target region 3 includes a first target region 31 located below the channel region 213 of the NMOS transistor 21, and the material crystal state of the first target region 31 is different from the material crystal state of other regions of the substrate 1.

[0039] In some embodiments of the present application, when the first target region 31 is located below the channel region 213 of the NMOS transistor 21, the stress of the first target region 31 on other regions of the substrate 1 is a compressive stress, that is, the stress direction is from the first target region 31 to other regions of the substrate 1. Since the compressive stress is located below the channel region 213 of the NMOS transistor 21, when the compressive stress is transmitted to the channel region 223 of the NMOS transistor 21, a compressive stress pointing to the source 211 along the channel region 213 and a compressive stress pointing to the drain 212 along the channel region 213 are generated on the channel region 223. At this time, the channel region 212 is subjected to a tensile stress pointing to both sides of the source and the drain, such as Figure 3 As shown by the arrow, it accumulates in the channel region of the NMOS transistor 21, thereby improving the mobility of carriers in the channel region 213 of the NMOS transistor 21 and improving the device performance. It can be known that when the first target region is located below the source 211 and the drain 212 of the NMOS transistor 21, the stress of the first target region 31 on other regions of the substrate 1 is tensile stress.

[0040] In some embodiments of the present application, the material of the first target region 31 is amorphous, and the area around the first target region 31 is crystalline. The process of the first target region 31 changing from crystalline to amorphous causes the volume of the first target region 31 to increase, thereby generating compressive stress on other areas of the substrate 1 caused by the first target region 31, such as Figure 3 As indicated by the arrow.

[0041] In some embodiments of the present application, the target region 3 further includes a second target region 32 located on a side of the first target region 31 away from the NMOS transistor 21, and the material crystalline state of the second target region 32 is the same as that of the first target region 31. Since the material crystalline state of the second target region 32 is the same as that of the first target region 31, the stress of the second target region 32 on other regions of the substrate 1 is also compressive stress, that is, the stress direction is from the second target region 32 to other regions of the substrate 1, such as Figure 3 As shown by the arrows, the compressive stress can also be transferred to the channel region 213 of the NMOS transistor 21 and accumulated in the channel region of the NMOS transistor 21, thereby improving the mobility of carriers in the channel region 213 of the NMOS transistor 21 and improving device performance.

[0042] In some embodiments of the present application, the size of the first target region 31 is smaller than or equal to the size of the second target region 32, that is, the volume of the first target region 31 or the vertical projection area on the substrate 1 is smaller than or equal to the volume of the second target region 32 or the vertical projection area on the substrate 1. Since the first target region 31 is closer to the channel region 213 of the NMOS transistor 21 than the second target region 32, when the size of the first target region 31 is limited and cannot exceed the size of the channel region 213, the compressive stress that can be transmitted to the channel region 213 by the first target region 31 is limited. At this time, by setting the second target region 32, since the second target region is farther away from the channel region 213, even if the second target region 32 is larger than the channel region 213, the stress will not be transmitted to the source and drain regions because the stress is farther away and attenuated more during the transmission process, and can be concentrated in the channel region 213, which can more effectively improve the carrier mobility.

[0043] In some embodiments of the present application, Figure 4 As shown, the device 2 includes a PMOS transistor 22, the PMOS transistor 22 includes a source 221, a drain 222, a channel region 223 and a gate 224 located above the channel region, and the target region 3 includes a third target region 33 located respectively below the source 221 and the drain 222 of the PMOS transistor 22, and the material crystal state of the third target region 33 is different from the material crystal state of other regions of the substrate 1.

[0044] In some embodiments of the present application, when the third target region 33 is respectively located below the source 221 and the drain 222 of the PMOS transistor 22, the stress of the third target region 33 on other regions of the substrate 1 is compressive stress, that is, the stress direction is from the third target region 33 to other regions of the substrate 1, such as Figure 4In the direction indicated by the arrow, since the compressive stress is located below the source 221 and the drain 222 of the PMOS transistor 22, when the compressive stress is transmitted to the channel region 223 of the PMOS transistor 22, a compressive stress pointing to the channel region 223 along the source 221 and a compressive stress pointing to the channel region 223 along the drain 222 are generated on the channel region 223, as shown in FIG. Figure 4 As shown by the arrow in the channel region 223, it accumulates in the channel region of the PMOS transistor 22, thereby improving the mobility of carriers in the channel region 223 of the PMOS transistor 22 and improving the device performance. It can be known that when the third target region is located below the channel region 223 of the PMOS transistor 22, the stress of the third target region 33 on other regions of the substrate 1 is tensile stress.

[0045] In some embodiments of the present application, the material of the third target region 33 is amorphous, and the area around the third target region 33 is crystalline. The process of the third target region 33 changing from crystalline to amorphous causes the volume of the third target region 33 to increase, thereby generating compressive stress on other areas of the substrate 1 by the third target region 33, such as Figure 4 As indicated by the arrow.

[0046] In some embodiments of the present application, the target region 3 further includes a fourth target region 34 located on a side of the third target region 33 away from the PMOS transistor 22, and the material crystalline state of the fourth target region 34 is the same as the material crystalline state of the third target region 33. Since the material crystalline state of the fourth target region 34 is the same as the material crystalline state of the third target region 33, the stress of the fourth target region 34 on other regions of the substrate 1 is also compressive stress, that is, the stress direction is from the fourth target region 34 to other regions of the substrate 1, such as Figure 4 As shown by the arrows, the compressive stress can also be transferred to the channel region 223 of the PMOS transistor 22 and accumulated in the channel region 223 of the PMOS transistor 22, thereby improving the mobility of carriers in the channel region 223 of the PMOS transistor 22 and improving device performance.

[0047] In some embodiments of the present application, the third target region 33 is smaller than or equal to the fourth target region 34, that is, the volume of the third target region 33 or the vertical projection area on the substrate 1 is smaller than or equal to the volume of the fourth target region 34 or the vertical projection area on the substrate 1. Since the third target region 33 is closer to the channel region 223 of the PMOS transistor 22 than the fourth target region 34, when the size of the third target region 33 is limited and cannot exceed the size of the channel region 223, the compressive stress that can be transmitted to the channel region 223 by the third target region 33 is limited. At this time, through the larger fourth target region 34, since the fourth target region 34 is farther away from the channel region 233, even if the fourth target region 34 is larger than the channel region 223, the stress will be attenuated more during the transmission process because the stress will not be transmitted to the source and drain regions, but can be concentrated in the channel region 223, which can more effectively improve the carrier mobility.

[0048] In some embodiments of the present application, the material of the target region 3 includes polycrystalline silicon, and the material of other regions of the substrate 1 includes single crystal silicon.

[0049] In some embodiments of the present application, Figure 5 As shown, the device 2 includes an NMOS transistor 21 and a PMOS transistor 22, the NMOS transistor 21 includes a source 211, a drain 212, a channel region 213 and a gate 224 located above the channel region, the target region 3 includes a first target region 31 located below the channel region 213 of the NMOS transistor 21, and the material crystalline state of the first target region 31 is different from that of other regions of the substrate 1; the PMOS transistor 22 includes a source 221, a drain 222, a channel region 223 and a gate 224 located above the channel region, the target region 3 includes a third target region 33 located below the source region 221 and the drain region 222 of the PMOS transistor 22, respectively, and the material crystalline state of the third target region 33 is different from that of other regions of the substrate 1. At this time, the material crystal state of the first target area 31 under the NMOS transistor and the second target area under the PMOS transistor can be changed in one process, thereby forming stresses in different directions in the channel area 213 of the NMOS transistor 21 and the channel area 223 of the PMOS transistor 22, respectively, and improving the carrier mobility of the NMOS and PMOS channel areas, thereby improving the performance of two different types of devices at the same time.

[0050] The present application also provides a method 100 for preparing a semiconductor structure. Figure 6 As shown, the method 100 includes:

[0051] S101, providing a substrate, the substrate including a device region.

[0052] In some embodiments of the present application, the substrate material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon-on-insulator (SOI) or single crystal silicon with an epitaxial layer, etc., and a plurality of shallow trench isolation structures are arranged on the substrate, and the area between two adjacent shallow trench isolation structures is the device area.

[0053] S102, performing heat treatment on a target area of ​​the substrate located below the device area to change the crystal state of the material of the substrate in the target area.

[0054] In some embodiments of the present application, a target area below the device area is heat treated from the back side of the substrate, that is, the other side of the substrate away from the device area, so that the crystal state of the substrate material in the target area changes, thereby avoiding affecting the device area.

[0055] S103, preparing devices in the device area.

[0056] In some embodiments of the present application, Figures 3 to 5 As shown, after the target area is heat treated, NMOS transistor 21 and / or PMOS transistor 22 can be prepared in the device area of ​​substrate 1. NMOS transistor 21 and PMOS transistor 22 can avoid affecting device performance by heat treating before device formation.

[0057] In some embodiments of the present application, reference Figure 3 or Figure 5 The device region can be used to prepare an NMOS transistor 21, the NMOS transistor 21 includes a source 211, a drain 212, a channel region 213 and a gate 224 located above the channel region, and the target region 3 includes a first target region 31 located below the channel region 213 of the NMOS transistor 21.

[0058] In some embodiments of the present application, when the first target region is located below the channel region 213 of the NMOS transistor 21, the first target region 31 is transformed into an amorphous state after heat treatment, and the area around the first target region 31 is crystalline. The process of the first target region 31 transforming from the crystalline state to the amorphous state causes the volume of the first target region 31 to increase, thereby generating a compressive stress on other regions of the substrate 1 by the first target region 31, that is, the stress direction is from the first target region 31 to other regions of the substrate 1. Since the compressive stress is located below the channel region 213 of the NMOS transistor 21, when the compressive stress is transmitted to the channel region 223 of the NMOS transistor 21, a compressive stress pointing to the source 211 along the channel region 213 and a compressive stress pointing to the drain 212 along the channel region 213 are generated on the channel region 223. At this time, the channel region 212 is subjected to a tensile stress pointing to both sides of the source and the drain, such as Figure 3As shown by the arrow, it accumulates in the channel region of the NMOS transistor 21, thereby improving the mobility of carriers in the channel region 213 of the NMOS transistor 21 and improving the device performance. It can be known that when the first target region is located below the source 211 and the drain 212 of the NMOS transistor 21, the stress of the first target region 31 on other regions of the substrate 1 is tensile stress.

[0059] In some embodiments of the present application, reference Figure 4 or Figure 5 The device area can also be used to prepare a PMOS transistor 22, the PMOS transistor 22 includes a source 221, a drain 222, a channel area 223 and a gate 224 located above the channel area, and the target area 3 includes a third target area 33 located below the source area 221 and the drain area 222 of the PMOS transistor 22 respectively.

[0060] In some embodiments of the present application, the material of the third target region 33 is amorphous, and the area around the third target region 33 is crystalline. The process of the third target region 33 changing from the crystalline state to the amorphous state causes the volume of the third target region 33 to increase, thereby causing the third target region 33 to generate compressive stress on other areas of the substrate 1. Since the compressive stress is located below the source 221 and the drain 222 of the PMOS transistor 22, when the compressive stress is transmitted to the channel region 223 of the PMOS transistor 22, a compressive stress pointing to the channel region 223 along the source 221 and a compressive stress pointing to the channel region 223 along the drain 222 are generated on the channel region 223, such as Figure 4 As shown by the arrow, it accumulates in the channel region of the PMOS transistor 22, thereby improving the mobility of carriers in the channel region 223 of the PMOS transistor 22 and improving the device performance. It can be known that when the third target region is located below the channel region 223 of the PMOS transistor 22, the stress of the third target region 33 on other regions of the substrate 1 is tensile stress.

[0061] In some embodiments of the present application, the target region 3 further includes a second target region 32 located on a side of the first target region 31 away from the device 2 , and the second target region 32 is heat treated to change the crystal state of the material of the second target region 32 .

[0062] In some embodiments of the present application, the target region 3 further includes a fourth target region 34 located on a side of the third target region 33 away from the device, and the fourth target region 34 is heat treated to change the crystal state of the material of the fourth target region 34 .

[0063] In some embodiments of the present application, thermally treating the target region 3 of the substrate 1 below the device further includes: irradiating the target region 3 with a high-energy beam.

[0064] The heat treatment in this application includes high-energy beam irradiation, which means directing the high-energy beam to act on the surface of the material to cause physical, chemical or phase structure changes, thereby achieving the purpose of modifying the surface of the material. The heat source of the high-energy beam usually includes laser, electron beam, ion beam, electric spark, etc. In this application, high-energy beam heat treatment includes any one of laser annealing, ion beam annealing or electron beam annealing. The beam spot size of the high-energy beam is small, and local heat treatment can be performed on micro-areas. At the same time, heat treatment of a larger area can also be performed by superposition scanning method, so the heat treatment area can be adjusted arbitrarily according to needs; high-energy beam heat treatment has good controllability, and the temperature and holding time of the heat treatment can be adjusted arbitrarily.

[0065] In some embodiments of the present application, laser is used to perform heat treatment on the target area 3. Laser application is relatively mature, and the heat treatment depth, heat treatment temperature, heat treatment time, etc. of the target area can be changed by adjusting the parameters such as the spot size, energy density, pulse width and wavelength of the incident laser, so that different heat treatment parameters can be used for laser annealing of different target areas to generate stresses of different magnitudes, and the stress of the device can be adjusted more controllably.

[0066] In some embodiments of the present application, the focus point of the laser is located at the target area 3, and the temperature of the heat treatment, the area size of the heat treatment and the position of the heat treatment are changed by changing the spot size and position of the laser focus.

[0067] An embodiment of the present application also provides a chip, comprising the semiconductor structure provided by the aforementioned embodiment.

[0068] For example, the chip may be a memory chip, a processor chip, an image chip, a power chip or a logic chip, or other chips, but the embodiments of the present application are not limited thereto.

[0069] An embodiment of the present application also provides an electronic device, comprising the chip provided in the aforementioned embodiment.

[0070] For example, the electronic device may be a device such as a television, a computer, a mobile phone or a tablet. The electronic device may include a circuit board and a packaging structure, and the chip may be soldered on the circuit board and protected by the packaging structure. In addition, the electronic device may also include a power supply for providing an operating voltage to the chip.

[0071] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any changes or modifications made by a person of ordinary skill in the art based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate having a device formed thereon; The substrate includes a target region located below the device, wherein the target region has a material crystalline state different from that of other regions of the substrate.

2. The semiconductor structure according to claim 1, characterized in that: The device includes an NMOS, and the target region includes a first target region located below a channel region of the NMOS, wherein a material crystal state of the first target region is different from a material crystal state of other regions of the substrate.

3. The semiconductor structure according to claim 2, characterized in that: The target region further includes a second target region located at a side of the first target region away from the NMOS, and a material crystalline state of the second target region is the same as that of the first target region.

4. The semiconductor structure according to claim 3, characterized in that: The first target area is smaller than or equal to the second target area.

5. The semiconductor structure according to claim 1, characterized in that: The device includes a PMOS, the target region includes a third target region located below a source and drain region of the PMOS, and a material crystal state of the third target region is different from a material crystal state of other regions.

6. The semiconductor structure according to claim 5, characterized in that: The target region further includes a fourth target region located at a side of the third target region away from the device, and a material crystalline state of the fourth target region is the same as that of the third target region.

7. The semiconductor structure according to claim 6, characterized in that: The third target area is smaller than or equal to the fourth target area.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that: The material of the target region includes polycrystalline silicon, and the material of other regions of the substrate includes single crystal silicon.

9. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: Providing a substrate, the substrate comprising a device region; Performing heat treatment on a target region of the substrate located below the device region to change the crystal state of the substrate material in the target region; A device is fabricated in the device region.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The device includes an NMOS, the target region includes a first target region located below a channel region of the NMOS, and the first target region is thermally treated to change a crystalline state of a material in the first target region.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: The target region further includes a second target region located at a side of the first target region away from the device, and the second target region is thermally treated to change the crystal state of the material in the second target region.

12. The method for preparing a semiconductor structure according to any one of claims 9 to 11, characterized in that: The device includes a PMOS, the target region includes a third target region located below a channel region of the PMOS, and the third target region is thermally treated to change a crystalline state of a material in the third target region.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that: The target region further includes a fourth target region located at a side of the third target region away from the device. The fourth target region is heat treated to change the crystal state of the material in the fourth target region.

14. The method for preparing a semiconductor structure according to claim 9, characterized in that: The heat treatment of the target area of ​​the substrate below the device further includes: performing the heat treatment using a high energy beam.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: The target area is focused on by laser to perform the heat treatment on the target area, and the temperature of the heat treatment, the area size of the heat treatment and the position of the heat treatment are changed by changing the spot size and position of the focus point of the laser.

16. A chip, characterized in that: Comprising the semiconductor structure as claimed in any one of claims 1 to 8.

17. An electronic device, characterized in that: Comprising the chip as claimed in claim 16.

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