Gate groove filled GaN UMOSFET and preparation method thereof

Abstract

The invention discloses a gate groove filled GaN UMOSFET (Unified Metal-Oxide-Semiconductor Field Effect Transistor) and a preparation method thereof. The UMOSFET comprises a semiconductor structure, a trench gate structure, a source electrode and a drain electrode, the trench gate structure comprises a gate electrode and a gate groove formed in the semiconductor structure, the gate electrode is at least partially arranged in the gate groove, the gate electrode is isolated from the inner wall of the gate groove through a dielectric layer, the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer continuously covers the inner wall of the gate groove, and the second dielectric layer continuously covers the inner wall of the gate groove. And the second dielectric layer is a thick-bottom dielectric medium, is filled at the bottom of the gate groove and is positioned between the gate and the first dielectric layer. According to the GaN UMOSFET, the composite dielectric layer containing the thick-bottom dielectric is arranged in the structure of the GaN UMOSFET, peak electric field concentration at the bottom of a gate groove of the device can be effectively restrained on the basis that the overall structure of the device is not changed, the overall electric field distribution trend of a drift region is not changed, and therefore the forward conduction characteristic of the device is not affected, and the reliability of the device is improved. Therefore, the breakdown characteristic of the device can be greatly enhanced.

Description

Technical Field

[0001] The present application relates to a UMOSFET device, in particular to a gate trench-filled GaN UMOSFET and a preparation method thereof, and belongs to the field of semiconductor technology. Background Art

[0002] Since the peak electric field of vertical GaN-based power devices is in the body, they mainly rely on increasing the thickness of the device's longitudinal epitaxial layer to increase the breakdown voltage. Therefore, they have the advantages of high breakdown voltage, high current density, high reliability, and natural enhancement, and are suitable for high-current and high-voltage fields such as electric vehicles and renewable energy. Compared with other structures, vertical GaN trench-gate metal-oxide-semiconductor field effect transistors (MOSFETs) have significant advantages such as natural enhancement, no need for secondary epitaxy, and theoretically high breakdown voltage. In recent years, vertical GaN trench-gate MOSFETs have made significant progress in breakdown voltage, current density, and dynamic performance. However, the electric field concentration at the bottom of the trench formed by etching causes the gate oxide dielectric to easily breakdown, resulting in a low device breakdown voltage (V BR ) is far below the theoretical value of the non-punch-through GaN pn junction and cannot reach the ideal breakdown limit, which limits the improvement of the breakdown voltage of the vertical GaN trench gate MOSFET. This is an important factor affecting the off-state performance of vertical trench gate devices and is a difficult problem that needs to be solved urgently. In response to this problem, the solutions that have been proposed are mainly: adding a p-GaN buried field shield at the bottom of the gate trench or introducing a p-type floating island (FLI) structure in the drift region. These structures mainly change the electric field distribution in the drift region by increasing the depletion region of the pn junction, thereby suppressing the peak electric field at the bottom of the trench of the device in the off state and protecting the gate dielectric from the influence of high fields, but this structure inevitably requires additional etching and secondary epitaxy, which greatly increases the complexity of the device process and the difficulty of preparation. Moreover, the introduction of the additional p-GaN structure will bring about the JFET effect, thereby increasing the on-resistance (R ON ), which is not conducive to the on-state characteristics of the device. It is usually necessary to introduce current diffusion layers (CSLs) with higher doping concentration than the drift layer to solve this problem. This also makes the device preparation process more complicated and has low feasibility. It is still in the simulation stage.

[0003] At the same time, some studies have been reported on the introduction of an additional thick bottom dielectric (TBD) layer in the gate trench. An ethylene octene copolymer (EOC) was introduced as an additional thick bottom dielectric at the bottom of the trench of the vertical GaN trench gate MOSFET, which effectively alleviated the electric field concentration at the corner of the bottom of the trench, and the breakdown voltage of the device was significantly improved. However, the introduction of the polymer requires additional curing and etching processes. In addition, the cost of high-performance polymers is high, and their effective life and reliability are difficult to guarantee. They often have problems such as poor thermal stability, weak chemical stability, easy aging or degradation, and poor material compatibility, which will affect the consistency of the device process and the overall preparation cost to a certain extent. Summary of the invention

[0004] The main purpose of the present application is to provide a gate trench filled GaN UMOSFET and a preparation method thereof, so as to overcome the deficiencies of the prior art.

[0005] In order to achieve the aforementioned invention objectives, the technical solutions adopted in this application include: One aspect of the present application provides a GaN UMOSFET with a gate groove filled, which includes a semiconductor structure, a groove gate structure, a source and a drain, wherein the groove gate structure includes a gate and a gate groove formed in the semiconductor structure, the gate is at least partially arranged in the gate groove, and the gate and the inner wall of the gate groove are isolated from each other by a dielectric layer, the dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer at least continuously covers the inner wall of the gate groove, and the second dielectric layer is at least filled in the bottom of the gate groove and is located between the gate and the first dielectric layer.

[0006] Another aspect of the present application provides a method for preparing the gate trench-filled GaN UMOSFET, comprising: Growing a fourth GaN layer, a third GaN layer, a second GaN layer and a first GaN layer in sequence on the substrate to form a semiconductor structure, wherein the first GaN layer and the fourth GaN layer are both n-type, and the second GaN layer and the third GaN layer are p-type and u-type respectively; Etching from the top surface of the semiconductor structure to a depth that at least reaches the bottom surface of the second GaN layer, thereby forming a gate groove in the semiconductor structure; Depositing a first dielectric material at least on the inner wall of the gate groove to form a first dielectric layer, and then depositing a second dielectric material at least in the gate groove to form a second dielectric layer, and making the second dielectric layer fill at least the bottom of the gate groove; Disposing a gate on the second dielectric layer, and at least partially disposing the gate in the gate groove; Furthermore, a source electrode and a drain electrode are arranged on the semiconductor structure, and the source electrode and the drain electrode are electrically contacted with the first GaN layer and the fourth GaN layer respectively.

[0007] Compared with the prior art, this application has at least the following beneficial effects: (1) By introducing a composite dielectric layer containing a thick bottom dielectric into the structure of the GaN UMOSFET, the peak electric field concentration at the bottom of the device gate trench can be effectively suppressed without changing the overall structure of the device, and the overall electric field distribution trend of the drift region can be unchanged. Therefore, the forward conduction characteristics of the device are not affected, which is beneficial to significantly enhance the breakdown characteristics of the device.

[0008] (2) By introducing a thick bottom dielectric process into the mature process of GaN UMOSFET, the peak electric field concentration at the bottom of the device gate trench is effectively suppressed without affecting the consistency of the device manufacturing process and basically without increasing the difficulty of the device manufacturing process, thereby ensuring the long-term stability and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1 is a schematic diagram of the structure of a GaN UMOSFET in a typical implementation scheme of the present application; Figure 2 This is a schematic diagram of the principle of a GaN UMOSFET preparation process in a typical implementation scheme of the present application; Figure 3 This is a schematic diagram of another GaN UMOSFET preparation process principle in a typical implementation scheme of the present application; Figure 4 This is a partial photograph of the gate trench of a GaN UMOSFET without a thick bottom dielectric in Comparative Example 1 (magnified 10,000 times); Figure 5 This is a partial photograph of a gate trench of a GaN UMOSFET with a thick bottom dielectric in Example 1 (magnified 10,000 times); Figure 6 It is a simulation diagram of the electric field distribution in the gate groove region of the device without thick bottom dielectric in comparative example 1 and the device with thick bottom dielectric in embodiment 1; Figure 7It is a schematic diagram of the electric field distribution in the Al2O3 gate dielectric at the bottom of the gate groove of the device without thick bottom dielectric in comparative example 1 and the device with thick bottom dielectric in embodiment 1. DETAILED DESCRIPTION

[0011] As mentioned above, many solutions proposed by the industry have defects in the many problems caused by the electric field concentration phenomenon at the bottom of the trench formed by etching in GaN trench gate MOSFET. For example, the introduction of p-GaN floating islands in the drift layer or the introduction of p-GaN buried layer shielding at the bottom of the gate trench are to reorganize the electric field distribution in the drift region by increasing the pn junction depletion region, so that the peak electric field at the bottom corner of the gate trench can be diffused, thereby improving the device breakdown characteristics. However, the structure of the secondary epitaxial p-GaN layer introduces an additional JFET region, which not only changes the electric field distribution in the drift region when the device is off, but also affects the current density distribution when the device is forward-conducted, increases the on-resistance, and deteriorates the forward turn-on characteristics of the device. Although the method of introducing polymers as thick bottom dielectrics deposited at the bottom of the gate trench does not affect the forward characteristics of the device, it increases the cost of device preparation. In addition, polymers have poor thermal and chemical stability and may degrade or deform under high temperature conditions. They may encounter corrosion, dissolution or chemical reactions during the manufacturing process, which affects the consistency of the device preparation process. Since polymer materials may also age or degrade over time, the long-term stability and reliability of the device are difficult to guarantee.

[0012] In view of this, the inventors of this case have proposed the technical solution of the present application after long-term research and extensive practice. The technical solution is mainly to deposit a gate dielectric layer (i.e., the aforementioned first dielectric layer) in the gate groove of the GaN UMOSFET, and then fill the gate groove with high-k dielectric materials such as silicon dioxide to form a thick bottom dielectric (i.e., the aforementioned second dielectric layer). The presence of the first dielectric layer can prevent dry etching from damaging the surface of the GaN material, thereby significantly improving the voltage resistance characteristics of the device while achieving high input characteristics of the device.

[0013] The technical solution of the present application will be described clearly and completely below. Obviously, the described implementation scheme is a part of the implementation scheme of the present application, not all the implementation schemes. Based on the implementation scheme in the present application, all other implementation schemes obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0014] Some embodiments of the present application provide a gate trench-filled GaN UMOSFET (hereinafter also referred to as a “device”), comprising: A semiconductor structure comprising a first GaN layer, a second GaN layer, a third GaN layer and a fourth GaN layer arranged in sequence along a first direction, wherein the first GaN layer and the fourth GaN layer are both n-type, and the second GaN layer and the third GaN layer are p-type and u-type, respectively; A trench gate structure, comprising a gate trench and a gate, wherein the gate is at least partially disposed in the gate trench, the notch of the gate trench is disposed at the top end surface of the semiconductor structure, the bottom of the trench is disposed at the bottom end surface of the second GaN layer or inside the third GaN layer, the top end surface of the semiconductor structure is away from the fourth GaN layer, the gate and the inner wall of the gate trench are isolated from each other by a dielectric layer, the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer at least continuously covers the inner wall of the gate trench, the second dielectric layer at least fills the bottom of the gate trench and is located between the gate and the first dielectric layer; A source electrode electrically contacting the first GaN layer; A drain electrode is electrically contacted with the fourth GaN layer.

[0015] In one embodiment, the gate groove is a U-shaped groove.

[0016] In one embodiment, the bottom of the gate trench is disposed inside the third GaN layer, that is, lower than the bottom end surface of the second GaN layer, to ensure normal opening of the device and facilitate subsequent deposition of a thick bottom dielectric.

[0017] In one embodiment, the space occupied by the first dielectric layer, the second dielectric layer, and the gate in the gate groove is 1-10% (preferably 5-10%), 1-10% (preferably 5-10%), and 80-98% (preferably 80-90%) of the volume of the gate groove, respectively. Exemplarily, the space occupied by the first dielectric layer, the second dielectric layer, and the gate in the gate groove is about 5%, 5%, and 10% of the volume of the gate groove, respectively. This design can improve the interface quality, reduce dielectric loss, improve electric field management, and give full play to the characteristics and advantages of different dielectric materials.

[0018] In one embodiment, the first dielectric layer continuously extends and covers the top surface of the semiconductor structure, plays a role in improving the charge at the dielectric interface, and acts as a passivation layer to achieve passivation treatment on the surface of the semiconductor structure.

[0019] Of course, in some cases, the top surface of the semiconductor structure may also be covered with other passivation layers.

[0020] In one embodiment, the top surface of the second dielectric layer is flush with or lower than the bottom surface of the second GaN layer, preferably lower than the bottom surface of the second GaN layer, so as to avoid affecting the forward conduction characteristics of the device.

[0021] Further, the thickness of the first dielectric layer is less than the thickness of the second dielectric layer. Preferably, the thickness of the second dielectric layer may be more than twice the thickness of the first dielectric layer. Exemplarily, the thickness of the first dielectric layer may be 1-200 nm, more preferably 10-100 nm. The thickness of the second dielectric layer may be 10-1000 nm, more preferably 50-1000 nm.

[0022] Preferably, the dielectric constant of the first dielectric material used to form the first dielectric layer is higher than the dielectric constant of the second dielectric material used to form the second dielectric layer, so that the composite dielectric layer composed of the first dielectric layer and the second dielectric layer can exert a greater capacitance advantage, while significantly improving the critical breakdown field strength at the gate dielectric, thereby more effectively improving the electric field management.

[0023] Furthermore, the material of the first dielectric layer may include but is not limited to any one or more combinations of Al2O3, Si3N4, silicon oxide, AlN or HfO2.

[0024] Furthermore, the material of the second dielectric layer may include but is not limited to silicon oxide or a curable insulating polymer (such as polyimide and other curable photoresist polymers, etc.), but inorganic dielectric materials such as silicon dioxide are more preferred because they have the advantages of excellent electrical insulation, high dielectric constant, good thermal stability, strong chemical stability, etc., and they have a mature manufacturing process, which does not affect the consistency of the device preparation process while also ensuring the long-term stability and reliability of the device.

[0025] Preferably, the first dielectric layer is an Al2O3 layer, and the second dielectric layer is a silicon dioxide layer. Under the same thickness of the composite dielectric layer, this solution can more effectively reduce the peak electric field at the bottom of the gate groove.

[0026] In one embodiment, the source electrode and the drain electrode form ohmic contacts with the first GaN layer and the fourth GaN layer respectively.

[0027] Furthermore, the materials of the gate, source and drain can be selected from but not limited to metals such as Au, Ag, Ti, Cu, or their alloys or a laminated structure of a single metal.

[0028] Some embodiments of the present application also provide a method for preparing the gate trench-filled GaN UMOSFET, which comprises: Growing a fourth GaN layer, a third GaN layer, a second GaN layer and a first GaN layer in sequence on the substrate to form a semiconductor structure, wherein the first GaN layer and the fourth GaN layer are both n-type, and the second GaN layer and the third GaN layer are p-type and u-type respectively; Etching from the top surface of the semiconductor structure to a depth that at least reaches the bottom surface of the second GaN layer, thereby forming a gate groove in the semiconductor structure; Depositing a first dielectric material at least on the inner wall of the gate groove to form a first dielectric layer, and then depositing a second dielectric material at least in the gate groove to form a second dielectric layer, and making the second dielectric layer fill at least the bottom of the gate groove; Disposing a gate on the second dielectric layer, and at least partially disposing the gate in the gate groove; Furthermore, a source electrode and a drain electrode are arranged on the semiconductor structure, and the source electrode and the drain electrode are electrically contacted with the first GaN layer and the fourth GaN layer respectively.

[0029] In one embodiment, the preparation method may include: Etching is performed from the top surface of the semiconductor structure to a depth reaching the inside of the third GaN layer, thereby forming the gate groove; A first dielectric material is deposited on the top surface of the semiconductor structure and the inner wall of the gate groove to form a continuous first dielectric layer, and then a second dielectric material is deposited on the first dielectric layer to at least fill the gate groove, and then a portion of the second dielectric material filled in the gate groove and the second dielectric material covering the top surface of the semiconductor structure are removed to form the second dielectric layer, and the top surface of the second dielectric layer is flush with or lower than the bottom surface of the second GaN layer.

[0030] Furthermore, the preparation method may specifically include: Depositing a second dielectric material on the first dielectric layer until the gate trench is filled with the second dielectric material and the top surface of the semiconductor structure is covered by the second dielectric material; At least a portion of the second dielectric material distributed outside the gate groove is removed by at least grinding and polishing, and the first dielectric layer is completely retained, and then the second dielectric material remaining on the top surface of the semiconductor structure and a portion of the second dielectric material filled in the gate groove are removed by a dry etching process, thereby forming the second dielectric layer.

[0031] In one embodiment, the preparation method may include: activating acceptor impurities in the second GaN layer by an annealing process in a protective atmosphere.

[0032] In one embodiment, the preparation method may include: forming a gate groove in the semiconductor structure by using a dry etching process, and then repairing the etching damage by using a wet etching process to obtain an ideal gate groove morphology.

[0033] In one embodiment, the preparation method may include: after etching to form the gate groove, at least performing plasma surface treatment on the inner wall of the gate groove to reduce defect states and / or dangling bonds. The plasma used may be selected from but not limited to hydrogen, oxygen, nitrogen and other plasmas.

[0034] In one embodiment, the preparation method may include: depositing a second dielectric material on the first dielectric layer by at least a chemical vapor deposition process such as MOCVD (metal organic chemical vapor deposition) or an atomic layer deposition (ALD) process to form the second dielectric layer.

[0035] In the present application, the substrate may be a homogeneous substrate (such as an intrinsic GaN substrate) or a heterogeneous substrate (such as a sapphire, Si or SiC substrate, etc.).

[0036] In the device preparation method provided in the present application, the peak electric field concentration at the bottom of the device gate groove is suppressed by introducing a thick bottom dielectric process, and no secondary epitaxial p-GaN layer is required, and the overall structure of the device is not changed, so the difficulty of the device preparation process is basically not affected. Since only a thick bottom dielectric is deposited at the bottom of the gate groove to resist the high electric field, the overall electric field distribution trend of the drift region is not changed, and therefore the forward conduction characteristics of the device are not affected.

[0037] In a typical embodiment of the present application, a structure of a GaN UMOSFET can be referred to Figure 1 , which includes a substrate 4, a semiconductor structure arranged on the substrate, a source 5, a drain 7 and a gate 6. The semiconductor structure includes a fourth GaN layer 10, a third GaN layer 3, a second GaN layer 2 and a first GaN layer 1 that are sequentially grown from bottom to top on the substrate 4. The first GaN layer 1 and the fourth GaN layer 10 are both n-type, especially heavily doped n-GaN layers. The second GaN layer 2 and the third GaN layer 3 are p-type and u-type, respectively. A gate groove 11 is formed in the gate region of the semiconductor structure, and the gate groove extends from the surface of the first GaN layer 1 to the third GaN layer 3. At the same time, a first dielectric layer 8 is formed on the top surface of the semiconductor structure, and the first dielectric layer 8 continuously covers the top surface of the semiconductor structure and the inner wall of the gate groove 11 to cooperate with the gate 6 to form a MOS structure. At the same time, a second dielectric layer 9 is also filled at the bottom of the gate groove 11, which is distributed between the portion of the gate 6 embedded in the gate groove 11 and the first dielectric layer 8 to form a thick bottom dielectric. The source electrode 5 and the drain electrode 7 form ohmic contacts with the first GaN layer 1 and the fourth GaN layer 10 respectively.

[0038] In this typical embodiment, the substrate 4 can be a GaN substrate, a sapphire substrate, a Si substrate or a SiC substrate, etc. The source 5, the drain 7 and the gate 6 can all be made of metal materials. The first dielectric layer 8 can be made of Al2O3, SiO2, silicon nitride, AlN, etc. The second dielectric layer 9 can be made of silicon oxide, etc.

[0039] This typical embodiment also provides a preparation Figure 1 The method of the device shown in the figure mainly comprises the following steps: S1. The semiconductor structure is grown on the substrate 4 by using MOCVD or other methods.

[0040] S2, etching the groove gate, including using Cl-based gas or the like to etch the semiconductor structure from the top surface of the first GaN layer 1 in the area corresponding to the gate, and etching to a specified depth, generally below the second GaN layer 2 (i.e., the p-GaN channel layer), thereby forming a gate groove 11. The etching depth can ensure the normal opening of the device. At the same time, due to the subsequent deposition of thick bottom dielectrics, the gate groove etching depth here is also required to be relatively large.

[0041] S3, performing out-of-furnace activation and wet etching and gate trench plasma treatment, including high-temperature annealing (usually around 850°C) in a protective atmosphere such as N2 to activate acceptor impurities such as Mg in the second GaN layer 2, and then using wet etching to repair the etching damage to obtain an ideal groove morphology. Surface treatment can also be performed using plasmas such as hydrogen, oxygen, and nitrogen to reduce defect states or dangling bonds.

[0042] S4. Deposition of the first dielectric layer 8: The first dielectric layer is mainly used as a gate dielectric layer, and its material can usually be one of Al2O3, SiO2, silicon nitride, AlN, etc., or a composite layer of two or more to form a MOS structure.

[0043] S5, deposition of the second dielectric layer 9 (i.e., thick bottom dielectric), including depositing at least a certain thickness of SiO2 with a high dielectric constant at the bottom of the gate groove before depositing the gate metal to form the gate 6, to resist the high electric field and suppress the peak electric field at the bottom of the groove without affecting the forward conduction characteristics of the device. The second dielectric layer 9 can be deposited by processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD) to accurately control its deposition thickness. Furthermore, the second dielectric layer 9 can be deposited in situ after the first dielectric layer 8 is deposited, thereby reducing the growth defects between the two different dielectrics.

[0044] S6. Source opening: making a gate dielectric opening in the source region to prepare for the subsequent deposition of source metal.

[0045] S7, drain deep etching: In a quasi-vertical device, it is necessary to perform deep etching to the fourth GaN layer 10 at the bottom, while for a full vertical device, this step can be omitted.

[0046] S8. Electrode metal deposition: The source and drain metals are usually Ti / Al / Ni / Au deposited on the heavily doped n-GaN layer (the first GaN layer 1 and the fourth GaN layer 10) to form an ohmic contact, and finally the gate metal is deposited.

[0047] In the above-mentioned preparation method provided in this typical embodiment, the preparation process of the second dielectric layer 9 can be carried out by Figure 2 , Figure 3 The two schemes shown are implemented.

[0048] For details, please refer to Figure 2 In one of the schemes, after the deposition of the first dielectric layer 8 is completed and before the gate metal is deposited, a SiO2 material 9' can be deposited on the first dielectric layer 8 by using a plasma chemical vapor deposition (PETEOS) or other method, and the deposited SiO2 material must be thick enough to ensure that the entire gate groove is filled; then, grinding and polishing is performed by using a chemical mechanical polishing (CMP) or other method to grind the surface of the SiO2 material flat; finally, the SiO2 material is etched using a F-based gas until a certain thickness of SiO2 material remains at the bottom of the gate groove, and the top of the remaining SiO2 material should be lower than the plane where the bottom end surface of the second GaN layer 2 is located, ensuring that the normal forward turn-on characteristics of the device are not affected, thereby completing the production of the second dielectric layer 9.

[0049] See also Figure 3 In another scheme, after the deposition of the first dielectric layer 8 is completed and before the gate metal is deposited, SiO2 material 9' can be deposited on the first dielectric layer 8 by plasma chemical vapor deposition (PETEOS) or other methods, and the deposited SiO2 material must be thick enough to ensure that the entire gate groove is filled; then, selective grinding and polishing is performed by chemical mechanical polishing (CMP) or other methods until the first dielectric layer 8 is ground and stopped; finally, F-based gas is used to selectively dry or wet etch the SiO2 material until a certain thickness of SiO2 material remains at the bottom of the gate groove, and the top of the remaining SiO2 material should be lower than the plane where the bottom end surface of the second GaN layer 2 is located, ensuring that the normal forward turn-on characteristics of the device are not affected, thereby completing the production of the second dielectric layer 9.

[0050] in, Figure 3 The solution shown is to use selective CMP grinding to terminate the grinding at the first dielectric layer 8 while achieving the flattening of the second dielectric layer 9, and then to achieve partial filling of the gate groove by dry or wet selective etching. Figure 2The scheme shown, Figure 3 The scheme shown causes less etching damage to the gate trench.

[0051] In the above typical implementation scheme of the present application, it is preferred to use plasma treatment in combination with ALD to deposit a gate dielectric layer such as aluminum oxide to form a low interface state protection layer (first dielectric layer 8), and deposit silicon dioxide to completely fill the trench gate, and then use CMP grinding to grind the surface silicon oxide layer flat, or use selective CMP grinding to form a plane between the surface of the first dielectric layer 8 and the silicon oxide in the gate trench, and then use dry or wet selective etching to achieve local filling inside the gate trench. The oxide filling process will not affect the GaN channel interface, and a high-quality gate dielectric layer and a thick bottom dielectric (second dielectric layer 9) can be achieved at the same time, which can not only achieve high input characteristics of the device, but also improve the withstand voltage characteristics of the device.

[0052] The following further explains the technical solution of the present application in conjunction with the accompanying drawings and several preferred embodiments, but the experimental conditions and setting parameters therein should not be regarded as limiting the basic technical solution of the present application. And the protection scope of the present application is not limited to the following embodiments.

[0053] Example 1 The structure of a GaN UMOSFET provided in this embodiment is as follows Figure 1 A method for preparing the device comprises the following steps: S1. A fourth GaN layer with a thickness of about 1000 nm, a third GaN layer with a thickness of about 4000 nm, a second GaN layer with a thickness of about 500 nm, and a first GaN layer with a thickness of about 200 nm are sequentially grown on a sapphire substrate using an MOCVD process, thereby forming a semiconductor structure. The first GaN layer and the fourth GaN layer are both heavily doped n-type GaN layers with a doping concentration of about 2.5e18, the third GaN layer is an intrinsic GaN layer, and the second GaN layer is a p-type GaN layer with a doping concentration of about 3e19.

[0054] S2. Use Cl-based gas to vertically etch downward from the gate region on the surface of the first GaN layer 1 to a depth of about 1200-1500 nm to form a gate groove in the semiconductor structure.

[0055] S3, the device structure obtained in step S2 is subjected to high temperature annealing in a N2 atmosphere, the annealing temperature is about 850°C, and the annealing time is about 20-30 minutes. Then it is cooled to room temperature, and then the device structure is wet-etched with a tetramethylammonium hydroxide solution at room temperature for about 120 minutes.

[0056] S4, using an ALD process to deposit aluminum oxide with a thickness of about 50 nm on the top surface of the device structure processed in step S3 and the inner wall of the gate groove to form a first dielectric layer.

[0057] S5. Deposit silicon oxide on the top surface and gate groove of the device structure after processing in step S4 by PETEOS process until the gate groove is filled with silicon oxide and the thickness of the silicon oxide layer on the top surface of the device structure is about 2000nm. Then grind and polish the silicon oxide layer by CMP process to flatten the surface of the silicon oxide layer, and finally etch SiO2 by F-based gas until the thickness of the silicon oxide remaining in the gate groove is about 500nm, forming a second dielectric layer. The space occupied by the first dielectric layer, the second dielectric layer and the gate is about 5%, 5% and 10% of the volume of the gate groove, respectively.

[0058] S6. Processing a window in the source region of the first dielectric layer to prepare for the subsequent deposition of source metal.

[0059] S7, using a Cl-based gas to perform mesa etching on the semiconductor structure until the fourth GaN layer is exposed.

[0060] S8. Use metal evaporation and metal stripping processes to deposit source metal and drain metal Ti / Al / Ni / Au (thickness of about 20 / 130 / 50 / 150 nm) on the first GaN layer and the fourth GaN layer respectively to form ohmic contacts, and finally deposit gate metal Ti / Au (thickness of about 20 / 120 nm) to form source, drain and gate respectively.

[0061] Comparative Example 1 The method for preparing a GaN UMOSFET provided in this comparative example is substantially the same as that in Example 1, except that step S5 is omitted.

[0062] Please refer to 4. Figure 5 Partial photographs of the gate trench of the GaN UMOSFET without a thick bottom dielectric in Comparative Example 1 and partial photographs of the gate trench of the GaN UMOSFET with a thick bottom dielectric in Example 1 are shown respectively.

[0063] The off-state characteristics of the two devices were simulated and tested, and the electric field distribution under the same drain voltage was as follows: Figure 6 , Figure 7 As shown, the peak electric field at the bottom of the gate groove of the device with the SiO2 thick bottom dielectric, i.e., the device of Example 1, is effectively reduced from 5.63 MV / cm to 3.54 MV / cm. This confirms that the introduction of the thick bottom dielectric can effectively suppress the peak electric field concentration phenomenon at the bottom of the gate groove, thereby helping to enhance the breakdown characteristics of the device.

[0064] Comparative Example 2 The preparation method of a GaN UMOSFET provided in this comparative example is basically the same as that in Example 1, except that: ① Step S4 is omitted.

[0065] ② In step S5, the PETEOS process is first used to deposit silicon oxide on the top surface and gate groove of the device structure after the treatment in step S4, until the gate groove is filled with silicon oxide, and the thickness of the silicon oxide layer on the top surface of the device structure is about 2000nm. Then the silicon oxide layer is ground and polished by the CMP process to flatten the surface of the silicon oxide layer until the thickness of the silicon oxide layer remaining on the top surface of the device structure is about 50nm. After that, a graphic mask is defined on the area of ​​the silicon oxide layer above the gate groove by photolithography, and then SiO2 is etched by F-based gas until the thickness of the silicon oxide remaining at the bottom of the gate groove is about 500nm, and the thickness of the silicon oxide layer retained on the side wall of the gate groove is about 50nm. The overall time consumption of step S5 is more than 3 times the total time required for steps S4 and S5 in Example 1, and the cost is more than 5 times higher.

[0066] The peak electric field at the bottom of the gate trench of the device of this comparative example is about 4.73 MV / cm.

[0067] Example 2 The structure of a GaN UMOSFET provided in this embodiment is substantially the same as that of Embodiment 1, except that the material of the second dielectric layer is replaced with polyimide. The peak electric field at the bottom of the gate trench of the device in this embodiment is about 3.89 MV / cm.

[0068] It should be understood that the technical solution of the present application is not limited to the above-mentioned specific implementation cases. Any technical deformation made according to the technical solution of the present application without departing from the purpose of the present application and the scope of protection of the claims shall fall within the scope of protection of the present application.

Claims

1. A gate trench filled GaN UMOSFET, characterized in that: include: A semiconductor structure, comprising a first GaN layer (1), a second GaN layer (2), a third GaN layer (3) and a fourth GaN layer (10) arranged in sequence along a first direction, wherein the first GaN layer (1) and the fourth GaN layer (10) are both n-type, and the second GaN layer (2) and the third GaN layer (3) are p-type and u-type respectively; A groove gate structure, comprising a gate groove (11) and a gate (6), wherein the gate (6) is at least partially arranged in the gate groove (11), the groove opening of the gate groove (11) is arranged at the top surface of the semiconductor structure, the groove bottom is arranged at the bottom end surface of the second GaN layer (2) or inside the third GaN layer (3), the top surface of the semiconductor structure is far away from the fourth GaN layer (10), the gate (6) and the inner wall of the gate groove (11) are isolated from each other by a dielectric layer, the dielectric layer comprises a first dielectric layer (8) and a second dielectric layer (9), the first dielectric layer (8) at least continuously covers the inner wall of the gate groove, and the second dielectric layer (9) at least fills the bottom of the gate groove (11) and is located between the gate (6) and the first dielectric layer (8); A source electrode (5) which is in electrical contact with the first GaN layer (1); A drain electrode (7) is in electrical contact with the fourth GaN layer (10).

2. The gate trench-filled GaN UMOSFET according to claim 1, characterized in that: The gate groove (11) is a U-shaped groove; and / or the bottom of the gate groove (11) is arranged inside the third GaN layer (3).

3. The gate trench-filled GaN UMOSFET according to claim 1, characterized in that: The spaces occupied by the first dielectric layer, the second dielectric layer and the gate in the gate groove (11) are 1-10%, 1-10% and 80-98% of the volume of the gate groove respectively; and / or the first dielectric layer (8) continuously extends and covers the top surface of the semiconductor structure; and / or the top surface of the second dielectric layer (9) is flush with or lower than the bottom surface of the second GaN layer (2); and / or the thickness of the second dielectric layer (9) is greater than that of the first dielectric layer (8).

4. The gate trench-filled GaN UMOSFET according to claim 1, characterized in that: The thickness of the first dielectric layer (8) is 1-200 nm; and / or the material of the first dielectric layer (8) is any one or more of Al2O3, Si3N4, silicon oxide, AlN or HfO2; and / or the thickness of the second dielectric layer (9) is 10-1000 nm; and / or the material of the second dielectric layer (9) includes silicon oxide or a curable insulating polymer.

5. The gate trench-filled GaN UMOSFET according to claim 1, characterized in that: The material of the gate electrode (6) includes metal; and / or the source electrode (5) and the drain electrode (7) form ohmic contacts with the first GaN layer (1) and the fourth GaN layer (10), respectively.

6. A method for preparing a GaN UMOSFET with gate trench filling according to any one of claims 1 to 5, characterized in that: include: A fourth GaN layer (10), a third GaN layer (3), a second GaN layer (2) and a first GaN layer (1) are sequentially grown on a substrate to form a semiconductor structure, wherein the first GaN layer (1) and the fourth GaN layer (10) are both n-type, and the second GaN layer (2) and the third GaN layer (3) are p-type and u-type, respectively; Etching is performed from the top surface of the semiconductor structure, with the etching depth reaching at least the bottom surface of the second GaN layer (2), thereby forming a gate groove (11) in the semiconductor structure; A first dielectric material is deposited at least on the inner wall of the gate groove to form a first dielectric layer (8), and then a second dielectric material is deposited at least in the gate groove to form a second dielectric layer (9), and the second dielectric layer (9) is filled at least at the bottom of the gate groove (11); A gate electrode (6) is arranged on the second dielectric layer (9), and the gate electrode (6) is at least partially arranged in the gate groove (11); Furthermore, a source electrode (5) and a drain electrode (7) are arranged on the semiconductor structure, and the source electrode (5) and the drain electrode (7) are electrically contacted with the first GaN layer (1) and the fourth GaN layer (10), respectively.

7. The preparation method according to claim 6, characterized in that: Specifically include: Etching is performed from the top surface of the semiconductor structure to a depth reaching the inside of the third GaN layer (3), thereby forming the gate groove (11); A first dielectric material is deposited on the top surface of the semiconductor structure and the inner wall of the gate groove (11) to form a continuous first dielectric layer (8), and then a second dielectric material is deposited on the first dielectric layer to at least fill the gate groove (11), and then a portion of the second dielectric material filled in the gate groove (11) and the second dielectric material covering the top surface of the semiconductor structure are removed to form the second dielectric layer (9), wherein the top surface of the second dielectric layer (9) is flush with or lower than the bottom surface of the second GaN layer (2).

8. The preparation method according to claim 7, characterized in that: Specifically include: Depositing a second dielectric material on the first dielectric layer until the gate trench (11) is filled with the second dielectric material and the top surface of the semiconductor structure is covered with the second dielectric material; At least a portion of the second dielectric material distributed outside the gate groove (11) is removed by at least grinding and polishing, and the first dielectric layer (8) is completely retained, and then the second dielectric material remaining on the top surface of the semiconductor structure and a portion of the second dielectric material filled in the gate groove (11) are removed by a dry etching process, thereby forming the second dielectric layer (9).

9. The preparation method according to claim 6, characterized in that: Specifically include: activating the acceptor impurities in the second GaN layer (2) by an annealing process in a protective atmosphere; and / or, using a dry etching process to form a gate groove (11) in the semiconductor structure, and then using a wet etching process to repair etching damage; And / or, after etching to form the gate groove (11), at least the inner wall of the gate groove (11) is subjected to plasma surface treatment to reduce defect states and / or dangling bonds.

10. The preparation method according to claim, characterized in that: Specifically include: The second dielectric material is deposited on the first dielectric layer (8) at least by chemical vapor deposition or atomic layer deposition process to form the second dielectric layer (9).

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