Semiconductor structure, manufacturing method thereof and memory device

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory device. The semiconductor structure comprises a substrate; the well region is located in the substrate; the threshold voltage doped region is positioned above the well region; the lightly doped regions are located on the two sides of the threshold voltage doped region; the source electrode region and the drain electrode region are located on the two sides of the lightly doped region respectively; the halo ring region is located between the source region and the threshold voltage doped region and between the drain region and the threshold voltage doped region; the gate structure is located on the surface of the threshold voltage doped region; wherein the conduction type of the threshold voltage doped region is different from that of the well region, the doping concentration of the lightly doped region is 8 * 10 < 19 >-9 * 10 < 19 > / cm < 3 >, and the doping concentration of the halo region is 5 * 10 < 18 >-6 * 10 < 18 > / cm < 3 >.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a manufacturing method thereof, and a memory device. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the size of integrated circuit devices has been continuously miniaturized. While bringing performance improvement and power consumption reduction, the device reliability problem caused by miniaturization has become increasingly serious. Among them, the device mismatch problem seriously affects the realization of circuit functions. Device (for example, MOS transistor) mismatch usually refers to the electrical characteristics (for example, threshold voltage V) of a group of devices with exactly the same design size when placed in a very close area. th ) will show certain differences. Device mismatch is often related to its intrinsic physical structure and is difficult to improve. Summary of the invention

[0003] The present application provides a semiconductor structure and a manufacturing method thereof, and a memory device that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor structure. The semiconductor structure includes: a substrate; a well region located in the substrate; a threshold voltage doped region located above the well region; a lightly doped region located on both sides of the threshold voltage doped region; a source region and a drain region located on both sides of the lightly doped region; a halo region located between the source region and the drain region and the threshold voltage doped region respectively; and a gate structure located on the surface of the threshold voltage doped region; wherein the conductivity type of the threshold voltage doped region is different from the conductivity type of the well region, and the doping concentration of the lightly doped region is 8×10 19 ~9×10 19 / cm 3 , the doping concentration of the halo region is 5×10 18 ~6×10 18 / cm 3 .

[0005] In some embodiments, the conductivity type of the well region is P-type, and the conductivity type of the threshold voltage doped region is N-type.

[0006] In some embodiments, the doping element of the threshold voltage doping region is phosphorus or arsenic.

[0007] In some embodiments, the doping element of the lightly doped region is arsenic, and the doping element of the halo region is boron.

[0008] In some embodiments, the doping concentrations of the source region and the drain region are both greater than the doping concentration of the lightly doped region.

[0009] In some embodiments, the semiconductor structure further includes an isolation structure located on both sides of the source region and the drain region away from the threshold voltage doping region.

[0010] In some embodiments, the gate structure includes a gate dielectric layer and a gate conductive layer, the gate dielectric layer is located on the surface of the threshold voltage doping region, and the gate conductive layer is located on the surface of the gate dielectric layer.

[0011] In a second aspect, some embodiments of the present application provide a memory device, which includes: at least one semiconductor structure as mentioned in any of the above embodiments.

[0012] In some embodiments, the memory device is a DRAM memory and the semiconductor structure is used to form a sense amplifier.

[0013] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor structure. The method for manufacturing the semiconductor structure includes: forming a well region in a substrate; forming a threshold voltage doping region above the well region; forming a gate structure on the surface of the threshold voltage doping region; forming a lightly doped region on both sides of the threshold voltage doping region; forming a source region and a drain region on both sides of the lightly doped region; and forming a halo region between the source region and the drain region and the threshold voltage doping region respectively; wherein the conductivity type of the threshold voltage doping region is different from the conductivity type of the well region, and the doping concentration of the lightly doped region is 8×10 19 ~9×10 19 / cm 3 , the doping concentration of the halo region is 5×10 18 ~6×10 18 / cm 3 .

[0014] In a fourth aspect, some embodiments of the present application provide another method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure includes: forming a well region in a substrate; forming an initial gate dielectric layer on the surface of the well region; forming an initial gate conductive layer on the surface of the initial gate dielectric layer; and etching the initial gate dielectric layer and the initial gate conductive layer to form a gate structure; wherein, after forming the initial gate dielectric layer, a threshold voltage doping region is formed above the well region.

[0015] In some embodiments, after forming the initial gate conductive layer and before etching the initial gate dielectric layer and the initial gate conductive layer to form the gate structure, a threshold voltage doping region is formed.

[0016] In some embodiments, after forming the initial gate dielectric layer, forming a threshold voltage doping region above the well region includes: implanting ions of an impurity element having a P-type conductivity type into a surface of the well region to form the threshold voltage doping region through an ion implantation process.

[0017] In some embodiments, the doping element having P-type conductivity is boron, and the ion source of the ion implantation process is boron atoms.

[0018] In some embodiments, after forming the initial gate dielectric layer, forming the threshold voltage doping region above the well region includes: implanting ions of doping elements having N-type conductivity into the surface of the well region through an ion implantation process to form the threshold voltage doping region; wherein, after etching the initial gate dielectric layer and the initial gate conductive layer to form the gate structure, the method further includes: forming a lightly doped region and a halo region on both sides of the threshold voltage doping region covered by the gate structure, wherein the halo region extends below the threshold voltage doping region, and the doping concentration of the lightly doped region is 8×10 19 ~9×10 19 / cm 3 , the doping concentration of the halo region is 5×10 18 ~6×10 18 / cm 3 .

[0019] In some embodiments, the doping element having N-type conductivity is phosphorus or arsenic.

[0020] In some embodiments, forming the well region in the substrate includes: implanting ions of a doping element having a P-type conductivity into the substrate through an ion implantation process; and annealing the well region.

[0021] In some embodiments, the material of the substrate is silicon, the material of the initial gate dielectric layer is silicon oxide, and forming the initial gate dielectric layer on the surface of the well region includes: forming a silicon oxide layer on the surface of the well region by thermal oxidation.

[0022] In some embodiments, the method further includes: forming a source region and a drain region on both sides of the threshold voltage doping region covered by the gate structure through an ion implantation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0024] Figure 1 is a schematic structural diagram of a semiconductor structure provided in an embodiment of the present application;

[0025] Figure 2 is a circuit diagram of a memory device provided in an embodiment of the present application;

[0026] Figure 3 is a flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0027] Figure 4is a flowchart of a method for manufacturing a semiconductor structure provided by another embodiment of the present application;

[0028] FIG. 5A to FIG. 5H is a schematic structural diagram of a semiconductor structure provided in an embodiment of the present application during a manufacturing process; and

[0029] FIG. 6A to FIG. 6C It is a structural schematic diagram of a semiconductor structure during the manufacturing process provided by another embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0032] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0033] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0034] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0035] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0036] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0037] Figure 1 Schematic diagram of the semiconductor structure provided by the embodiment of the present application. Figure 1 As shown, the semiconductor structure 100 includes a substrate 111. For example, the substrate 111 may be a thin sheet structure extending laterally in the x-direction and the y-direction. In some examples, the substrate 111 may be a semiconductor substrate such as silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), etc. In other examples, the substrate 111 may be a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrate, etc. In one implementation of the present application, the material of the substrate 111 may be single crystal silicon.

[0038] The semiconductor structure 100 also includes a well region 112 located in the substrate 111. In some embodiments, the well region 112 may have smaller extension dimensions in the x-direction and the y-direction than the substrate 111, and in the z-direction, the size of the well region 112 is smaller than the size of the substrate 111. For example, the well region 112 may serve as a "local substrate". In some embodiments, the well region 112 and the substrate 111 may have the same or different conductivity types, for example, the conductivity type of the well region 112 may be N-type or P-type. In one implementation of the present application, the conductivity type of the well region 112 may be P-type. For example, the doping element of the well region 112 may include boron (B).

[0039] The semiconductor structure 100 further includes a threshold voltage doping region 113 located above the well region 112. In some embodiments, the threshold voltage doping region 113 may have a smaller extension dimension in the x direction than the well region 112, and in the z direction, the dimension of the threshold voltage doping region 113 is smaller than the dimension of the well region 112. From the z direction, the threshold voltage doping region 113 may be approximately located in the center region of the well region 112. For example, the threshold voltage doping region 113 may be used to adjust the threshold voltage V of the device. thThe conductivity type of the threshold voltage doping region 113 is different from the conductivity type of the well region 112. In one implementation of the present application, when the conductivity type of the well region 112 is P-type, the conductivity type of the threshold voltage doping region 113 is N-type. For example, the doping element of the threshold voltage doping region 113 may be phosphorus (P) or arsenic (As).

[0040] The semiconductor structure 100 further includes lightly doped regions 116-1 and 116-2 located on both sides of the threshold voltage doped region 113, and a source region 114 and a drain region 115 located on both sides of the lightly doped regions 116-1 and 116-2, respectively. In some embodiments, the lightly doped regions 116-1 and 116-2 are symmetrically arranged in the x-direction relative to the threshold voltage doped region 113. In the z-direction, the size of the lightly doped regions 116-1 and 116-2 may be larger than the size of the threshold voltage doped region 113 and smaller than the size of the well region 112. In some embodiments, the source region 114 and the drain region 115 are symmetrically arranged relative to the threshold voltage doped region 113. For example, one lightly doped region 116-1 is located between the source region 114 and the threshold voltage doped region 113, and the other lightly doped region 116-2 is located between the drain region 115 and the threshold voltage doped region 113. In addition, in the z direction, the size of the source region 114 and the drain region 115 may be larger than the size of the lightly doped regions 116-1 and 116-2, and smaller than the size of the well region 112. In some embodiments, the top surfaces of the source region 114, the drain region 115, the threshold voltage doped region 113, and the lightly doped regions 116-1 and 116-2 may be substantially flush. It should be noted that Figure 1 The positions of the source region 114 and the drain region 115 are shown as examples. However, in other examples, the positions of the source region 114 and the drain region 115 may be replaced. Figure 1 The source region 114 shown may be referred to as a drain region. Figure 1 The drain region 115 shown may be referred to as a source region.

[0041] In some embodiments, the conductivity type of the source region 114, the drain region 115, and the lightly doped regions 116-1 and 116-2 may be different from the conductivity type of the well region 112. In one implementation of the present application, when the conductivity type of the well region 112 is P-type, the conductivity types of the source region 114, the drain region 115, and the lightly doped regions 116-1 and 116-2 are all N-type. For example, the doping elements of the source region 114, the drain region 115, and the lightly doped regions 116-1 and 116-2 may include phosphorus (P), arsenic (As), or antimony (Pb). More specifically, the doping elements of the source region 114, the drain region 115, and the lightly doped regions 116-1 and 116-2 may all be arsenic (As). Among them, the doping concentration of the lightly doped regions 116-1 and 116-2 is 8×10 19 ~9×10 19 / cm 3 .

[0042] In some embodiments, the doping concentrations of the source region 114 and the drain region 115 are greater than the doping concentrations of the lightly doped regions 116-1 and 116-2 to form a concentration gradient between the source region 114 and the threshold voltage doping region 113, and a concentration gradient between the drain region 115 and the threshold voltage doping region 113, thereby reducing the peak electric field near the drain region 115 and achieving the purpose of improving the hot carrier injection (HCI) effect and device reliability.

[0043] Continue to refer Figure 1 , the semiconductor structure 100 also includes halo regions 117-1 and 117-2. The halo regions 117-1 and 117-2 are located between the source region 114 and the drain region 115 and the threshold voltage doping region 113, respectively. In some embodiments, the halo regions 117-1 and 117-2 are symmetrically arranged relative to the threshold voltage doping region 113. For example, the halo region 117-1 may be located below the lightly doped region 116-1 and extend obliquely relative to the z-direction to below the threshold voltage doping region 113, while directly contacting the source region 114. For example, the halo regions 117-1 and 117-2 may reduce the lateral expansion of the source and drain depletion regions and prevent source-drain punch-through.

[0044] In some embodiments, the conductivity type of the halo regions 117-1 and 117-2 may be the same as the conductivity type of the well region 112. In one implementation of the present application, when the conductivity type of the well region 112 is P-type, the conductivity type of the halo regions 117-1 and 117-2 may also be P-type. For example, the doping elements of the halo regions 117-1 and 117-2 may include boron (B), gallium (Ga), or indium (In). More specifically, the doping element of the halo regions 117-1 and 117-2 may be boron (B). The doping concentration of the halo regions 117-1 and 117-2 is 5×10 18 ~6×10 18 / cm 3

[0045] Continue to refer Figure 1 , the semiconductor structure 100 further includes a gate structure 118 located on the surface of the threshold voltage doping region 113. In some embodiments, the gate structure 118 may include a gate dielectric layer 119 and a gate conductive layer 120 stacked in the z direction. The gate dielectric layer 119 is located on the surface of the threshold voltage doping region 113, and the gate conductive layer 120 is located on the surface of the gate dielectric layer 119. For example, the material of the gate dielectric layer 119 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2) or any other suitable insulating material. For example, the material of the gate conductive layer 120 may include one or more of aluminum (Al), copper (Gu), tungsten (W), titanium (Ti), titanium nitride (TiN), polycrystalline silicon (poly-Si) or any other suitable conductive material. In one implementation of the present application, the material of the gate dielectric layer 119 may be silicon oxide (SiO2), and the material of the gate conductive layer 120 may be polycrystalline silicon (poly-Si).

[0046] In some embodiments, the semiconductor structure 100 may further include spacers 122-1 and 122-2. The spacers 122-1 and 122-2 may be located on both sides of the gate structure 118 in the x direction and above the lightly doped regions 116-1 and 116-2. For example, the material of the spacers 122-1 and 122-2 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The sidewalls 122-1 and 122-2 may be used as a mask layer in the process of forming the lightly doped regions 116-1 and 116-2.

[0047] In some embodiments, the semiconductor structure 100 further includes an isolation structure 121. The isolation structure 121 may be located on both sides of the source region 114 and the drain region 115 away from the threshold voltage doping region 113. For example, the material of the isolation structure 121 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. Exemplarily, from the z direction, the isolation structure 121 may surround the well region 112. In addition, in some embodiments, the bottom surface of the isolation structure 121 may be substantially flush with the bottom surface of the well region 112 or have a spacing, and the present application does not impose specific restrictions on this. In some embodiments, the top surface of the isolation structure 121 is substantially flush with the top surface of the source region 114 or the drain region 115, or the top surface of the isolation structure 121 is higher than the top surface of the source region 114 or the drain region 115. For example, the isolation structure 121 may be implemented as a shallow trench isolation structure or a field oxygen isolation structure (LOCOS). The isolation structure 121 can be used to improve parasitic field effect transistors and latch-up effects.

[0048] According to the above description, in some embodiments, the well region 112, the threshold voltage doped region 113, the lightly doped regions 116-1 and 116-2, the source region 114, the drain region 115, the halo regions 117-1 and 117-2, and the gate structure 118 may constitute a transistor. For example, the transistor may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In some examples, when the conductivity type of the well region 112 is P-type, the conductivity type of the halo regions 117-1 and 117-2 is also P-type, and the conductivity type of the source region 114, the drain region 115, the lightly doped regions 116-1 and 116-2 is N-type, the transistor may be an NMOS transistor. In other examples, when the conductivity type of the well region 112 is N-type, the conductivity type of the halo regions 117-1 and 117-2 is also N-type, and the conductivity type of the source region 114, the drain region 115, and the lightly doped regions 116-1 and 116-2 are P-type, the transistor may be a PMOS transistor.

[0049] In some exemplary embodiments, a threshold voltage doping region having the same conductivity type as the well region is provided, and the threshold voltage of the transistor is made to meet the design requirements by adjusting the doping concentration of the threshold voltage doping region. For example, when the transistor is an NMOS transistor, boron (B) element is usually used as the doping element of the threshold voltage doping region. The inventors have found that one of the important factors leading to device mismatch is random ion fluctuations (RDF), and the strength of RDF is mainly closely related to the type of doping ions in the threshold voltage doping region. When boron (B) ions are used as doping ions, RDF is more likely to occur due to the small volume of boron (B) ions, resulting in serious device mismatch problems. In addition, ions of other doping elements (e.g., gallium (Ga) or indium (In)) with P-type conductivity have poor diffusivity after doping due to the large ion volume, and it is difficult to meet the device performance requirements.

[0050] According to the semiconductor structure provided by the embodiment of the present application, by selecting the doping element of the threshold voltage doping region with the opposite conductivity type to the well region, for example, when the conductivity type of the well region is P type, phosphorus (P) or arsenic (As) is selected as the doping element of the threshold voltage doping region. Since the volume of phosphorus (P) ions or arsenic (As) ions is larger, RDF is less likely to occur, thereby improving the device mismatch problem. In addition, by increasing the doping concentration of the lightly doped region and the halo region (that is, the doping concentration of the lightly doped region is 8×10 19 ~9×10 19 / cm 3 , the doping concentration of the halo region is 5×10 18~6×10 18 / cm 3 ) is used to compensate for the doping ion concentration of the threshold voltage doping region having the opposite conductivity type to the well region, thereby meeting the device design requirements.

[0051] An embodiment of the present application also provides a memory device. Figure 2 is a circuit diagram of a memory device provided in an embodiment of the present application. For example, the memory device may be a DRAM memory.

[0052] like Figure 2 As shown, the memory device 200 may include a plurality of memory cells 201. For example, the plurality of memory cells 201 may constitute a memory cell array. In some embodiments, each memory cell 201 may include a transistor 202 and a capacitor 203. One of the source or drain of the transistor 202 is connected to the first electrode of the capacitor 203, and the second electrode of the capacitor 203 is grounded. The other of the sources or drains of a column of transistors 202 are connected to each other and to the same bit line BL, and the gates of a row of transistors 202 are connected to each other and to the same word line WL. For example, the capacitor 203 may be used to store binary data, and the transistor 202 may be used as a switch to access the capacitor 203.

[0053] In some embodiments, one end of the bit line BL may be connected to a sense amplifier (SA) 204. For example, in a read operation, when the transistor 202 is turned on and the capacitor 203 charges the bit line BL, or the bit line BL charges the capacitor 203, a small change in voltage occurs on the bit line BL. The sense amplifier 204 compares the voltage on the bit line BL with a reference voltage provided on another separate bit line (not shown), and amplifies the voltage difference, so that the binary data is interpreted as 1 or 0, thereby reading the stored data in the memory cell 201.

[0054] In some embodiments, the sense amplifier 204 may be a differential amplifier and include a group of devices (e.g., MOS devices) placed in close proximity and designed to have exactly the same size. The inventors have found that device mismatch in the sense amplifier 204 is closely related to the sensing margin and affects the reading accuracy.

[0055] According to the memory device of the embodiment of the present application, the semiconductor structure mentioned in any of the above embodiments (for example, Figure 1 The semiconductor structure 100 shown is used in a memory device (eg, a sense amplifier), which can improve the device mismatch problem, increase the sensing margin of the DRAM memory device, and improve the reading accuracy of the DRAM memory device.

[0056] It should be noted that, in some embodiments, Figure 1 The semiconductor structure 100 shown can be applied to sense amplifiers or other peripheral circuits of other types of memory devices to improve device mismatch problems. For example, the types of memory devices may include but are not limited to NAND memory, NOR memory, ferroelectric memory, magnetic variable memory, phase change memory, and resistive variable memory.

[0057] Figure 3 is a flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application. Figure 3 As shown, a method 300 for manufacturing a semiconductor structure (hereinafter referred to as manufacturing method 300) includes the following steps. For example, the manufacturing method 300 can be used to form Figure 1 A semiconductor structure 100 is shown.

[0058] S310, forming a well region in the substrate.

[0059] S320, forming a threshold voltage doping region above the well region.

[0060] S330, forming a gate structure on the surface of the threshold voltage doping region.

[0061] S340, forming lightly doped regions on both sides of the threshold voltage doped region.

[0062] S350, forming a source region and a drain region on both sides of the lightly doped region respectively.

[0063] S360, forming halo regions between the source region and the drain region and the threshold voltage doping region respectively.

[0064] The conductivity type of the threshold voltage doped region is different from that of the well region, and the doping concentration of the lightly doped region is 8×10 19 ~9×10 19 / cm 3 , the doping concentration of the halo region is 5×10 18 ~6×10 18 / cm 3 .

[0065] According to the above embodiment, a method 300 for manufacturing a semiconductor structure is provided, wherein a threshold voltage doping region having a conductivity type opposite to that of the well region is formed. For example, when the conductivity type of the well region is P type, phosphorus (P) or arsenic (As) is selected as the doping element of the threshold voltage doping region. Since the volume of phosphorus (P) ions or arsenic (As) ions is large, RDF is less likely to occur, thereby improving the device mismatch problem. In addition, by increasing the doping concentration of the lightly doped region and the halo region (i.e., the doping concentration of the lightly doped region is 8×10 19 ~9×10 19 / cm 3 , the doping concentration of the halo region is 5×1018 ~6×10 18 / cm 3 ) is used to compensate for the doping ion concentration of the threshold voltage doping region having the opposite conductivity type to the well region, thereby meeting the device design requirements.

[0066] Figure 4 FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure provided by another embodiment of the present application. Figure 4 As shown, a method 400 for manufacturing a semiconductor structure (hereinafter referred to as manufacturing method 400) includes the following steps. For example, the manufacturing method 400 can be used to form Figure 1 A semiconductor structure 100 is shown.

[0067] S410, forming a well region in the substrate.

[0068] S420, forming an initial gate dielectric layer on the surface of the well region.

[0069] S430, forming an initial gate conductive layer on the surface of the initial gate dielectric layer.

[0070] S440, etching the initial gate dielectric layer and the initial gate conductive layer to form a gate structure.

[0071] After the initial gate dielectric layer is formed, a threshold voltage doping region is formed above the well region.

[0072] According to the above embodiment, a method 400 for manufacturing a semiconductor structure is provided. By arranging the step of forming a threshold voltage doping region after forming an initial gate dielectric layer, the thermal budget for forming the threshold voltage doping region can be reduced, and the probability of RDF occurrence can be reduced, thereby improving the device mismatch problem.

[0073] Combine the following FIG. 5A to FIG. 5H as well as FIG. 6A to FIG. 6C The manufacturing methods 300 and 400 are described by way of example.

[0074] FIG. 5A to FIG. 5H Schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present application during the manufacturing process. The structure of the semiconductor structure during the manufacturing process is referred to as an intermediate structure.

[0075] Figure 5A The intermediate structure 500a is shown after forming the isolation structure 521. In some embodiments, as Figure 5A As shown, first, the substrate 511 may be etched by photolithography and etching (e.g., dry etching and / or wet etching) to form an isolation trench (corresponding to the outer contour of the isolation structure 521). For example, from the z direction, the isolation trench may surround the well region 512 to be formed (refer to Figure 5BThen, an insulating material (e.g., silicon oxide (SiO2)) may be filled in the isolation trench by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form an isolation structure 521.

[0076] Figure 5B The intermediate structure 500b is shown after forming the well region 512. In some embodiments, as Figure 5B As shown, first, a photolithography process can be used to pattern the photoresist layer 523 covering the top surface of the intermediate structure 500b to expose the well region 512 and cover the area other than the well region 512. Then, using the photoresist layer 523 as a masking layer, ions of doping elements with P-type or N-type conductivity are implanted into the substrate 511 through an ion implantation process to form the well region 512. For example, the design requirements of the depth of the well region 512 (i.e., the size in the z direction) can be met by adjusting the energy of the ion implantation. In one implementation of the present application, ions of doping elements with P-type conductivity can be implanted into the substrate 511, so that the well region 512 can be called a P-well region. For example, the doping element with P-type conductivity can include boron (B). Next, the well region 512 can be annealed by heating to repair the lattice damage caused by the ion implantation.

[0077] Figure 5C The intermediate structure 500c is shown after forming the threshold voltage doping region 513 and the initial gate dielectric layer 519'. Figure 5B and Figure 5C As shown, after the well region 512 is formed, the photoresist layer 523 may be removed, and then an initial gate dielectric layer 519' may be formed on the surface of the well region 512. In some examples, the material of the substrate 511 may be silicon (Si), and an initial gate dielectric layer 519' made of silicon oxide (SiO2) may be formed on the surface of the well region 512 by an oxidation method (e.g., dry oxygen oxidation method and / or wet oxygen oxidation method) under heating conditions. In other examples, an initial gate dielectric layer 519' made of other insulating materials may be formed on the surface of the well region 512 by a nitridation method or a thin film deposition process such as CVD, PVD, ALD or any combination thereof. For example, other insulating materials may include silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), one or more of aluminum oxide (Al2O3), zirconium oxide (ZrO2), and hafnium oxide (HfO2).

[0078] In some embodiments, when the conductivity type of the doping element of the well region 512 is P-type, ions of the doping element having P-type conductivity may be implanted into the surface of the well region 512 to form a threshold voltage doping region 513. For example, the doping element having P-type conductivity may be boron (B). The ion source of the ion implantation process is boron (B) atoms. In this embodiment, compared to ion sources such as BF2, boron atoms as ion sources of the ion implantation process may have stronger penetration ability, and can increase the ion implantation energy, thereby penetrating the initial gate dielectric layer 519' to reach the surface of the well region 512.

[0079] In other embodiments, when the conductivity type of the doping element of the well region 512 is P-type, ions of the doping element with N-type conductivity may be implanted into the surface of the well region 512 to form the threshold voltage doping region 513. For example, the doping element with N-type conductivity may be phosphorus (P) or arsenic (As). In this embodiment, when the conductivity type of the well region 512 is P-type, phosphorus (P) or arsenic (As) is selected as the doping element of the threshold voltage doping region 513. Since the volume of phosphorus (P) ions or arsenic (As) ions is larger, RDF is less likely to occur, thereby improving the device mismatch problem.

[0080] In some exemplary embodiments, after forming the well region, the photoresist layer may not be removed first, but the photoresist layer may be used as a masking layer, and ions of doping elements with P-type or N-type conductivity are implanted into the surface of the well region through an ion implantation process to form a threshold voltage doping region. Next, an initial gate dielectric layer is formed on the surface of the well region. In this exemplary embodiment, the inventors have found that the strength of RDF, one of the important factors leading to device mismatch, is also closely related to the thermal budget. That is, if a threshold voltage doping region is formed before forming the initial gate dielectric layer, the ions of the doping elements in the threshold voltage doping region will undergo a heating process following the manufacturing process of forming the initial gate dielectric layer, making it easier to have RDF, which in turn leads to serious device mismatch problems.

[0081] According to the manufacturing method provided in the embodiment of the present application, compared with the above exemplary embodiments, by arranging the step of forming the threshold voltage doping region after forming the initial gate dielectric layer, the thermal budget for forming the threshold voltage doping region can be reduced, and the probability of RDF occurrence can be reduced, thereby improving the device mismatch problem.

[0082] Figure 5D The intermediate structure 500d is shown after forming the initial gate conductive layer 520'. Figure 5DAs shown, the initial gate conductive layer 520' may be formed on the surface of the initial gate dielectric layer 519' by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. For example, when the material of the initial gate conductive layer 520' is polycrystalline silicon (poly-Si), silane (SiH4) may be decomposed under heating conditions to deposit undoped polycrystalline silicon (poly-Si) on the surface of the initial gate dielectric layer 519'.

[0083] Figure 5E The intermediate structure 500e is shown after forming the gate structure 518. In some embodiments, as Figure 5D and Figure 5E As shown, an etching process (e.g., dry etching and / or wet etching) may be used to etch the initial gate conductive layer 520' and the initial gate dielectric layer 519', thereby forming a gate structure 518. In the process of forming the gate structure 518, a portion of the initial gate conductive layer 520' and the initial gate dielectric layer 519' may be removed, and the remaining initial gate conductive layer 520' and the initial gate dielectric layer 519' are respectively used as the gate conductive layer 520 and the gate dielectric layer 519 (i.e., the gate structure 518).

[0084] Fig. 5F The intermediate structure 500f is shown after forming the lightly doped regions 516-1 and 516-2 and the halo regions 517-1 and 517-2. Fig. 5F As shown, first, the gate structure 518 can be used as a masking layer, and ions of doping elements with P-type or N-type conductivity type are implanted into the threshold voltage doping region 513 and the well region 512 on both sides of the gate structure 518 through an ion implantation process to form lightly doped regions 516-1 and 516-2. For example, the depth of the lightly doped regions 516-1 and 516-2 (i.e., the size in the z direction) can be greater than the depth of the threshold voltage doping region 513 (i.e., the size in the z direction). Then, the gate structure 518 can be further used as a masking layer to form halo regions 517-1 and 517-2 through an ion implantation process. During the halo ion implantation process, the direction of ion implantation is not perpendicular to the thickness direction of the substrate 511 (i.e., the z direction), but there is a certain angle, and the intermediate structure 500f is rotated at the same time, so as to form halo regions 517-1 and 517-2 similar to pockets. The ion implantation depth of the halo regions 517 - 1 and 517 - 2 is deeper than that of the lightly doped regions 516 - 1 and 516 - 2 , so that the halo regions 517 - 1 and 517 - 2 extend to below the threshold voltage doping region 513 .

[0085] In some embodiments, as described above, when the conductivity type of the doping element of the well region 512 is P-type and the conductivity type of the doping element of the threshold voltage doping region 513 is N-type, in the process of forming the lightly doped regions 516-1 and 516-2 and the halo regions 517-1 and 517-2, the doping concentrations of the lightly doped regions 516-1 and 516-2 and the halo regions 517-1 and 517-2 may be increased (i.e., the doping concentrations of the lightly doped regions 516-1 and 516-2 are 8×10 19 ~9×10 19 / cm 3 , the doping concentration of halo regions 517-1 and 517-2 is 5×10 18 ~6×10 18 / cm 3 ) is used to compensate for the doping ion concentration of the threshold voltage doping region 513 having the opposite conductivity type to the well region 512, thereby meeting the device design requirements.

[0086] Figure 5G The intermediate structure 500g is shown after forming the sidewalls 522-1 and 522-2. Fig. 5F and Figure 5G As shown, first, a dielectric layer (not shown) can be formed on the top surface of the intermediate structure 500f by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. Then, an etching process (e.g., dry etching) can be used to remove the portion of the dielectric layer covering the top surface of the gate structure 518, the portion covering the top surface of the lightly doped regions 516-1 and 516-2 and away from the gate structure 518 in the x direction, and the portion covering the isolation structure 521, so that the remaining dielectric layer covers the top surface of the lightly doped regions 516-1 and 516-2 and is located on both sides of the gate structure 518 in the x direction. That is, the remaining dielectric layer serves as the sidewalls 522-1 and 522-2, and is used to subsequently form the source region 514 and the drain region 515 (see Figure 5H ) process as a masking layer for the lightly doped regions 516 - 1 and 516 - 2.

[0087] Figure 5H 5 shows the semiconductor structure 500 after forming the source region 514 and the drain region 515. In some embodiments, as Figure 5HAs shown, ions of doping elements with P-type or N-type conductivity can be implanted into both sides of the threshold voltage doping region 513 covered by the gate structure 518 and the sidewalls 522-1 and 522-2 through an ion implantation process to form a source region 514 and a drain region 515, respectively. The ion implantation depth of the source region 514 and the drain region 515 is deeper than that of the lightly doped regions 516-1 and 516-2. For example, when the material of the gate conductive layer 520 in the gate structure 518 is undoped polysilicon (poly-Si), the gate conductive layer 520 can be doped during the process of forming the source region 514 and the drain region 515 to improve the conductive performance.

[0088] FIG. 6A to FIG. 6C FIG. 1 is a schematic diagram of a semiconductor structure in a manufacturing process provided by another embodiment of the present invention. FIG. 5A to FIG. 5H The same contents in the illustrated embodiments will not be repeated in this application.

[0089] Fig. 6A The intermediate structure 600a is shown after forming the initial gate dielectric layer 619' and the initial gate conductive layer 620'. Figure 5B and Fig. 6A As shown, after the well region 612 is formed, an initial gate dielectric layer 619' is formed on the surface of the well region 612. In some examples, the material of the substrate 611 may be silicon (Si), and an initial gate dielectric layer 619' made of silicon oxide (SiO2) may be formed on the surface of the well region 612 by an oxidation method (e.g., dry oxygen oxidation method and / or wet oxygen oxidation method) under heating conditions. In other examples, an initial gate dielectric layer 619' made of other insulating materials may be formed on the surface of the well region 612 by a nitridation method or a thin film deposition process such as CVD, PVD, ALD or any combination thereof. For example, other insulating materials may include silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), one or more of aluminum oxide (Al2O3), zirconium oxide (ZrO2), and hafnium oxide (HfO2).

[0090] Furthermore, the initial gate conductive layer 620' may be formed on the surface of the initial gate dielectric layer 619' by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. For example, when the material of the initial gate conductive layer 620' is polycrystalline silicon (poly-Si), silane (SiH4) may be decomposed under heating conditions to deposit undoped polycrystalline silicon (poly-Si) on the surface of the initial gate dielectric layer 619'.

[0091] Figure 6BThe intermediate structure 600b is shown after forming the initial gate dielectric layer 619' and the initial gate conductive layer 620'. Figure 6B As shown, in the case where the conductivity type of the doping element of the well region 612 is P-type, ions of the doping element with P-type conductivity type can be implanted into the surface of the well region 612 to form a threshold voltage doping region 613. For example, the doping element with P-type conductivity type can be boron (B). Among them, the ion source of the ion implantation process is boron (B) atoms. In this embodiment, compared with ion sources such as BF2, boron atoms as ion sources of the ion implantation process can have stronger penetration ability, and can increase the ion implantation energy, thereby penetrating the initial conductive layer 620' and the initial gate dielectric layer 619' to reach the surface of the well region 612.

[0092] In other embodiments, when the conductivity type of the doping element of the well region 612 is P-type, ions of the doping element with N-type conductivity may be implanted into the surface of the well region 612 to form the threshold voltage doping region 613. For example, the doping element with N-type conductivity may be phosphorus (P) or arsenic (As). In this embodiment, when the conductivity type of the well region 612 is P-type, phosphorus (P) or arsenic (As) is selected as the doping element of the threshold voltage doping region 613. Since the volume of phosphorus (P) ions or arsenic (As) ions is larger, RDF is less likely to occur, thereby improving the device mismatch problem.

[0093] Figure 6C The intermediate structure 600c is shown after forming the gate structure 618. In some embodiments, as Figure 6B and Figure 6C As shown, an etching process (e.g., dry etching and / or wet etching) may be used to etch the initial gate conductive layer 620' and the initial gate dielectric layer 619', thereby forming a gate structure 618. In the process of forming the gate structure 618, a portion of the initial gate conductive layer 620' and the initial gate dielectric layer 619' may be removed, and the remaining initial gate conductive layer 620' and the initial gate dielectric layer 619' are respectively used as the gate conductive layer 620 and the gate dielectric layer 619 (i.e., the gate structure 618).

[0094] In some embodiments, the following may be used: FIG. 5F to FIG. 5H The method shown is used to form a lightly doped region, a halo region, a sidewall, a source region, and a drain region, thereby forming a semiconductor structure.

[0095] According to the manufacturing method provided in the embodiment of the present application, by arranging the step of forming the threshold voltage doping region after forming the initial gate conductive layer, not only can the thermal budget for forming the threshold voltage doping region be reduced, the probability of RDF occurrence can be reduced, thereby improving the device mismatch problem, but also the initial gate conductive layer can be used as an ion implantation barrier layer for forming the threshold voltage doping region, thereby reducing the difficulty of energy control of ion implantation. On the other hand, arranging the step of forming the threshold voltage doping region before etching the initial gate conductive layer and the initial gate dielectric layer to form the gate structure can avoid that after the gate structure is formed, the region not covered by the gate structure has a different thickness from the region covered by the gate structure, resulting in different implantation depths of the threshold voltage doping region, thereby affecting the implantation depths of the subsequently formed lightly doped regions, halo regions, source regions, and drain regions.

[0096] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A well region located in the substrate; a threshold voltage doped region, located above the well region; A lightly doped region, located on both sides of the threshold voltage doped region; A source region and a drain region, respectively located on two sides of the lightly doped region; A halo region, located between the source region and the drain region and the threshold voltage doping region respectively; as well as A gate structure, located on the surface of the threshold voltage doping region; The conductivity type of the threshold voltage doped region is different from the conductivity type of the well region, and the doping concentration of the lightly doped region is 8×10 19 ~9×10 19 / cm 3 The doping concentration of the halo region is 5×10 18 ~6×10 18 / cm 3 .

2. The semiconductor structure according to claim 1, wherein: The conductivity type of the well region is P type, and the conductivity type of the threshold voltage doping region is N type.

3. The semiconductor structure according to claim 2, wherein: The doping element of the threshold voltage doping region is phosphorus or arsenic.

4. The semiconductor structure according to claim 2, wherein: The doping element of the lightly doped region is arsenic, and the doping element of the halo region is boron.

5. The semiconductor structure according to claim 1, wherein: The doping concentrations of the source region and the drain region are both greater than the doping concentration of the lightly doped region.

6. The semiconductor structure according to claim 1, wherein: It also includes an isolation structure located on both sides of the source region and the drain region away from the threshold voltage doping region.

7. The semiconductor structure according to claim 1, wherein: The gate structure comprises a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer is located on the surface of the threshold voltage doping region, and the gate conductive layer is located on the surface of the gate dielectric layer.

8. A memory device, characterized in that: include: At least one semiconductor structure as claimed in any one of claims 1 to 7.

9. The memory device according to claim 8, wherein: The memory device is a DRAM memory, and the semiconductor structure is used to form a sense amplifier.

10. A method for manufacturing a semiconductor structure, characterized in that: include: forming a well region in the substrate; forming a threshold voltage doping region above the well region; forming a gate structure on a surface of the threshold voltage doping region; forming lightly doped regions on both sides of the threshold voltage doped region; forming a source region and a drain region on both sides of the lightly doped region respectively; as well as forming a halo region between the source region and the drain region and the threshold voltage doping region respectively; The conductivity type of the threshold voltage doped region is different from the conductivity type of the well region, and the doping concentration of the lightly doped region is 8×10 19 ~9×10 19 / cm 3 The doping concentration of the halo region is 5×10 18 ~6×10 18 / cm 3 .

11. A method for manufacturing a semiconductor structure, characterized in that: include: forming a well region in the substrate; forming an initial gate dielectric layer on the surface of the well region; forming an initial gate conductive layer on a surface of the initial gate dielectric layer; as well as Etching the initial gate dielectric layer and the initial gate conductive layer to form a gate structure; After the initial gate dielectric layer is formed, a threshold voltage doping region is formed above the well region.

12. The manufacturing method according to claim 11, wherein: The threshold voltage doping region is formed after the initial gate conductive layer is formed and before the initial gate dielectric layer and the initial gate conductive layer are etched to form the gate structure.

13. The manufacturing method according to claim 11, wherein: After forming the initial gate dielectric layer, forming a threshold voltage doping region above the well region comprises: Through an ion implantation process, ions of a doping element having a P-type conductivity type are implanted into the surface of the well region to form the threshold voltage doping region.

14. The manufacturing method according to claim 13, wherein: The doping element with P-type conductivity is boron, and the ion source of the ion implantation process is boron atoms.

15. The manufacturing method according to claim 11, wherein: After forming the initial gate dielectric layer, forming a threshold voltage doping region above the well region comprises: Implanting ions of an N-type conductive doping element into the surface of the well region to form the threshold voltage doping region through an ion implantation process; After etching the initial gate dielectric layer and the initial gate conductive layer to form a gate structure, the method further includes: A lightly doped region and a halo region are formed on both sides of the threshold voltage doped region covered by the gate structure, wherein the halo region extends below the threshold voltage doped region, and the doping concentration of the lightly doped region is 8×10 19 ~9×10 19 / cm 3 The doping concentration of the halo region is 5×10 18 ~6×10 18 / cm 3 .

16. The manufacturing method according to claim 15, wherein: The doping element with N-type conductivity is phosphorus or arsenic.

17. The manufacturing method according to claim 11, wherein: Forming a well region in a substrate includes: Implanting ions of a doping element having a P-type conductivity into the substrate through an ion implantation process; and The well region is subjected to an annealing process.

18. The manufacturing method according to claim 11, wherein: The material of the substrate is silicon, the material of the initial gate dielectric layer is silicon oxide, and forming the initial gate dielectric layer on the surface of the well region comprises: A silicon oxide layer is formed on the surface of the well region by a thermal oxidation method.

19. The manufacturing method according to claim 11, wherein: Also includes: Through an ion implantation process, a source region and a drain region are formed on both sides of the threshold voltage doping region covered by the gate structure.

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