Double-groove super junction structure and manufacturing method thereof

Abstract

The invention discloses a double-groove super junction structure and a manufacturing method thereof, the double-groove super junction structure comprises a plurality of MOS cells which are connected in parallel, and each MOS cell comprises a drain electrode, an upper metal source electrode, a grid electrode, a semiconductor epitaxial layer, a substrate layer, a P well layer and an N well layer; a groove is formed between adjacent MOS cells and in the middle of the heavily doped P well layer I through etching, an oxide layer is deposited at the bottom of the groove, a side metal source electrode is arranged on the surface of the oxide layer, and the top of the side metal source electrode is in contact with the upper metal source electrode; the side surface of the side metal source is in ohmic contact with the N well layer, the lightly doped P well layer I and the heavily doped P well layer I; the grid electrode is a longitudinal groove type grid electrode and is arranged between the two N well layers of the single MOS cell, and the grid electrode is connected with the N well layers, the first lightly-doped P well layer and the diffusion layer in an isolated mode through a grid oxide layer. According to the invention, the injection depth of the heavily doped P well layer I is increased through the groove, and the (11-20) surface channel is adopted, so that the interface state density is greatly reduced, and the overall size of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a double-trench super junction structure and a manufacturing method thereof. Background Art

[0002] SiC MOSFET devices have the significant advantages of high frequency and low loss, and are widely used in electric vehicles, photovoltaic inverters, charging piles and other fields. With the gradual development of SiC MOSFET devices, the voltage requirements of the devices at the application end are gradually increasing. For SiC MOSFET, higher voltage resistance means thicker epitaxial layer, and the increase of epitaxial layer means a sharp increase in the on-resistance of the device. For devices with the same on-resistance, the epitaxial thickness and device area of ​​high-voltage devices will be much higher than those of low-voltage devices. The superjunction structure solves the above problems due to its special structure.

[0003] However, the manufacture of super junction structures usually requires very deep P+ implantation to improve voltage resistance and reduce on-resistance. The implantation depth of P+ ions is limited by the implantation capacity of the implantation machine. Currently, implantation machines in the industry can usually only achieve an implantation depth of 2 to 3 μm. If you want to manufacture a heavily doped P well layer with a thickness of more than 5 μm, it is actually impossible. Even with more advanced implantation machines, silicon carbide substrates cannot withstand such a high concentration of impurity ions, resulting in material damage. Limited by process manufacturing, super junction structures are greatly limited in actual device production and cannot be widely used.

[0004] In addition, conventional SiC MOSFET devices still have problems such as high planar channel interface state and low planar mobility, which need to be improved. Summary of the invention

[0005] The purpose of the present invention is to provide a double-trench super junction structure and a manufacturing method thereof, which not only solves the problem in the prior art that P+ injection is limited by the injection capacity of the implanter, improves the feasibility of the process, but also transforms the source ohmic contact from horizontal to vertical, transforms the planar channel into a vertical channel, reduces the cell size, and improves the device performance.

[0006] The technical solution adopted by the present invention is:

[0007] A double-trench super junction structure, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain, an upper metal source, a gate, a semiconductor epitaxial layer, and a substrate layer; the semiconductor epitaxial layer is located on the surface of the substrate layer, also known as a diffusion layer, and is formed with a P-well layer and an N-well layer by ion implantation; the P-well layer comprises a lightly doped P-well layer 1 and a heavily doped P-well layer 1, wherein the heavily doped P-well layer 1 extends to the bottom of the semiconductor epitaxial layer and contacts the substrate layer;

[0008] A groove is etched between adjacent MOS cells in the middle of the heavily doped P-well layer 1, the bottom of the groove may or may not extend to the substrate layer, an oxide layer is deposited at the bottom of the groove, a side metal source is provided on the surface of the oxide layer and the top of the groove, the top of the side metal source is in contact with the upper metal source; the side surface of the side metal source is in ohmic contact with the N-well layer, the lightly doped P-well layer 1 and the heavily doped P-well layer 1;

[0009] The gate is a longitudinal trench gate, which is arranged between two N-well layers and two lightly doped P-well layers of a single MOS cell, and the trench gate is connected to the side of the N-well layer, the side of the lightly doped P-well layer and the diffusion layer through gate oxide layer isolation; the upper surface of the trench gate is isolated from the upper metal source by a dielectric layer.

[0010] Further, the substrate layer is arranged on the drain surface, the heavily doped P well layer 1 and the diffusion layer are arranged on the substrate layer surface, and the heavily doped P well layer 1 is respectively arranged on both sides of a single MOS cell, the diffusion layer is located in the middle of the heavily doped P well layer 1 located on both sides of the single MOS cell, the lightly doped P well layer 1 is arranged on the surfaces of the diffusion layer and the heavily doped P well layer 1, and are respectively connected to the diffusion layer and the heavily doped P well layer 1, and the N well layer is located on the surface of the lightly doped P well layer 1, and is connected to the lightly doped P well layer 1;

[0011] The upper surface of the trench gate is isolated from the upper metal source by a dielectric layer;

[0012] The dielectric layers of adjacent MOS cells are isolated by the upper metal source.

[0013] Furthermore, the N well layer includes a lightly doped N well layer 1 and a heavily doped N well layer 1, wherein the heavily doped N well layer 1 is located on the upper layer of the lightly doped N well layer 1; the lightly doped N well layer 1 is located on the surface of the lightly doped P well layer 1, the side of the side metal source is in ohmic contact with the lightly doped N well layer 1, the heavily doped N well layer 1, the lightly doped P well layer 1 and the heavily doped P well layer 1, the trench gate is arranged between two heavily doped N well layers 1, two lightly doped N well layers 1 and two lightly doped P well layers 1 of a single MOS cell, and the trench gate is connected to the side of the heavily doped N well layer 1, the side of the lightly doped N well layer 1, the side of the lightly doped P well layer 1 and the diffusion layer through gate oxide layer isolation.

[0014] Furthermore, the height of the oxide layer filled in the trench is lower than the bottom cross-sectional height of the lightly-doped P-well layer 1, so that the side metal source can contact the heavily-doped P-well layer 1.

[0015] More preferably, the groove is perpendicular to the substrate layer.

[0016] Furthermore, the depth of the trench gate is greater than the depth of the lightly doped P-well layer 1, so that the trench gate can contact the diffusion layer.

[0017] The present invention sets a silicon oxide insulating layer in the middle of the original P+ injection area. When the super junction structure is in a blocking state, the oxide layer bears pressure together with the device. It will not cause the device's withstand voltage characteristics to decrease. In the device manufacturing process, the setting of the oxide layer can greatly reduce the requirements for the ion implanter in the super junction structure manufacturing process. The present invention converts the source ohmic contact buried from horizontal to vertical, which can greatly reduce the cell size occupied by the source contact. There is no longer a horizontal gate-source alternating structure in the structure of the present invention, eliminating any concerns caused by the gate-source horizontal isolation dielectric layer. The structure of the present invention adopts a groove structure in the channel, converting the planar channel into a vertical channel, eliminating the cell size occupied by the channel. The structure of the present invention uses an oxide layer isolation at the top of the gate instead of direct isolation in the U groove, with the purpose of causing the device surface to be uneven. This shape helps to release the thermal stress generated when the device temperature rises, and improves the reliability of the device's high temperature resistance.

[0018] The present invention also provides a method for manufacturing the double-trench super junction structure, the method comprising the following steps:

[0019] S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them;

[0020] S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation;

[0021] S3. Between adjacent MOS cells, a reserved heavily doped P-well layer is etched to form a groove. The depth and width of the groove can be set according to the specific device design.

[0022] S4, performing multiple implantations at multiple angles to obtain a heavily doped P-well layer 1 that meets the specifications;

[0023] S5, depositing an oxide layer in the trench, filling the trench to a height lower than the bottom cross-sectional height of the lightly doped P-well layer 1, and then depositing metal into the trench to prepare a side metal source electrode, so that the side metal source electrode fills the trench and the top can contact the upper metal source electrode;

[0024] S6. Complete the remaining parts of the device according to the normal process.

[0025] In the step S6, the trench gate, dielectric layer and upper metal source are generally manufactured according to normal processes.

[0026] In the step S5, the oxide layer may be deposited using an oxide layer deposition device.

[0027] Furthermore, in step S3, by inspecting the average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench, it is determined whether the substrate epitaxial layer trench etching process is qualified, and:

[0028]

[0029] In the formula, C represents the yield rate of the trench etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched trench, and g represents the existence rate of cracks in the inner surface of the trench;

[0030] When C≥80%, it means that the process of performing trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

[0031] Furthermore, in step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating.

[0032]

[0033] In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where the larger h is, the worse the verticality of the groove is; m represents the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u represents the maximum inclination angle of the groove side wall after heating.

[0034] The beneficial effects of the present invention are:

[0035] The present invention solves for the first time the problem of the difficulty of the super junction device manufacturing process. By increasing the groove etching, the injection port of the implanter can penetrate deep into the groove, so that when the maximum injection depth of the implanter remains unchanged, the injection depth of the heavily doped P-well layer 1 is increased through the groove, making it possible to manufacture the heavily doped P-well layer 1 with an injection depth greater than the maximum injection depth of the implanter. This greatly reduces the requirements of the super junction device for the implanter, significantly reduces the difficulty of manufacturing super junction devices, lowers the threshold for manufacturing super junction devices, and lays a solid foundation for the industrial application of super junction devices.

[0036] The present invention changes the source ohmic contact from being buried horizontally to vertically, greatly reducing the cell size occupied by the source contact; and eliminates the horizontal gate-source alternating structure, thereby eliminating any concerns caused by the gate-source horizontal isolation dielectric layer.

[0037] The structure of the present invention adopts a U-groove structure in the channel, converts the planar channel into a longitudinal channel, and eliminates the cell size occupied by the channel.

[0038] The structure of the present invention adopts a (11-20) surface channel, which can significantly reduce the interface state density, increase the device service life, and increase the device reliability; improve the device mobility, increase the device unit cell current flux, further increase the device current density, and reduce the overall size of the device.

[0039] The structure of the present invention uses an oxide layer for isolation on the surface of the trench gate, thereby improving the high temperature resistance reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a schematic diagram of the structure of the super junction structure in which the oxide layer fills the trench in Example 1.

[0041] Figure 2 Schematic cross-sectional view of the double-trench super junction structure of the present invention in Example 2.

[0042] Figure 3 It is a comparison diagram of the cross-sectional structures of Example 1 and Example 2.

[0043] Figure 4 It is a cross-sectional schematic diagram of the super junction structure in which the gate-source lateral alternating structure is eliminated in Example 3.

[0044] Figure 5 It is a cross-sectional structure comparison diagram of Example 2 and Example 3.

[0045] In the figure: 1. drain; 2. upper metal source; 3. dielectric layer; 4. gate; 41. trench gate; 5. side metal source; 6. oxide layer; 61. trench; 7. lightly doped P-well layer 1; 8. heavily doped P-well layer 1; 9. diffusion layer; 10. lightly doped N-well layer 1; 11. heavily doped N-well layer 1; 12. substrate layer. DETAILED DESCRIPTION

[0046] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments, but the protection scope of the present invention is not limited thereto. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0047] Example 1

[0048] The schematic diagram of the super junction structure with the oxide layer filling the trench is as follows Figure 1 As shown, it includes several MOS cells connected in parallel, and a single MOS cell includes a drain 1, an upper metal source 2, a gate 3, a semiconductor epitaxial layer, and a substrate layer 12. The surface of the gate 4 is provided with a dielectric layer 3; the semiconductor epitaxial layer is located on the surface of the substrate layer 12, also known as the diffusion layer 9, and is formed with a P well layer and an N well layer by ion implantation; the P well layer includes a lightly doped P well layer 7 and a heavily doped P well layer 8, wherein the heavily doped P well layer 8 extends to the bottom of the diffusion layer 9 and contacts with the substrate layer 12.

[0049] The gate 4 is arranged inside the upper metal source 2 and is isolated from the upper metal source 2 by a dielectric layer 3;

[0050] The substrate layer 12 is located on the surface of the drain 1, the heavily doped P well layer 8 and the diffusion layer 9 are located on the surface of the substrate layer 12, and the heavily doped P well layer 8 is respectively arranged on both sides of a single MOS cell, the diffusion layer 9 is located in the middle of the heavily doped P well layer 8 located on both sides of the single MOS cell, the lightly doped P well layer 7 is located on the surface of the diffusion layer 9 and the heavily doped P well layer 8, and is respectively connected to the diffusion layer 9 and the heavily doped P well layer 8, the N well layer is located on the surface of the lightly doped P well layer 7, Figure 1 In the embodiment of the present invention, the N well layer includes a lightly doped N well layer 10 and a heavily doped N well layer 11, wherein the heavily doped N well layer 11 is located on the upper layer of the lightly doped N well layer 10; the lightly doped N well layer 10 is located on the surface of the lightly doped P well layer 7, and is connected to the lightly doped P well layer 7 and the heavily doped P well layer 8 respectively; the heavily doped N well layer 11 is connected to the heavily doped P well layer 8, and the gate 4 is isolated and connected to the upper surface of the heavily doped N well layer 11, the lightly doped P well layer 7 and the surface of the diffusion layer 9 through the dielectric layer 3;

[0051] The upper metal source 2 is connected to the upper surface of the heavily doped N-well layer 11 and the upper surface of the heavily doped P-well layer 8;

[0052] Between adjacent MOS cells, a groove 61 is etched in the middle of the heavily doped P-well layer 8, the bottom of the groove 61 extends to the substrate layer 12, and the top of the groove 61 contacts the upper metal source 2; an oxide layer 6 is deposited inside the groove, the oxide layer 6 fills the groove 61, and when the super junction structure is in a blocking state, the oxide layer 6 is under pressure together with the device.

[0053] Figure 1 The bottom of the groove 61 shown extends to the substrate layer 12, but the groove 61 may not extend to the substrate layer 12, because considering the implantation depth that the implanter can reach, the depth of the groove only needs to ensure that the impurities injected by the implanter can reach the bottom of the diffusion layer and the surface of the substrate layer. That is, the depth of the groove 61 can be greater than or equal to the target implantation depth minus the maximum implantation depth of the implanter.

[0054] By increasing the groove etching, the injection port of the implanter can penetrate deeper into the groove, thereby increasing the injection depth of the heavily doped P-well layer 1 through the groove while keeping the maximum injection depth of the implanter unchanged, making it possible to manufacture a heavily doped P-well layer 1 with an injection depth greater than the maximum injection depth of the implanter.

[0055] However, the device cell size of this structure needs to be further reduced, and there are still problems such as high planar channel interface state and low planar mobility. There is room for further improvement, as shown in Example 2.

[0056] Example 2

[0057] This embodiment provides a double-trench super junction structure, the cross-sectional structure diagram is as follows Figure 2 As shown, it includes several MOS cells connected in parallel, and a single MOS cell includes a drain 1, an upper metal source 2, a gate, a semiconductor epitaxial layer, and a substrate layer 12, wherein the gate is a longitudinal trench gate 41; the semiconductor epitaxial layer is located on the surface of the substrate layer 12, also known as the diffusion layer 9, and is formed with a P-well layer and an N-well layer by ion implantation; the P-well layer includes a lightly doped P-well layer 7 and a heavily doped P-well layer 8, wherein the heavily doped P-well layer 8 extends to the bottom of the diffusion layer 9 and contacts the substrate layer 12.

[0058] Between adjacent MOS cells, a groove 61 is etched in the middle of the heavily doped P-well layer 8, and the bottom of the groove 61 extends or does not extend to the substrate layer 12. In this embodiment, the groove 61 does not extend to the substrate layer 12, and an oxide layer 6 is deposited at the bottom of the groove 61. A side metal source 5 is provided on the surface of the oxide layer 6 and the top of the groove 61, and the top of the side metal source 5 is in contact with the upper metal source 2; the side of the side metal source 5 is in ohmic contact with the N-well layer, the lightly doped P-well layer 7 and the heavily doped P-well layer 8.

[0059] Further, the substrate layer 12 is arranged on the surface of the drain 1, the heavily doped P well layer 8 and the diffusion layer 9 are arranged on the surface of the substrate layer 12, and the heavily doped P well layer 8 is respectively arranged on both sides of a single MOS cell, the diffusion layer 9 is located in the middle of the heavily doped P well layer 8 located on both sides of the single MOS cell, the lightly doped P well layer 7 is arranged on the surface of the diffusion layer 9 and the heavily doped P well layer 8, and is respectively connected to the diffusion layer 9 and the heavily doped P well layer 8, the N well layer is located on the surface of the lightly doped P well layer 7, Figure 2 In the embodiment of the present invention, the N well layer includes a lightly doped N well layer 10 and a heavily doped N well layer 11, wherein the heavily doped N well layer 11 is located on the upper layer of the lightly doped N well layer 10; the lightly doped N well layer 10 is located on the surface of the lightly doped P well layer 7; the side surface of the side metal source 5 is in ohmic contact with the lightly doped N well layer 10 and the heavily doped N well layer 11, the lightly doped P well layer 7 and the heavily doped P well layer 8;

[0060] The gate is a longitudinal trench gate 41, which is disposed between two heavily doped N-well layers 11, two lightly doped N-well layers 10, and two lightly doped P-well layers 7 of a single MOS cell, and the gate is connected to the side of the heavily doped N-well layer 11, the side of the lightly doped N-well layer 10, the side of the lightly doped P-well layer 7, and the diffusion layer 9 through gate oxide layer isolation;

[0061] The upper surface of the trench gate 41 is isolated from the upper metal source 2 by a dielectric layer 3;

[0062] The dielectric layers 3 of adjacent MOS cells are isolated by the upper metal source 2 .

[0063] The height of the oxide layer 6 filled in the groove 61 is lower than the bottom cross-sectional height of the lightly doped P-well layer 7 , so that the side gold metal source 5 can contact the heavily doped P-well layer 8 .

[0064] More preferably, the groove 61 is perpendicular to the substrate layer 12 .

[0065] The depth of the trench gate 41 is greater than the depth of the lightly doped P-well layer 7 , so that the trench gate 41 can contact the diffusion layer 9 .

[0066] When the super junction structure is in a blocking state, the oxide layer bears pressure together with the device.

[0067] The double-trench super junction structure is prepared by the following method:

[0068] S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them;

[0069] S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation;

[0070] S3. Between adjacent MOS cells, a reserved heavily doped P-well layer is etched to form a groove. The depth and width of the groove can be set according to the specific device design.

[0071] In step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating, and:

[0072]

[0073] In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where the larger h is, the worse the verticality of the groove is; m represents the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u represents the maximum inclination angle of the groove side wall after heating.

[0074] Among them, for the semiconductor substrate layer, the ratio of the cross-sectional width at the bottom of the trench to the cross-sectional width at the top is m=1.5, and the maximum inclination angle of the trench sidewall after heating is u=4.2 (degrees), then:

[0075]

[0076] From the above calculation, it can be known that the vertical coefficient of the inner wall of the trench etched by the semiconductor substrate layer is h=1.8.

[0077] The average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench are inspected to determine whether the substrate epitaxial layer trench etching process is qualified.

[0078]

[0079] In the formula, C represents the yield rate of the trench etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched trench, and g represents the existence rate of cracks in the inner surface of the trench;

[0080] When C≥80%, it means that the process of performing trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

[0081] Among them, the average width of the trench etched for the substrate epitaxial layer is d=3.4 (micrometers), the target width of the etched trench is d0=2 (micrometers), and the existence rate of cracks in the inner surface of the trench is g=35% (the existence rate of cracks = the number of substrate epitaxial layers with more than 10 cracks in the trench ÷ the number of sampled substrate epitaxial layers), then:

[0082]

[0083] From the above calculations, it can be known that the process of trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

[0084] S4. Perform multiple injections at multiple angles to obtain a heavily doped P-well layer 1 that meets the specifications. Multiple injections at multiple angles can be performed by rotating the wafer and tilting it.

[0085] S5, depositing an oxide layer in the trench, filling the trench to a height lower than the bottom cross-sectional height of the lightly doped P-well layer 1, and then depositing metal into the trench to prepare a side metal source electrode, so that the side metal source electrode fills the trench and its top can contact the upper metal source electrode; the oxide layer can be deposited using an oxide layer deposition device

[0086] S6. Complete the production of the trench gate, dielectric layer and upper metal source according to normal process.

[0087] In this embodiment, a side metal source is designed, and the source ohmic contact is designed in the vertical direction within the epitaxial layer. The adjacent P hydrazine layer, lightly doped P well layer 1 and heavily doped P well layer 1 can directly contact the side metal source, so that adjacent MOS cells do not need to be isolated by heavily doped P well layer 1, and the design structure is more compact, greatly reducing the cell size occupied by the source contact. The lateral alternating gate-source structure is eliminated, thereby eliminating any concerns caused by the gate-source lateral isolation dielectric layer. The structure of the present invention adopts a groove structure in the channel, converting the planar channel into a longitudinal channel, eliminating the cell size occupied by the channel, and can further reduce the size.

[0088] The design comparison diagram of the two structures of Example 1 and Example 2 is as follows Figure 3 As shown, it can be seen that the distance between adjacent MOS cells in Example 2 is significantly reduced, and the cell size is also reduced.

[0089] Example 3

[0090] As a comparison, this embodiment provides another low-resistance super junction structure that eliminates the gate-source lateral alternating structure, and the cross-sectional schematic diagram is shown in FIG. Figure 4 As shown, it includes several MOS cells connected in parallel, and a single MOS cell includes a drain 1, an upper metal source 2, a gate 4, a semiconductor epitaxial layer, and a substrate layer 12. The surface of the gate 4 is provided with a dielectric layer 3; the semiconductor epitaxial layer is located on the surface of the substrate layer 12, also known as the diffusion layer 9, and is formed with a P well layer and an N well layer by ion implantation; the P well layer includes a lightly doped P well layer 7 and a heavily doped P well layer 8, wherein the heavily doped P well layer 8 extends to the bottom of the diffusion layer 9 and contacts with the substrate layer 12.

[0091] Between adjacent MOS cells, in the middle of the heavily doped P-well layer 8, a groove 61 is etched to form, the bottom of the groove 61 may or may not extend to the substrate layer 12, and in this embodiment, it is chosen not to extend to the substrate layer, an oxide layer 6 is deposited at the bottom of the groove 61, and a side metal source 5 is provided on the surface of the oxide layer 6 and the top of the groove 61, the top of the side metal source 5 is in contact with the dielectric layer 3, and the top of the side metal source 5 is in unified lead-out contact with the upper metal source 2 in the main junction region; the side surface of the side metal source 5 is in ohmic contact with the N-well layer, the lightly doped P-well layer 7 and the heavily doped P-well layer 8.

[0092] The substrate layer 12 is arranged on the surface of the drain 1, the heavily doped P well layer 8 and the diffusion layer 9 are arranged on the surface of the substrate layer 12, and the heavily doped P well layer 8 is respectively arranged on both sides of a single MOS cell, the diffusion layer 9 is located in the middle of the heavily doped P well layer 8 located on both sides of the single MOS cell, the lightly doped P well layer 7 is arranged on the surface of the diffusion layer 9 and the heavily doped P well layer 8, and is respectively connected to the diffusion layer 9 and the heavily doped P well layer 8, the N well layer is located on the surface of the lightly doped P well layer 7, Figure 4 In the embodiment of the present invention, the N well layer includes a lightly doped N well layer 10 and a heavily doped N well layer 11, wherein the heavily doped N well layer 11 is located on the upper layer of the lightly doped N well layer 10; the lightly doped N well layer 10 is located on the surface of the lightly doped P well layer 7; the side surface of the side metal source 5 is in ohmic contact with the lightly doped N well layer 10 and the heavily doped N well layer 11, the lightly doped P well layer 7 and the heavily doped P well layer 8, and the gate 4 is isolated and connected with the upper surface of the heavily doped N well layer 11, the lightly doped P well layer 7 and the surface of the diffusion layer 9 through the dielectric layer 3;

[0093] Furthermore, the height of the oxide layer 6 filled in the trench 61 is lower than the bottom cross-sectional height of the lightly-doped P-well layer 7 , so that the side metal source 5 can contact the heavily-doped P-well layer 8 .

[0094] The groove 61 is perpendicular to the substrate layer 12 .

[0095] In this embodiment, the dielectric layer 3 forms a laterally continuous dielectric layer, the gate 4 is arranged inside the dielectric layer 3, adjacent gates 4 are isolated by the dielectric layer 3, and no gate-source alternating structure is formed. The upper metal source 2 is arranged on the upper surface of the dielectric layer 3.

[0096] The structural comparison diagram of Example 3 and Example 2 is as follows Figure 5 As shown, it can be seen that, under the condition of the same width of the N-hydrazine layer, Example 2 adopts the design of the trench gate, converts the planar channel into a longitudinal channel, eliminates the cell size occupied by the channel, and further reduces the cell size compared with Example 3. Moreover, the (11-20) surface channel can significantly reduce the interface state density, increase the device service life, and increase the device reliability; improve the device mobility, increase the current flux of the device unit cell, further increase the device current density, and reduce the overall size of the device.

Claims

1. A double-slot superjunction structure, comprising a plurality of MOS cells connected in parallel, characterized in that A single MOS cell includes a drain, an upper metal source, a gate, a semiconductor epitaxial layer, and a substrate layer; the semiconductor epitaxial layer is located on the surface of the substrate layer, also known as a diffusion layer, and is formed with a P-well layer and an N-well layer by ion implantation; the P-well layer includes a lightly doped P-well layer 1 and a heavily doped P-well layer 1, wherein the heavily doped P-well layer 1 extends to the bottom of the semiconductor epitaxial layer and contacts the substrate layer; A groove is etched between adjacent MOS cells in the middle of the heavily doped P-well layer 1, the bottom of the groove may or may not extend to the substrate layer, an oxide layer is deposited at the bottom of the groove, a side metal source is provided on the surface of the oxide layer and the top of the groove, the top of the side metal source is in contact with the upper metal source; the side surface of the side metal source is in ohmic contact with the N-well layer, the lightly doped P-well layer 1 and the heavily doped P-well layer 1; The gate is a longitudinal trench gate, which is arranged between two N-well layers and two lightly doped P-well layers of a single MOS cell, and the trench gate is connected to the side of the N-well layer, the side of the lightly doped P-well layer, and the diffusion layer through gate oxide layer isolation; the upper surface of the trench gate is isolated from the upper metal source by a dielectric layer.

2. The double-trench super junction structure according to claim 1, characterized in that The substrate layer is arranged on the drain surface, the heavily doped P-well layer 1 and the diffusion layer are arranged on the substrate layer surface, and the heavily doped P-well layer 1 is respectively arranged on both sides of a single MOS cell, the diffusion layer is located in the middle of the heavily doped P-well layer 1 located on both sides of the single MOS cell, the lightly doped P-well layer 1 is arranged on the surfaces of the diffusion layer and the heavily doped P-well layer 1, and are respectively connected to the diffusion layer and the heavily doped P-well layer 1, and the N-well layer is located on the surface of the lightly doped P-well layer 1, and is connected to the lightly doped P-well layer 1.

3. The double-trench super junction structure according to claim 2, characterized in that The N-well layer includes a lightly doped N-well layer 1 and a heavily doped N-well layer 1, wherein the heavily doped N-well layer 1 is located on the upper layer of the lightly doped N-well layer 1; the lightly doped N-well layer 1 is located on the surface of the lightly doped P-well layer 1, the side of the side metal source is in ohmic contact with the lightly doped N-well layer 1, the heavily doped N-well layer 1, the lightly doped P-well layer 1 and the heavily doped P-well layer 1, the trench gate is arranged between two heavily doped N-well layers 1, two lightly doped N-well layers 1 and two lightly doped P-well layers 1 of a single MOS cell, and the trench gate is connected to the side of the heavily doped N-well layer 1, the side of the lightly doped N-well layer 1, the side of the lightly doped P-well layer 1 and the diffusion layer through gate oxide layer isolation.

4. The double-trench super junction structure according to claim 1, characterized in that The dielectric layers of the adjacent MOS cells are isolated by an upper metal source.

5. The double-trench super junction structure according to claim 1, characterized in that The height of the oxide layer filled in the trench is lower than the bottom cross-sectional height of the lightly doped P-well layer 1, so that the side metal source is in contact with the heavily doped P-well layer 1.

6. The double-trench super junction structure according to claim 1, characterized in that The depth of the trench gate is greater than the depth of the lightly doped P-well layer 1, so that the trench gate is in contact with the diffusion layer.

7. The double-trench super junction structure according to claim 1, characterized in that When the super junction structure is in a blocking state, the oxide layer bears pressure together with the device.

8. The method for manufacturing a double-trench super junction structure according to any one of claims 1 to 7, characterized in that The method comprises the following steps: S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them; S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation; S3, between adjacent MOS cells, a reserved heavily doped P-well layer is etched to form a groove; S4, performing multiple implantations at multiple angles to obtain a heavily doped P-well layer 1 that meets the specifications; S5, depositing an oxide layer in the trench, filling the trench to a height lower than the bottom cross-sectional height of the lightly doped P-well layer 1, and then depositing metal into the trench to prepare a side metal source electrode, so that the side metal source electrode fills the trench and the top can contact the upper metal source electrode; S6. Complete the remaining parts of the device according to the normal process.

9. The method according to claim 8, characterized in that In step S3, by inspecting the average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench, it is determined whether the substrate epitaxial layer trench etching process is qualified, as follows: In the formula, C represents the yield rate of the trench etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched trench, and g represents the existence rate of cracks in the inner surface of the trench; When C≥80%, it means that the process of performing trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

10. The method according to claim 9, characterized in that In step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating. In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where the larger h is, the worse the verticality of the groove is; m represents the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u represents the maximum inclination angle of the groove side wall after heating.

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